diff --git a/lib/Target/SparcV9/SparcV9.td b/lib/Target/SparcV9/SparcV9.td index b2d412c3c0e..d9114a8125e 100644 --- a/lib/Target/SparcV9/SparcV9.td +++ b/lib/Target/SparcV9/SparcV9.td @@ -13,10 +13,10 @@ include "SparcV9_Reg.td" class InstV9 : Instruction { // Sparc instruction baseline field bits<32> Inst; - set Namespace = "V9"; + let Namespace = "V9"; bits<2> op; - set Inst{31-30} = op; // Top two bits are the 'op' field + let Inst{31-30} = op; // Top two bits are the 'op' field // Bit attributes specific to Sparc instructions bit isPasi = 0; // Does this instruction affect an alternate addr space? @@ -43,7 +43,7 @@ def ADDCccr : F3_1<2, 0b011000, "addCcc">; // addCcc rs1, rs2, rd def ADDCcci : F3_2<2, 0b011000, "addCcc">; // addCcc rs1, imm, rd // Section A.3: Branch on Integer Register with Prediction - p138 -set op2 = 0b011 in { +let op2 = 0b011 in { def BRZ : F2_4<0b001, "brz">; // Branch on rs1 == 0 def BRLEZ : F2_4<0b010, "brlez">; // Branch on rs1 <= 0 def BRLZ : F2_4<0b011, "brlz">; // Branch on rs1 < 0 @@ -55,8 +55,8 @@ set op2 = 0b011 in { // Section A.4: Branch on Floating-Point Condition Codes (FBfcc) p140 // The following deprecated instructions don't seem to play nice on Sparc /* -set isDeprecated = 1 in { - set op2 = 0b110 in { +let isDeprecated = 1 in { + let op2 = 0b110 in { def FBA : F2_2<0b1000, "fba">; // Branch always def FBN : F2_2<0b0000, "fbn">; // Branch never def FBU : F2_2<0b0111, "fbu">; // Branch on unordered @@ -78,7 +78,7 @@ set isDeprecated = 1 in { */ // We now make these same opcodes represent the FBPfcc instructions -set op2 = 0b101 in { +let op2 = 0b101 in { def FBA : F2_3<0b1000, "fba">; // Branch always def FBN : F2_3<0b0000, "fbn">; // Branch never def FBU : F2_3<0b0111, "fbu">; // Branch on unordered @@ -100,7 +100,7 @@ set op2 = 0b101 in { // Section A.5: Branch on FP condition codes with prediction - p143 // Not used in the Sparc backend (directly) /* -set op2 = 0b101 in { +let op2 = 0b101 in { def FBPA : F2_3<0b1000, "fba">; // Branch always def FBPN : F2_3<0b0000, "fbn">; // Branch never def FBPU : F2_3<0b0111, "fbu">; // Branch on unordered @@ -122,8 +122,8 @@ set op2 = 0b101 in { // Section A.6: Branch on Integer condition codes (Bicc) - p146 /* -set isDeprecated = 1 in { - set op2 = 0b010 in { +let isDeprecated = 1 in { + let op2 = 0b010 in { def BA : F2_2<0b1000, "ba">; // Branch always def BN : F2_2<0b0000, "bn">; // Branch never def BNE : F2_2<0b1001, "bne">; // Branch != @@ -145,8 +145,8 @@ set isDeprecated = 1 in { */ // Using the format of A.7 instructions... -set op2 = 0b001 in { - set cc = 0 in { // BA and BN don't read condition codes +let op2 = 0b001 in { + let cc = 0 in { // BA and BN don't read condition codes def BA : F2_3<0b1000, "ba">; // Branch always def BN : F2_3<0b0000, "bn">; // Branch never } @@ -169,7 +169,7 @@ set op2 = 0b001 in { // Section A.7: Branch on integer condition codes with prediction - p148 // Not used in the Sparc backend /* -set op2 = 0b001 in { +let op2 = 0b001 in { def BPA : F2_3<0b1000, "bpa">; // Branch always def BPN : F2_3<0b0000, "bpn">; // Branch never def BPNE : F2_3<0b1001, "bpne">; // Branch != @@ -192,10 +192,10 @@ set op2 = 0b001 in { // Section A.8: CALL - p151, the only Format #1 instruction def CALL : InstV9 { bits<30> disp; - set op = 1; - set Inst{29-0} = disp; - set Name = "call"; - set isCall = 1; + let op = 1; + let Inst{29-0} = disp; + let Name = "call"; + let isCall = 1; } // Section A.9: Compare and Swap - p176 @@ -205,7 +205,7 @@ def CALL : InstV9 { // Section A.10: Divide (64-bit / 32-bit) - p178 // Not used in the Sparc backend /* -set isDeprecated = 1 in { +let isDeprecated = 1 in { def UDIVr : F3_1<2, 0b001110, "udiv">; // udiv r, r, r def UDIVi : F3_2<2, 0b001110, "udiv">; // udiv r, r, i def SDIVr : F3_1<2, 0b001111, "sdiv">; // sdiv r, r, r @@ -220,7 +220,7 @@ set isDeprecated = 1 in { // Section A.11: DONE and RETRY - p181 // Not used in the Sparc backend /* -set isPrivileged = 1 in { +let isPrivileged = 1 in { def DONE : F3_18<0, "done">; // done def RETRY : F3_18<1, "retry">; // retry } @@ -321,13 +321,13 @@ def LDDFr : F3_1<3, 0b100011, "ldd">; // ldd [rs1+rs2], rd def LDDFi : F3_2<3, 0b100011, "ldd">; // ldd [rs1+imm], rd def LDQFr : F3_1<3, 0b100010, "ldq">; // ldq [rs1+rs2], rd def LDQFi : F3_2<3, 0b100010, "ldq">; // ldq [rs1+imm], rd -set isDeprecated = 1 in { - set rd = 0 in { +let isDeprecated = 1 in { + let rd = 0 in { def LDFSRr : F3_1<3, 0b100001, "ld">; // ld [rs1+rs2], rd def LDFSRi : F3_2<3, 0b100001, "ld">; // ld [rs1+imm], rd } } -set rd = 1 in { +let rd = 1 in { def LDXFSRr : F3_1<3, 0b100001, "ldx">; // ldx [rs1+rs2], rd def LDXFSRi : F3_2<3, 0b100001, "ldx">; // ldx [rs1+imm], rd } @@ -349,7 +349,7 @@ def LDUWi : F3_2<3, 0b000000, "lduw">; // lduw [rs1+imm], rd def LDXr : F3_1<3, 0b001011, "ldx">; // ldx [rs1+rs2], rd def LDXi : F3_2<3, 0b001011, "ldx">; // ldx [rs1+imm], rd /* -set isDeprecated = 1 in { +let isDeprecated = 1 in { def LDDr : F3_1<3, 0b000011, "ldd">; // ldd [rs1+rs2], rd def LDDi : F3_2<3, 0b000011, "ldd">; // ldd [rs1+imm], rd } @@ -615,13 +615,13 @@ def UDIVXi : F3_2<2, 0b001101, "udivx">; // udivx r, i, r // Section A.38: Multiply (32-bit) - p200 // Not used in the Sparc backend /* -set Inst{13} = 0 in { +let Inst{13} = 0 in { def UMULr : F3_1<2, 0b001010, "umul">; // umul r, r, r def SMULr : F3_1<2, 0b001011, "smul">; // smul r, r, r def UMULCCr : F3_1<2, 0b011010, "umulcc">; // mulcc r, r, r def SMULCCr : F3_1<2, 0b011011, "smulcc">; // smulcc r, r, r } -set Inst{13} = 1 in { +let Inst{13} = 1 in { def UMULi : F3_1<2, 0b001010, "umul">; // umul r, i, r def SMULi : F3_1<2, 0b001011, "smul">; // smul r, i, r def UMULCCi : F3_1<2, 0b011010, "umulcc">; // umulcc r, i, r @@ -634,9 +634,9 @@ set Inst{13} = 1 in { // Section A.40: No operation - p204 // NOP is really a pseudo-instruction (special case of SETHI) -set op2 = 0b100 in { - set rd = 0 in { - set imm = 0 in { +let op2 = 0b100 in { + let rd = 0 in { + let imm = 0 in { def NOP : F2_1<"nop">; // nop } } @@ -653,12 +653,12 @@ set op2 = 0b100 in { // Section A.44: Read State Register // The only instr from this section currently used is RDCCR -set rs1 = 2 in { +let rs1 = 2 in { def RDCCR : F3_17<2, 0b101000, "rd">; // rd %ccr, r } // Section A.45: RETURN - p216 -set isReturn = 1 in { +let isReturn = 1 in { def RETURNr : F3_3<2, 0b111001, "return">; // return def RETURNi : F3_4<2, 0b111001, "return">; // return } @@ -673,7 +673,7 @@ def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r // Not currently used in Sparc backend // Section A.48: SETHI - p220 -set op2 = 0b100 in { +let op2 = 0b100 in { def SETHI : F2_1<"sethi">; // sethi } @@ -681,7 +681,7 @@ set op2 = 0b100 in { // Not currently used in the Sparc backend /* uses 5 least significant bits of rs2 -set x = 0 in { +let x = 0 in { def SLLr5 : F3_11<2, 0b100101, "sll">; // sll r, r, r def SRLr5 : F3_11<2, 0b100110, "srl">; // srl r, r, r def SRAr5 : F3_11<2, 0b100111, "sra">; // sra r, r, r @@ -692,12 +692,12 @@ set x = 0 in { */ // uses 6 least significant bits of rs2 -set x = 0 in { +let x = 0 in { def SLLr5 : F3_11<2, 0b100101, "sll">; // sll r, r, r def SRLr5 : F3_11<2, 0b100110, "srl">; // srl r, r, r def SRAr5 : F3_11<2, 0b100111, "sra">; // sra r, r, r } -set x = 1 in { +let x = 1 in { def SLLXr6 : F3_11<2, 0b100101, "sllx">; // sllx r, r, r def SRLXr6 : F3_11<2, 0b100110, "srlx">; // srlx r, r, r def SRAXr6 : F3_11<2, 0b100111, "srax">; // srax r, r, r @@ -733,7 +733,7 @@ def STQFi : F3_2rd<3, 0b100110, "stq">; // stq r, [r+i] // while STXFSRx expect rd=1, but assembly syntax dictates %fsr as first arg. // These are being disabled because they aren't used in the Sparc backend. /* -set isDeprecated = 1 in { +let isDeprecated = 1 in { def STFSRr : F3_1<3, 0b100101, "st">; // st %fsr, [r+r] def STFSRi : F3_2<3, 0b100101, "st">; // st %fsr, [r+i] } @@ -771,7 +771,7 @@ def SUBCcci : F3_2<2, 0b011100, "subccc">; // subccc r, i, r // FIXME: More...? // Section A.63: Write State Register - p244 -set rd = 2 in { +let rd = 2 in { def WRCCRr : F3_1<2, 0b110000, "wr">; // wr r, r, %y/ccr/etc def WRCCRi : F3_2<2, 0b110000, "wr">; // wr r, i, %y/ccr/etc } diff --git a/lib/Target/SparcV9/SparcV9_F2.td b/lib/Target/SparcV9/SparcV9_F2.td index e84146a461f..a9cd247062f 100644 --- a/lib/Target/SparcV9/SparcV9_F2.td +++ b/lib/Target/SparcV9/SparcV9_F2.td @@ -7,8 +7,8 @@ // class F2 : InstV9 { // Format 2 instructions bits<3> op2; - set op = 0; // Op = 0 - set Inst{24-22} = op2; + let op = 0; // Op = 0 + let Inst{24-22} = op2; } // Format 2.1 instructions @@ -16,23 +16,23 @@ class F2_1 : F2 { bits<22> imm; bits<5> rd; - set Name = name; - set Inst{29-25} = rd; - set Inst{21-0} = imm; + let Name = name; + let Inst{29-25} = rd; + let Inst{21-0} = imm; } class F2_br : F2 { // Format 2 Branch instruction - set isBranch = 1; // All instances are branch instructions + let isBranch = 1; // All instances are branch instructions } class F2_2 cond, string name> : F2_br { // Format 2.2 instructions bits<22> disp; bit annul; - set Name = name; - set Inst{29} = annul; - set Inst{28-25} = cond; - set Inst{21-0} = disp; + let Name = name; + let Inst{29} = annul; + let Inst{28-25} = cond; + let Inst{21-0} = disp; } class F2_3 cond, string name> : F2_br { // Format 2.3 instructions @@ -41,12 +41,12 @@ class F2_3 cond, string name> : F2_br { // Format 2.3 instructions bit predict = 1; bit annul; - set Name = name; - set Inst{29} = annul; - set Inst{28-25} = cond; - set Inst{21-20} = cc; - set Inst{19} = 1; // predict; - set Inst{18-0} = disp; + let Name = name; + let Inst{29} = annul; + let Inst{28-25} = cond; + let Inst{21-20} = cc; + let Inst{19} = 1; // predict; + let Inst{18-0} = disp; } class F2_4 rcond, string name> : F2_br { // Format 2.4 instructions @@ -55,12 +55,12 @@ class F2_4 rcond, string name> : F2_br { // Format 2.4 instructions bit predict = 1; bit annul; - set Name = name; - set Inst{29} = annul; - set Inst{28} = 0; - set Inst{27-25} = rcond; - set Inst{21-20} = disp{15-14}; - set Inst{19} = 1; // predict; - set Inst{18-14} = rs1; - set Inst{13-0 } = disp{13-0}; + let Name = name; + let Inst{29} = annul; + let Inst{28} = 0; + let Inst{27-25} = rcond; + let Inst{21-20} = disp{15-14}; + let Inst{19} = 1; // predict; + let Inst{18-14} = rs1; + let Inst{13-0 } = disp{13-0}; } diff --git a/lib/Target/SparcV9/SparcV9_F3.td b/lib/Target/SparcV9/SparcV9_F3.td index c83c61d614a..37efe717ecc 100644 --- a/lib/Target/SparcV9/SparcV9_F3.td +++ b/lib/Target/SparcV9/SparcV9_F3.td @@ -10,79 +10,79 @@ // field. class F3 : InstV9 { bits<6> op3; - set op{1} = 1; // Op = 2 or 3 - set Inst{24-19} = op3; + let op{1} = 1; // Op = 2 or 3 + let Inst{24-19} = op3; } // F3_rs1 - Common class of instructions that have an rs1 field class F3_rs1 : F3 { bits<5> rs1; - set Inst{18-14} = rs1; + let Inst{18-14} = rs1; } // F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields class F3_rs1rs2 : F3_rs1 { bits<5> rs2; - set Inst{4-0} = rs2; + let Inst{4-0} = rs2; } // F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields class F3_rs1rs2rd : F3_rs1rs2 { bits<5> rd; - set Inst{29-25} = rd; + let Inst{29-25} = rd; } // F3_rs1simm13 - Common class of instructions that only have rs1 and simm13 class F3_rs1simm13 : F3_rs1 { bits<13> simm13; - set Inst{12-0} = simm13; + let Inst{12-0} = simm13; } class F3_rs1simm13rd : F3_rs1simm13 { bits<5> rd; - set Inst{29-25} = rd; + let Inst{29-25} = rd; } // F3_rs1rd - Common class of instructions that have an rs1 and rd fields class F3_rs1rd : F3_rs1 { bits<5> rd; - set Inst{29-25} = rd; + let Inst{29-25} = rd; } // F3_rs2 - Common class of instructions that don't use an rs1 class F3_rs2 : F3 { bits<5> rs2; - set Inst{4-0} = rs2; + let Inst{4-0} = rs2; } // F3_rs2rd - Common class of instructions that use rs2 and rd, but not rs1 class F3_rs2rd : F3_rs2 { bits<5> rd; - set Inst{29-25} = rd; + let Inst{29-25} = rd; } // F3_rd - Common class of instructions that have an rd field class F3_rd : F3 { bits<5> rd; - set Inst{29-25} = rd; + let Inst{29-25} = rd; } // F3_rdrs1 - Common class of instructions that have rd and rs1 fields class F3_rdrs1 : F3_rd { bits<5> rs1; - set Inst{18-14} = rs1; + let Inst{18-14} = rs1; } // F3_rdrs1simm13 - Common class of instructions that have rd, rs1, and simm13 class F3_rdrs1simm13 : F3_rdrs1 { bits<13> simm13; - set Inst{12-0} = simm13; + let Inst{12-0} = simm13; } // F3_rdrs1rs2 - Common class of instructions that have rd, rs1, and rs2 fields class F3_rdrs1rs2 : F3_rdrs1 { bits<5> rs2; - set Inst{4-0} = rs2; + let Inst{4-0} = rs2; } @@ -90,63 +90,63 @@ class F3_rdrs1rs2 : F3_rdrs1 { // class F3_1 opVal, bits<6> op3val, string name> : F3_rs1rs2rd { - set op = opVal; - set op3 = op3val; - set Name = name; - set Inst{13} = 0; // i field = 0 - set Inst{12-5} = 0; // don't care + let op = opVal; + let op3 = op3val; + let Name = name; + let Inst{13} = 0; // i field = 0 + let Inst{12-5} = 0; // don't care } // The store instructions seem to like to see rd first, then rs1 and rs2 class F3_1rd opVal, bits<6> op3val, string name> : F3_rdrs1rs2 { - set op = opVal; - set op3 = op3val; - set Name = name; - set Inst{13} = 0; // i field = 0 - set Inst{12-5} = 0; // don't care + let op = opVal; + let op3 = op3val; + let Name = name; + let Inst{13} = 0; // i field = 0 + let Inst{12-5} = 0; // don't care } class F3_2 opVal, bits<6> op3val, string name> : F3_rs1simm13rd { - set op = opVal; - set op3 = op3val; - set Name = name; - set Inst{13} = 1; // i field = 1 + let op = opVal; + let op3 = op3val; + let Name = name; + let Inst{13} = 1; // i field = 1 } // The store instructions seem to like to see rd first, then rs1 and imm class F3_2rd opVal, bits<6> op3val, string name> : F3_rdrs1simm13 { - set op = opVal; - set op3 = op3val; - set Name = name; - set Inst{13} = 1; // i field = 1 + let op = opVal; + let op3 = op3val; + let Name = name; + let Inst{13} = 1; // i field = 1 } class F3_3 opVal, bits<6> op3val, string name> : F3_rs1rs2 { - set op = opVal; - set op3 = op3val; - set Name = name; - set Inst{29-25} = 0; // don't care - set Inst{13} = 0; // i field = 0 - set Inst{12-5} = 0; // don't care + let op = opVal; + let op3 = op3val; + let Name = name; + let Inst{29-25} = 0; // don't care + let Inst{13} = 0; // i field = 0 + let Inst{12-5} = 0; // don't care } class F3_4 opVal, bits<6> op3Val, string name> : F3_rs1simm13 { - set op = opVal; - set op3 = op3Val; - set Name = name; - set Inst{29-25} = 0; // don't care - set Inst{13} = 1; // i field = 1 - set Inst{12-0} = simm13; + let op = opVal; + let op3 = op3Val; + let Name = name; + let Inst{29-25} = 0; // don't care + let Inst{13} = 1; // i field = 1 + let Inst{12-0} = simm13; } class F3_5 opVal, bits<6> op3Val, bits<3> rcondVal, string name> : F3_rs1rs2rd { - set op = opVal; - set op3 = op3Val; - set Name = name; - set Inst{13} = 0; // i field = 0 - set Inst{12-10} = rcondVal; // rcond field - set Inst{9-5} = 0; // don't care + let op = opVal; + let op3 = op3Val; + let Name = name; + let Inst{13} = 0; // i field = 0 + let Inst{12-10} = rcondVal; // rcond field + let Inst{9-5} = 0; // don't care } class F3_6 opVal, bits<6> op3Val, bits<3> rcondVal, @@ -154,62 +154,62 @@ class F3_6 opVal, bits<6> op3Val, bits<3> rcondVal, bits<10> simm10; bits<5> rd; - set op = opVal; - set op3 = op3Val; - set Name = name; - set Inst{29-25} = rd; - set Inst{13} = 1; // i field = 1 - set Inst{12-10} = rcondVal; // rcond field - set Inst{9-0} = simm10; + let op = opVal; + let op3 = op3Val; + let Name = name; + let Inst{29-25} = rd; + let Inst{13} = 1; // i field = 1 + let Inst{12-10} = rcondVal; // rcond field + let Inst{9-0} = simm10; } //FIXME: classes 7-10 not defined!! class F3_11 opVal, bits<6> op3Val, string name> : F3_rs1rs2rd { bit x; - set op = opVal; - set op3 = op3Val; - set Name = name; - set Inst{13} = 0; // i field = 0 - set Inst{12} = x; - set Inst{11-5} = 0; // don't care + let op = opVal; + let op3 = op3Val; + let Name = name; + let Inst{13} = 0; // i field = 0 + let Inst{12} = x; + let Inst{11-5} = 0; // don't care } class F3_12 opVal, bits<6> op3Val, string name> : F3_rs1 { bits<5> shcnt; bits<5> rd; - set op = opVal; - set op3 = op3Val; - set Name = name; - set Inst{29-25} = rd; - set Inst{13} = 1; // i field = 1 - set Inst{12} = 0; // x field = 0 - set Inst{11-5} = 0; // don't care - set Inst{4-0} = shcnt; + let op = opVal; + let op3 = op3Val; + let Name = name; + let Inst{29-25} = rd; + let Inst{13} = 1; // i field = 1 + let Inst{12} = 0; // x field = 0 + let Inst{11-5} = 0; // don't care + let Inst{4-0} = shcnt; } class F3_13 opVal, bits<6> op3Val, string name> : F3_rs1 { bits<6> shcnt; bits<5> rd; - set op = opVal; - set op3 = op3Val; - set Name = name; - set Inst{29-25} = rd; - set Inst{13} = 1; // i field = 1 - set Inst{12} = 1; // x field = 1 - set Inst{11-6} = 0; // don't care - set Inst{5-0} = shcnt; + let op = opVal; + let op3 = op3Val; + let Name = name; + let Inst{29-25} = rd; + let Inst{13} = 1; // i field = 1 + let Inst{12} = 1; // x field = 1 + let Inst{11-6} = 0; // don't care + let Inst{5-0} = shcnt; } class F3_14 opVal, bits<6> op3Val, bits<9> opfVal, string name> : F3_rs2rd { - set op = opVal; - set op3 = op3Val; - set Name = name; - set Inst{18-14} = 0; // don't care - set Inst{13-5} = opfVal; + let op = opVal; + let op3 = op3Val; + let Name = name; + let Inst{18-14} = 0; // don't care + let Inst{13-5} = opfVal; } class F3_15 opVal, bits<6> op3Val, @@ -218,44 +218,44 @@ class F3_15 opVal, bits<6> op3Val, bits<5> rs1; bits<5> rs2; - set op = opVal; - set op3 = op3Val; - set Name = name; - set Inst{29-27} = 0; // defined to be zero - set Inst{26-25} = cc; - set Inst{18-14} = rs1; - set Inst{13-5} = opfVal; - set Inst{4-0} = rs2; + let op = opVal; + let op3 = op3Val; + let Name = name; + let Inst{29-27} = 0; // defined to be zero + let Inst{26-25} = cc; + let Inst{18-14} = rs1; + let Inst{13-5} = opfVal; + let Inst{4-0} = rs2; } class F3_16 opVal, bits<6> op3Val, bits<9> opfval, string name> : F3_rs1rs2rd { - set op = opVal; - set op3 = op3Val; - set Name = name; - set Inst{13-5} = opfval; + let op = opVal; + let op3 = op3Val; + let Name = name; + let Inst{13-5} = opfval; } class F3_17 opVal, bits<6> op3Val, string name> : F3_rs1rd { - set op = opVal; - set op3 = op3Val; - set Name = name; - set Inst{13-0} = 0; // don't care + let op = opVal; + let op3 = op3Val; + let Name = name; + let Inst{13-0} = 0; // don't care } class F3_18 fcn, string name> : F3 { - set op = 2; - set op3 = 0b111110; - set Name = name; - set Inst{29-25} = fcn; - set Inst{18-0 } = 0; // don't care; + let op = 2; + let op3 = 0b111110; + let Name = name; + let Inst{29-25} = fcn; + let Inst{18-0 } = 0; // don't care; } class F3_19 opVal, bits<6> op3Val, string name> : F3_rd { - set op = opVal; - set op3 = op3Val; - set Name = name; - set Inst{18-0} = 0; // don't care + let op = opVal; + let op3 = op3Val; + let Name = name; + let Inst{18-0} = 0; // don't care } // FIXME: class F3_20 diff --git a/lib/Target/SparcV9/SparcV9_F4.td b/lib/Target/SparcV9/SparcV9_F4.td index 43711f32877..1624a195d95 100644 --- a/lib/Target/SparcV9/SparcV9_F4.td +++ b/lib/Target/SparcV9/SparcV9_F4.td @@ -8,25 +8,25 @@ // field. class F4 : InstV9 { bits<6> op3; - set Inst{24-19} = op3; + let Inst{24-19} = op3; } // F4_rs1 - Common class of instructions that use an rs1 field class F4_rs1 : F4 { bits<5> rs1; - set Inst{18-14} = rs1; + let Inst{18-14} = rs1; } // F4_rs1rs2 - Common class of instructions that have rs1 and rs2 fields class F4_rs1rs2 : F4_rs1 { bits<5> rs2; - set Inst{4-0} = rs2; + let Inst{4-0} = rs2; } // F4_rs1rs2rd - Common class of instructions that have 3 register operands class F4_rs1rs2rd : F4_rs1rs2 { bits<5> rd; - set Inst{29-25} = rd; + let Inst{29-25} = rd; } // F4_rs1rs2rd - Common class of instructions that have 2 reg and 1 imm operand @@ -34,22 +34,22 @@ class F4_rs1simm11rd : F4_rs1 { bits<11> simm11; bits<5> rd; - set Inst{10-0} = simm11; - set Inst{29-25} = rd; + let Inst{10-0} = simm11; + let Inst{29-25} = rd; } // F4_cc - Common class of instructions that have a cond field class F4_cond : F4 { bits<4> cond; - set Inst{17-14} = cond; + let Inst{17-14} = cond; } // F4_cc - Common class of instructions that have cc register as first operand class F4_condcc : F4_cond { bits<3> cc; - set Inst{18} = cc{2}; - set Inst{12} = cc{1}; - set Inst{11} = cc{0}; + let Inst{18} = cc{2}; + let Inst{12} = cc{1}; + let Inst{11} = cc{0}; } // Actual F4 instruction classes @@ -57,22 +57,22 @@ class F4_condcc : F4_cond { class F4_1 opVal, bits<6> op3Val, string name> : F4_rs1rs2rd { bits<2> cc; - set op = opVal; - set op3 = op3Val; - set Name = name; - set Inst{13} = 0; // i bit - set Inst{12-11} = cc; - set Inst{10-5} = 0; // don't care + let op = opVal; + let op3 = op3Val; + let Name = name; + let Inst{13} = 0; // i bit + let Inst{12-11} = cc; + let Inst{10-5} = 0; // don't care } class F4_2 opVal, bits<6> op3Val, string name> : F4_rs1simm11rd { bits<2> cc; - set op = opVal; - set op3 = op3Val; - set Name = name; - set Inst{13} = 1; // i bit - set Inst{12-11} = cc; + let op = opVal; + let op3 = op3Val; + let Name = name; + let Inst{13} = 1; // i bit + let Inst{12-11} = cc; } class F4_3 opVal, bits<6> op3Val, bits<4> condVal, @@ -80,14 +80,14 @@ class F4_3 opVal, bits<6> op3Val, bits<4> condVal, bits<5> rs2; bits<5> rd; - set op = opVal; - set op3 = op3Val; - set cond = condVal; - set Name = name; - set Inst{29-25} = rd; - set Inst{13} = 0; // i bit - set Inst{10-5} = 0; // don't care - set Inst{4-0} = rs2; + let op = opVal; + let op3 = op3Val; + let cond = condVal; + let Name = name; + let Inst{29-25} = rd; + let Inst{13} = 0; // i bit + let Inst{10-5} = 0; // don't care + let Inst{4-0} = rs2; } class F4_4 opVal, bits<6> op3Val, bits<4> condVal, @@ -95,25 +95,25 @@ class F4_4 opVal, bits<6> op3Val, bits<4> condVal, bits<11> simm11; bits<5> rd; - set op = opVal; - set op3 = op3Val; - set cond = condVal; - set Name = name; - set Inst{29-25} = rd; - set Inst{13} = 1; // i bit - set Inst{10-0} = simm11; + let op = opVal; + let op3 = op3Val; + let cond = condVal; + let Name = name; + let Inst{29-25} = rd; + let Inst{13} = 1; // i bit + let Inst{10-0} = simm11; } // FIXME: class F4_5 class F4_6 opVal, bits<6> op3Val, bits<3> rcondVal, bits<5> opf_lowVal, string name> : F4_rs1rs2rd { - set op = opVal; - set op3 = op3Val; - set Name = name; - set Inst{13} = 0; - set Inst{12-10} = rcondVal; - set Inst{9-5} = opf_lowVal; + let op = opVal; + let op3 = op3Val; + let Name = name; + let Inst{13} = 0; + let Inst{12-10} = rcondVal; + let Inst{9-5} = opf_lowVal; } class F4_7 opVal, bits<6> op3Val, bits<4> condVal, @@ -122,15 +122,15 @@ class F4_7 opVal, bits<6> op3Val, bits<4> condVal, bits<5> rs2; bits<5> rd; - set op = opVal; - set op3 = op3Val; - set cond = condVal; - set Name = name; - set Inst{29-25} = rd; - set Inst{18} = 0; - set Inst{13-11} = cc; - set Inst{10-5} = opf_lowVal; - set Inst{4-0} = rs2; + let op = opVal; + let op3 = op3Val; + let cond = condVal; + let Name = name; + let Inst{29-25} = rd; + let Inst{18} = 0; + let Inst{13-11} = cc; + let Inst{10-5} = opf_lowVal; + let Inst{4-0} = rs2; } // FIXME: F4 classes 8-9 diff --git a/lib/Target/SparcV9/SparcV9_Reg.td b/lib/Target/SparcV9/SparcV9_Reg.td index 7b3817723f9..c63d825f165 100644 --- a/lib/Target/SparcV9/SparcV9_Reg.td +++ b/lib/Target/SparcV9/SparcV9_Reg.td @@ -11,7 +11,7 @@ class Ri num> : Register { field bits<5> Num = num; // Numbers are identified with a 5 bit ID } -set Namespace = "SparcV9" in { +let Namespace = "SparcV9" in { def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>; def G4 : Ri< 4>; def G5 : Ri< 5>; def G6 : Ri< 6>; def G7 : Ri< 7>; def O0 : Ri< 8>; def O1 : Ri< 9>; def O2 : Ri<10>; def O3 : Ri<11>;