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Dynamic stack realignment use of sp register as source/dest register
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode. Emit the following code instead: mov r4, sp bic r4, r4, #15 mov sp, r4 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90724 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -578,6 +578,13 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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MFI->calculateMaxStackAlignment();
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MFI->calculateMaxStackAlignment();
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}
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}
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// Spill R4 if Thumb2 function requires stack realignment - it will be used as
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// scratch register.
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// FIXME: It will be better just to find spare register here.
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if (needsStackRealignment(MF) &&
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AFI->isThumb2Function())
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MF.getRegInfo().setPhysRegUsed(ARM::R4);
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// Don't spill FP if the frame can be eliminated. This is determined
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// Don't spill FP if the frame can be eliminated. This is determined
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// by scanning the callee-save registers to see if any is used.
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// by scanning the callee-save registers to see if any is used.
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const unsigned *CSRegs = getCalleeSavedRegs();
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const unsigned *CSRegs = getCalleeSavedRegs();
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@ -1351,14 +1358,30 @@ emitPrologue(MachineFunction &MF) const {
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// If we need dynamic stack realignment, do it here.
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// If we need dynamic stack realignment, do it here.
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if (needsStackRealignment(MF)) {
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if (needsStackRealignment(MF)) {
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unsigned Opc;
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unsigned MaxAlign = MFI->getMaxAlignment();
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unsigned MaxAlign = MFI->getMaxAlignment();
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assert (!AFI->isThumb1OnlyFunction());
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assert (!AFI->isThumb1OnlyFunction());
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Opc = AFI->isThumbFunction() ? ARM::t2BICri : ARM::BICri;
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if (!AFI->isThumbFunction()) {
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// Emit bic sp, sp, MaxAlign
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AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), ARM::SP)
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AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
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TII.get(ARM::BICri), ARM::SP)
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.addReg(ARM::SP, RegState::Kill)
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.addReg(ARM::SP, RegState::Kill)
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.addImm(MaxAlign-1)));
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.addImm(MaxAlign-1)));
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} else {
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// We cannot use sp as source/dest register here, thus we're emitting the
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// following sequence:
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// mov r4, sp
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// bic r4, r4, MaxAlign
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// mov sp, r4
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// FIXME: It will be better just to find spare register here.
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R4)
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.addReg(ARM::SP, RegState::Kill);
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AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
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TII.get(ARM::t2BICri), ARM::R4)
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.addReg(ARM::R4, RegState::Kill)
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.addImm(MaxAlign-1)));
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
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.addReg(ARM::R4, RegState::Kill);
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}
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}
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}
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}
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}
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@ -18,7 +18,7 @@ define void @test2() {
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define i32 @test3() {
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define i32 @test3() {
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; CHECK: test3:
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; CHECK: test3:
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; CHECK: sub.w sp, sp, #805306368
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; CHECK: sub.w sp, sp, #805306368
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; CHECK: sub sp, #24
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; CHECK: sub sp, #20
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%retval = alloca i32, align 4
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%retval = alloca i32, align 4
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%tmp = alloca i32, align 4
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%tmp = alloca i32, align 4
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%a = alloca [805306369 x i8], align 16
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%a = alloca [805306369 x i8], align 16
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@ -11,7 +11,7 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly
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define arm_apcscc void @aaa(%quuz* %this, i8* %block) {
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define arm_apcscc void @aaa(%quuz* %this, i8* %block) {
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; CHECK: aaa:
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; CHECK: aaa:
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; CHECK: bic sp, sp, #15
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; CHECK: bic r4, r4, #15
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; CHECK: vst1.64 {{.*}}sp, :128
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; CHECK: vst1.64 {{.*}}sp, :128
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; CHECK: vld1.64 {{.*}}sp, :128
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; CHECK: vld1.64 {{.*}}sp, :128
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entry:
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entry:
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