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Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176411 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2682,7 +2682,7 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
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CCInfo.AnalyzeFormalArguments(Ins,
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CCInfo.AnalyzeFormalArguments(Ins,
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CCAssignFnForNode(CallConv, /* Return*/ false,
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CCAssignFnForNode(CallConv, /* Return*/ false,
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isVarArg));
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isVarArg));
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SmallVector<SDValue, 16> ArgValues;
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SmallVector<SDValue, 16> ArgValues;
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int lastInsIndex = -1;
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int lastInsIndex = -1;
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SDValue ArgValue;
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SDValue ArgValue;
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@ -2797,7 +2797,7 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
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} else {
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} else {
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int FI = MFI->CreateFixedObject(Flags.getByValSize(),
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int FI = MFI->CreateFixedObject(Flags.getByValSize(),
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VA.getLocMemOffset(), false);
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VA.getLocMemOffset(), false);
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InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
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InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
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}
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}
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} else {
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} else {
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int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
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int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
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@ -3594,7 +3594,7 @@ static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
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/// input = [v0 v1 v2 v3 ] (vi 16-bit element)
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/// input = [v0 v1 v2 v3 ] (vi 16-bit element)
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/// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
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/// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
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/// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
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/// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
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/// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
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/// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
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/// [b0 b1 b2 b3 b4 b5 b6 b7]
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/// [b0 b1 b2 b3 b4 b5 b6 b7]
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/// +[b1 b0 b3 b2 b5 b4 b7 b6]
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/// +[b1 b0 b3 b2 b5 b4 b7 b6]
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/// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
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/// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
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@ -3615,7 +3615,7 @@ static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
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/// bit-count for each 16-bit element from the operand. We need slightly
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/// bit-count for each 16-bit element from the operand. We need slightly
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/// different sequencing for v4i16 and v8i16 to stay within NEON's available
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/// different sequencing for v4i16 and v8i16 to stay within NEON's available
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/// 64/128-bit registers.
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/// 64/128-bit registers.
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///
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///
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/// Trace for v4i16:
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/// Trace for v4i16:
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/// input = [v0 v1 v2 v3 ] (vi 16-bit element)
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/// input = [v0 v1 v2 v3 ] (vi 16-bit element)
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/// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
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/// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
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@ -3646,7 +3646,7 @@ static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
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/// input = [v0 v1 ] (vi: 32-bit elements)
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/// input = [v0 v1 ] (vi: 32-bit elements)
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/// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
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/// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
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/// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
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/// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
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/// vrev: N0 = [k1 k0 k3 k2 ]
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/// vrev: N0 = [k1 k0 k3 k2 ]
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/// [k0 k1 k2 k3 ]
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/// [k0 k1 k2 k3 ]
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/// N1 =+[k1 k0 k3 k2 ]
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/// N1 =+[k1 k0 k3 k2 ]
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/// [k0 k2 k1 k3 ]
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/// [k0 k2 k1 k3 ]
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@ -4424,7 +4424,7 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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ValueCounts.insert(std::make_pair(V, 0));
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ValueCounts.insert(std::make_pair(V, 0));
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unsigned &Count = ValueCounts[V];
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unsigned &Count = ValueCounts[V];
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// Is this value dominant? (takes up more than half of the lanes)
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// Is this value dominant? (takes up more than half of the lanes)
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if (++Count > (NumElts / 2)) {
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if (++Count > (NumElts / 2)) {
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hasDominantValue = true;
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hasDominantValue = true;
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@ -4505,7 +4505,7 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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if (usesOnlyOneValue) {
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if (usesOnlyOneValue) {
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SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
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SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
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if (isConstant && Val.getNode())
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if (isConstant && Val.getNode())
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return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
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return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
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}
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}
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}
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}
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