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Add a 'pattern' arg to the ARM PseudoNeonI class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115831 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1550,11 +1550,13 @@ class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
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list<Predicate> Predicates = [HasNEON];
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}
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class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr>
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class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
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list<dag> pattern>
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: InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
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itin> {
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let OutOperandList = oops;
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let InOperandList = !con(iops, (ins pred:$p));
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let Pattern = pattern;
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list<Predicate> Predicates = [HasNEON];
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}
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@ -3816,11 +3816,11 @@ def VTBL4
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} // hasExtraSrcRegAllocReq = 1
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def VTBL2Pseudo
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: PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "">;
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: PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
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def VTBL3Pseudo
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: PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "">;
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: PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
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def VTBL4Pseudo
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: PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "">;
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: PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
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// VTBX : Vector Table Extension
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def VTBX1
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@ -3849,13 +3849,13 @@ def VTBX4
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def VTBX2Pseudo
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: PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
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IIC_VTBX2, "$orig = $dst">;
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IIC_VTBX2, "$orig = $dst", []>;
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def VTBX3Pseudo
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: PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
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IIC_VTBX3, "$orig = $dst">;
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IIC_VTBX3, "$orig = $dst", []>;
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def VTBX4Pseudo
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: PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
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IIC_VTBX4, "$orig = $dst">;
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IIC_VTBX4, "$orig = $dst", []>;
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//===----------------------------------------------------------------------===//
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// NEON instructions for single-precision FP math
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