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Fix decoding of pre-indexed stores.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137487 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2011-08-12 18:12:39 +00:00
parent 11abf5bca9
commit 7cdbf086e4
2 changed files with 43 additions and 0 deletions
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41
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -139,6 +139,11 @@ static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
uint64_t Address, const void *Decoder);
@ -2524,4 +2529,40 @@ static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
return true;
}
static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
unsigned imm = fieldFromInstruction32(Insn, 0, 12);
imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE
if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
if (!DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)) return false;
if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
return true;
}
static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
unsigned imm = fieldFromInstruction32(Insn, 0, 12);
imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE
if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
if (!DecodeSORegMemOperand(Inst, imm, Address, Decoder)) return false;
if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
return true;
}