mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
Matches MachineInstr changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31712 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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d7de496b23
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@ -18,6 +18,8 @@
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#define LLVM_CODEGEN_MACHINEINSTRBUILDER_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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@ -33,8 +35,9 @@ public:
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/// addReg - Add a new virtual register operand...
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///
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const MachineInstrBuilder &addReg(int RegNo, bool isDef = false,
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bool isImp = false) const {
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const
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MachineInstrBuilder &addReg(int RegNo, bool isDef = false, bool isImp = false,
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bool isKill = false, bool isDead = false) const {
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MI->addRegOperand(RegNo, isDef, isImp);
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return *this;
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}
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@ -77,28 +80,24 @@ public:
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MI->addExternalSymbolOperand(FnName);
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return *this;
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}
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const MachineInstrBuilder &addImplicitDefsUses() const {
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MI->addImplicitDefUseOperands();
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return *this;
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}
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};
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/// BuildMI - Builder interface. Specify how to create the initial instruction
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/// itself. NumOperands is the number of operands to the machine instruction to
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/// allow for memory efficient representation of machine instructions.
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///
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inline MachineInstrBuilder BuildMI(int Opcode, unsigned NumOperands) {
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return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands));
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inline MachineInstrBuilder BuildMI(const TargetInstrInfo &TII, int Opcode,
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unsigned NumOperands) {
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return MachineInstrBuilder(new MachineInstr(TII, Opcode, NumOperands));
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}
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/// BuildMI - This version of the builder sets up the first operand as a
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/// destination virtual register. NumOperands is the number of additional add*
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/// calls that are expected, not including the destination register.
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///
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inline MachineInstrBuilder
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BuildMI(int Opcode, unsigned NumOperands, unsigned DestReg) {
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return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands+1))
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inline MachineInstrBuilder BuildMI(const TargetInstrInfo &TII, int Opcode,
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unsigned NumOperands, unsigned DestReg) {
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return MachineInstrBuilder(new MachineInstr(TII, Opcode, NumOperands+1))
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.addReg(DestReg, true);
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}
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@ -112,7 +111,8 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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int Opcode, unsigned NumOperands,
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unsigned DestReg) {
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MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1);
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MachineInstr *MI = new MachineInstr(*BB.getParent()->getTarget().
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getInstrInfo(), Opcode, NumOperands+1);
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BB.insert(I, MI);
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return MachineInstrBuilder(MI).addReg(DestReg, true);
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}
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@ -124,7 +124,8 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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int Opcode, unsigned NumOperands) {
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MachineInstr *MI = new MachineInstr(Opcode, NumOperands);
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MachineInstr *MI = new MachineInstr(*BB.getParent()->getTarget().
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getInstrInfo(), Opcode, NumOperands);
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BB.insert(I, MI);
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return MachineInstrBuilder(MI);
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}
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@ -395,7 +395,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
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#endif
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// Create the new machine instruction.
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MachineInstr *MI = new MachineInstr(Opc, NumMIOperands);
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MachineInstr *MI = new MachineInstr(*TII, Opc, NumMIOperands);
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// Add result register values for things that are defined by this
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// instruction.
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@ -441,9 +441,6 @@ void ScheduleDAG::EmitNode(SDNode *Node,
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}
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}
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// Emit implicit def / use operands.
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MI->addImplicitDefUseOperands();
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// Now that we have emitted all operands, emit this instruction itself.
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if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
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BB->insert(BB->end(), MI);
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@ -19,7 +19,8 @@
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using namespace llvm;
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AlphaInstrInfo::AlphaInstrInfo()
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: TargetInstrInfo(AlphaInsts, sizeof(AlphaInsts)/sizeof(AlphaInsts[0])) { }
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: TargetInstrInfo(AlphaInsts, sizeof(AlphaInsts)/sizeof(AlphaInsts[0])),
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RI(*this) { }
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bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
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@ -51,8 +51,9 @@ static long getLower16(long l)
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return l - h * IMM_MULT;
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}
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AlphaRegisterInfo::AlphaRegisterInfo()
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: AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP)
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AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
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: AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
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TII(tii)
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{
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}
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@ -114,13 +115,13 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
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unsigned InReg = MI->getOperand(1).getReg();
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Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
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((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
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return BuildMI(Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
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return BuildMI(TII, Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
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.addReg(Alpha::F31);
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} else { // load -> move
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unsigned OutReg = MI->getOperand(0).getReg();
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Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
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((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
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return BuildMI(Opc, 2, OutReg).addFrameIndex(FrameIndex)
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return BuildMI(TII, Opc, 2, OutReg).addFrameIndex(FrameIndex)
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.addReg(Alpha::F31);
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}
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}
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@ -205,11 +206,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineInstr *New;
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if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
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New=BuildMI(Alpha::LDA, 2, Alpha::R30)
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New=BuildMI(TII, Alpha::LDA, 2, Alpha::R30)
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.addImm(-Amount).addReg(Alpha::R30);
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} else {
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assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
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New=BuildMI(Alpha::LDA, 2, Alpha::R30)
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New=BuildMI(TII, Alpha::LDA, 2, Alpha::R30)
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.addImm(Amount).addReg(Alpha::R30);
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}
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@ -266,7 +267,7 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
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MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
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//insert the new
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MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
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MachineInstr* nMI=BuildMI(TII, Alpha::LDAH, 2, Alpha::R28)
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.addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
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MBB.insert(II, nMI);
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} else {
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@ -22,7 +22,9 @@ namespace llvm {
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class Type;
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struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
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AlphaRegisterInfo();
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const TargetInstrInfo &TII;
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AlphaRegisterInfo(const TargetInstrInfo &tii);
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/// Code Generation virtual methods...
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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@ -121,7 +121,7 @@ static bool hasFP(const MachineFunction &MF) {
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void IA64RegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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if (hasFP(MF)) {
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// If we have a frame pointer, turn the adjcallstackup instruction into a
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// 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP,
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@ -137,11 +137,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineInstr *New;
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if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
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New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
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New=BuildMI(TII, IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
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.addImm(-Amount);
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} else {
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assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
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New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
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New=BuildMI(TII, IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
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.addImm(Amount);
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}
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@ -158,6 +158,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II)const{
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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bool FP = hasFP(MF);
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@ -186,16 +187,16 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II)const{
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// Fix up the old:
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MI.getOperand(i).ChangeToRegister(IA64::r22, false);
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//insert the new
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MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22)
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MachineInstr* nMI=BuildMI(TII, IA64::ADDIMM22, 2, IA64::r22)
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.addReg(BaseRegister).addImm(Offset);
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MBB.insert(II, nMI);
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} else { // it's big
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//fix up the old:
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MI.getOperand(i).ChangeToRegister(IA64::r22, false);
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MachineInstr* nMI;
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nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(Offset);
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nMI=BuildMI(TII, IA64::MOVLIMM64, 1, IA64::r22).addImm(Offset);
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MBB.insert(II, nMI);
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nMI=BuildMI(IA64::ADD, 2, IA64::r22).addReg(BaseRegister)
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nMI=BuildMI(TII, IA64::ADD, 2, IA64::r22).addReg(BaseRegister)
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.addReg(IA64::r22);
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MBB.insert(II, nMI);
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}
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@ -206,6 +207,7 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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MachineInstr *MI;
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bool FP = hasFP(MF);
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@ -250,7 +252,7 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
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}
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}
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MI=BuildMI(IA64::ALLOC,5).addReg(dstRegOfPseudoAlloc).addImm(0).\
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MI=BuildMI(TII, IA64::ALLOC,5).addReg(dstRegOfPseudoAlloc).addImm(0). \
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addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0);
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MBB.insert(MBBI, MI);
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@ -282,22 +284,23 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
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// adjust stack pointer: r12 -= numbytes
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if (NumBytes <= 8191) {
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MI=BuildMI(IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).addImm(-NumBytes);
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MI=BuildMI(TII, IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).
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addImm(-NumBytes);
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MBB.insert(MBBI, MI);
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} else { // we use r22 as a scratch register here
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MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(-NumBytes);
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MI=BuildMI(TII, IA64::MOVLIMM64, 1, IA64::r22).addImm(-NumBytes);
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// FIXME: MOVLSI32 expects a _u_32imm
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MBB.insert(MBBI, MI); // first load the decrement into r22
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MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
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MI=BuildMI(TII,IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
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MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr)
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}
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// now if we need to, save the old FP and set the new
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if (FP) {
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MI = BuildMI(IA64::ST8, 2).addReg(IA64::r12).addReg(IA64::r5);
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MI = BuildMI(TII, IA64::ST8, 2).addReg(IA64::r12).addReg(IA64::r5);
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MBB.insert(MBBI, MI);
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// this must be the last instr in the prolog ? (XXX: why??)
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MI = BuildMI(IA64::MOV, 1, IA64::r5).addReg(IA64::r12);
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MI = BuildMI(TII, IA64::MOV, 1, IA64::r5).addReg(IA64::r12);
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MBB.insert(MBBI, MI);
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}
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@ -306,6 +309,7 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
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void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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MachineInstr *MI;
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assert(MBBI->getOpcode() == IA64::RET &&
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@ -320,22 +324,24 @@ void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
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if (FP)
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{
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//copy the FP into the SP (discards allocas)
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MI=BuildMI(IA64::MOV, 1, IA64::r12).addReg(IA64::r5);
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MI=BuildMI(TII, IA64::MOV, 1, IA64::r12).addReg(IA64::r5);
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MBB.insert(MBBI, MI);
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//restore the FP
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MI=BuildMI(IA64::LD8, 1, IA64::r5).addReg(IA64::r5);
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MI=BuildMI(TII, IA64::LD8, 1, IA64::r5).addReg(IA64::r5);
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MBB.insert(MBBI, MI);
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}
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if (NumBytes != 0)
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{
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if (NumBytes <= 8191) {
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MI=BuildMI(IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).addImm(NumBytes);
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MI=BuildMI(TII, IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).
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addImm(NumBytes);
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MBB.insert(MBBI, MI);
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} else {
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MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(NumBytes);
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MI=BuildMI(TII, IA64::MOVLIMM64, 1, IA64::r22).addImm(NumBytes);
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MBB.insert(MBBI, MI);
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MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
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MI=BuildMI(TII, IA64::ADD, 2, IA64::r12).addReg(IA64::r12).
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addReg(IA64::r22);
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MBB.insert(MBBI, MI);
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}
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}
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@ -20,7 +20,7 @@ using namespace llvm;
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PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
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: TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])), TM(tm),
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RI(*TM.getSubtargetImpl()) {}
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RI(*TM.getSubtargetImpl(), *this) {}
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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@ -80,9 +80,10 @@ unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
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}
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}
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PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST)
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PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
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const TargetInstrInfo &tii)
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: PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
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Subtarget(ST) {
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Subtarget(ST), TII(tii) {
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ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
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ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
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ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
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@ -322,39 +323,39 @@ MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
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MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
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if (OpNum == 0) { // move -> store
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unsigned InReg = MI->getOperand(1).getReg();
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return addFrameReference(BuildMI(PPC::STW,
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return addFrameReference(BuildMI(TII, PPC::STW,
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3).addReg(InReg), FrameIndex);
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} else { // move -> load
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unsigned OutReg = MI->getOperand(0).getReg();
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return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
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return addFrameReference(BuildMI(TII, PPC::LWZ, 2, OutReg), FrameIndex);
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}
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} else if ((Opc == PPC::OR8 &&
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MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
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if (OpNum == 0) { // move -> store
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unsigned InReg = MI->getOperand(1).getReg();
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return addFrameReference(BuildMI(PPC::STD,
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return addFrameReference(BuildMI(TII, PPC::STD,
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3).addReg(InReg), FrameIndex);
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} else { // move -> load
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unsigned OutReg = MI->getOperand(0).getReg();
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return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex);
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return addFrameReference(BuildMI(TII, PPC::LD, 2, OutReg), FrameIndex);
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}
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} else if (Opc == PPC::FMRD) {
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if (OpNum == 0) { // move -> store
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unsigned InReg = MI->getOperand(1).getReg();
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return addFrameReference(BuildMI(PPC::STFD,
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return addFrameReference(BuildMI(TII, PPC::STFD,
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3).addReg(InReg), FrameIndex);
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} else { // move -> load
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unsigned OutReg = MI->getOperand(0).getReg();
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return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
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return addFrameReference(BuildMI(TII, PPC::LFD, 2, OutReg), FrameIndex);
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}
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} else if (Opc == PPC::FMRS) {
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if (OpNum == 0) { // move -> store
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unsigned InReg = MI->getOperand(1).getReg();
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return addFrameReference(BuildMI(PPC::STFS,
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return addFrameReference(BuildMI(TII, PPC::STFS,
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3).addReg(InReg), FrameIndex);
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} else { // move -> load
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unsigned OutReg = MI->getOperand(0).getReg();
|
||||
return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex);
|
||||
return addFrameReference(BuildMI(TII, PPC::LFS, 2, OutReg), FrameIndex);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
@ -25,8 +25,9 @@ class Type;
|
||||
class PPCRegisterInfo : public PPCGenRegisterInfo {
|
||||
std::map<unsigned, unsigned> ImmToIdxMap;
|
||||
const PPCSubtarget &Subtarget;
|
||||
const TargetInstrInfo &TII;
|
||||
public:
|
||||
PPCRegisterInfo(const PPCSubtarget &SubTarget);
|
||||
PPCRegisterInfo(const PPCSubtarget &SubTarget, const TargetInstrInfo &tii);
|
||||
|
||||
/// getRegisterNumbering - Given the enum value for some register, e.g.
|
||||
/// PPC::F14, return the number that it corresponds to (e.g. 14).
|
||||
|
@ -19,7 +19,7 @@ using namespace llvm;
|
||||
|
||||
SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
|
||||
: TargetInstrInfo(SparcInsts, sizeof(SparcInsts)/sizeof(SparcInsts[0])),
|
||||
RI(ST) {
|
||||
RI(ST, *this) {
|
||||
}
|
||||
|
||||
static bool isZeroImm(const MachineOperand &op) {
|
||||
|
@ -23,9 +23,10 @@
|
||||
#include <iostream>
|
||||
using namespace llvm;
|
||||
|
||||
SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
|
||||
SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
|
||||
const TargetInstrInfo &tii)
|
||||
: SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
|
||||
Subtarget(st) {
|
||||
Subtarget(st), TII(tii) {
|
||||
}
|
||||
|
||||
void SparcRegisterInfo::
|
||||
@ -81,10 +82,10 @@ MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
|
||||
if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
|
||||
MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
|
||||
if (OpNum == 0) // COPY -> STORE
|
||||
return BuildMI(SP::STri, 3).addFrameIndex(FI).addImm(0)
|
||||
return BuildMI(TII, SP::STri, 3).addFrameIndex(FI).addImm(0)
|
||||
.addReg(MI->getOperand(2).getReg());
|
||||
else // COPY -> LOAD
|
||||
return BuildMI(SP::LDri, 2, MI->getOperand(0).getReg())
|
||||
return BuildMI(TII, SP::LDri, 2, MI->getOperand(0).getReg())
|
||||
.addFrameIndex(FI).addImm(0);
|
||||
}
|
||||
break;
|
||||
@ -93,10 +94,10 @@ MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
|
||||
// FALLTHROUGH
|
||||
case SP::FMOVD:
|
||||
if (OpNum == 0) // COPY -> STORE
|
||||
return BuildMI(isFloat ? SP::STFri : SP::STDFri, 3)
|
||||
return BuildMI(TII, isFloat ? SP::STFri : SP::STDFri, 3)
|
||||
.addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
|
||||
else // COPY -> LOAD
|
||||
return BuildMI(isFloat ? SP::LDFri : SP::LDDFri, 2,
|
||||
return BuildMI(TII, isFloat ? SP::LDFri : SP::LDDFri, 2,
|
||||
MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
|
||||
break;
|
||||
}
|
||||
|
@ -24,8 +24,9 @@ class Type;
|
||||
|
||||
struct SparcRegisterInfo : public SparcGenRegisterInfo {
|
||||
SparcSubtarget &Subtarget;
|
||||
const TargetInstrInfo &TII;
|
||||
|
||||
SparcRegisterInfo(SparcSubtarget &st);
|
||||
SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii);
|
||||
|
||||
/// Code Generation virtual methods...
|
||||
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
|
@ -40,6 +40,7 @@
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/Compiler.h"
|
||||
#include "llvm/ADT/DepthFirstIterator.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/ADT/Statistic.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include <algorithm>
|
||||
@ -213,20 +214,12 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
|
||||
|
||||
// Get dead variables list now because the MI pointer may be deleted as part
|
||||
// of processing!
|
||||
LiveVariables::killed_iterator IB, IE;
|
||||
tie(IB, IE) = LV->dead_range(MI);
|
||||
|
||||
DEBUG(
|
||||
const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo();
|
||||
LiveVariables::killed_iterator I = LV->killed_begin(MI);
|
||||
LiveVariables::killed_iterator E = LV->killed_end(MI);
|
||||
if (I != E) {
|
||||
std::cerr << "Killed Operands:";
|
||||
for (; I != E; ++I)
|
||||
std::cerr << " %" << MRI->getName(*I);
|
||||
std::cerr << "\n";
|
||||
}
|
||||
);
|
||||
SmallVector<unsigned, 8> DeadRegs;
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
const MachineOperand &MO = MI->getOperand(i);
|
||||
if (MO.isReg() && MO.isDead())
|
||||
DeadRegs.push_back(MO.getReg());
|
||||
}
|
||||
|
||||
switch (Flags & X86II::FPTypeMask) {
|
||||
case X86II::ZeroArgFP: handleZeroArgFP(I); break;
|
||||
@ -241,8 +234,8 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
|
||||
|
||||
// Check to see if any of the values defined by this instruction are dead
|
||||
// after definition. If so, pop them.
|
||||
for (; IB != IE; ++IB) {
|
||||
unsigned Reg = *IB;
|
||||
for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
|
||||
unsigned Reg = DeadRegs[i];
|
||||
if (Reg >= X86::FP0 && Reg <= X86::FP6) {
|
||||
DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
|
||||
freeStackSlotAfter(I, Reg-X86::FP0);
|
||||
@ -762,6 +755,7 @@ void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
|
||||
|
||||
unsigned Op0 = getFPReg(MI->getOperand(0));
|
||||
unsigned Op1 = getFPReg(MI->getOperand(2));
|
||||
bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
|
||||
|
||||
// The first operand *must* be on the top of the stack.
|
||||
moveToTop(Op0, I);
|
||||
@ -773,9 +767,8 @@ void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
|
||||
MI->getOperand(0).setReg(getSTReg(Op1));
|
||||
MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
|
||||
|
||||
|
||||
// If we kill the second operand, make sure to pop it from the stack.
|
||||
if (Op0 != Op1 && LV->KillsRegister(MI, X86::FP0+Op1)) {
|
||||
if (Op0 != Op1 && KillsOp1) {
|
||||
// Get this value off of the register stack.
|
||||
freeStackSlotAfter(I, Op1);
|
||||
}
|
||||
|
@ -525,8 +525,7 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
|
||||
|
||||
// Finally, if we found any FP code, emit the FP_REG_KILL instruction.
|
||||
if (ContainsFPCode) {
|
||||
BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0).
|
||||
addImplicitDefsUses();
|
||||
BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
|
||||
++NumFPKill;
|
||||
}
|
||||
}
|
||||
@ -537,8 +536,7 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
|
||||
void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
|
||||
MachineFrameInfo *MFI) {
|
||||
if (Subtarget->isTargetCygwin())
|
||||
BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("__main").
|
||||
addImplicitDefsUses();
|
||||
BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("__main");
|
||||
|
||||
// Switch the FPU to 64-bit precision mode for better compatibility and speed.
|
||||
int CWFrameIdx = MFI->CreateStackObject(2, 2);
|
||||
@ -949,8 +947,7 @@ SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
|
||||
// type of register here.
|
||||
GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass);
|
||||
BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0);
|
||||
BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg).
|
||||
addImplicitDefsUses();
|
||||
BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg);
|
||||
}
|
||||
return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val;
|
||||
}
|
||||
|
@ -5076,7 +5076,7 @@ X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
|
||||
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
|
||||
unsigned Opc =
|
||||
X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
|
||||
BuildMI(BB, Opc, 1).addMBB(sinkMBB).addImplicitDefsUses();
|
||||
BuildMI(BB, Opc, 1).addMBB(sinkMBB);
|
||||
MachineFunction *F = BB->getParent();
|
||||
F->getBasicBlockList().insert(It, copy0MBB);
|
||||
F->getBasicBlockList().insert(It, sinkMBB);
|
||||
|
@ -140,7 +140,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
|
||||
unsigned C = MI->getOperand(2).getReg();
|
||||
unsigned M = MI->getOperand(3).getImmedValue();
|
||||
if (!Subtarget->hasSSE2() || B != C) return 0;
|
||||
return BuildMI(X86::PSHUFDri, 2, A).addReg(B).addImm(M);
|
||||
return BuildMI(*this, X86::PSHUFDri, 2, A).addReg(B).addImm(M);
|
||||
}
|
||||
}
|
||||
|
||||
@ -157,35 +157,35 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
|
||||
case X86::INC32r:
|
||||
case X86::INC64_32r:
|
||||
assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
|
||||
return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1);
|
||||
return addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, 1);
|
||||
case X86::INC16r:
|
||||
case X86::INC64_16r:
|
||||
if (DisableLEA16) return 0;
|
||||
assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
|
||||
return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1);
|
||||
return addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, 1);
|
||||
case X86::DEC32r:
|
||||
case X86::DEC64_32r:
|
||||
assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
|
||||
return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1);
|
||||
return addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, -1);
|
||||
case X86::DEC16r:
|
||||
case X86::DEC64_16r:
|
||||
if (DisableLEA16) return 0;
|
||||
assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
|
||||
return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1);
|
||||
return addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, -1);
|
||||
case X86::ADD32rr:
|
||||
assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
|
||||
return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src,
|
||||
return addRegReg(BuildMI(*this, X86::LEA32r, 5, Dest), Src,
|
||||
MI->getOperand(2).getReg());
|
||||
case X86::ADD16rr:
|
||||
if (DisableLEA16) return 0;
|
||||
assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
|
||||
return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src,
|
||||
return addRegReg(BuildMI(*this, X86::LEA16r, 5, Dest), Src,
|
||||
MI->getOperand(2).getReg());
|
||||
case X86::ADD32ri:
|
||||
case X86::ADD32ri8:
|
||||
assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
|
||||
if (MI->getOperand(2).isImmediate())
|
||||
return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src,
|
||||
return addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src,
|
||||
MI->getOperand(2).getImmedValue());
|
||||
return 0;
|
||||
case X86::ADD16ri:
|
||||
@ -193,7 +193,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
|
||||
if (DisableLEA16) return 0;
|
||||
assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
|
||||
if (MI->getOperand(2).isImmediate())
|
||||
return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src,
|
||||
return addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src,
|
||||
MI->getOperand(2).getImmedValue());
|
||||
break;
|
||||
|
||||
@ -208,7 +208,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
|
||||
AM.Scale = 1 << ShAmt;
|
||||
AM.IndexReg = Src;
|
||||
unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
|
||||
return addFullAddress(BuildMI(Opc, 5, Dest), AM);
|
||||
return addFullAddress(BuildMI(*this, Opc, 5, Dest), AM);
|
||||
}
|
||||
break;
|
||||
}
|
||||
@ -239,7 +239,7 @@ MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
|
||||
unsigned A = MI->getOperand(0).getReg();
|
||||
unsigned B = MI->getOperand(1).getReg();
|
||||
unsigned C = MI->getOperand(2).getReg();
|
||||
return BuildMI(Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt);
|
||||
return BuildMI(*this, Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt);
|
||||
}
|
||||
default:
|
||||
return TargetInstrInfo::commuteInstruction(MI);
|
||||
|
@ -165,7 +165,7 @@ static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
|
||||
const TargetInstrInfo &TII) {
|
||||
unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
|
||||
// Create the base instruction with the memory operand as the first part.
|
||||
MachineInstrBuilder MIB = addFrameReference(BuildMI(Opcode, 4+NumOps),
|
||||
MachineInstrBuilder MIB = addFrameReference(BuildMI(TII, Opcode, 4+NumOps),
|
||||
FrameIndex);
|
||||
|
||||
// Loop over the rest of the ri operands, converting them over.
|
||||
@ -188,7 +188,7 @@ static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
|
||||
static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
|
||||
unsigned FrameIndex, MachineInstr *MI,
|
||||
const TargetInstrInfo &TII) {
|
||||
MachineInstrBuilder MIB = BuildMI(Opcode, MI->getNumOperands()+3);
|
||||
MachineInstrBuilder MIB = BuildMI(TII, Opcode, MI->getNumOperands()+3);
|
||||
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
@ -209,9 +209,10 @@ static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
|
||||
return MIB;
|
||||
}
|
||||
|
||||
static MachineInstr *MakeM0Inst(unsigned Opcode, unsigned FrameIndex,
|
||||
static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII,
|
||||
unsigned Opcode, unsigned FrameIndex,
|
||||
MachineInstr *MI) {
|
||||
return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addImm(0);
|
||||
return addFrameReference(BuildMI(TII, Opcode, 5), FrameIndex).addImm(0);
|
||||
}
|
||||
|
||||
|
||||
@ -464,13 +465,13 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
|
||||
isTwoAddrFold = true;
|
||||
} else if (i == 0) { // If operand 0
|
||||
if (MI->getOpcode() == X86::MOV16r0)
|
||||
return MakeM0Inst(X86::MOV16mi, FrameIndex, MI);
|
||||
return MakeM0Inst(TII, X86::MOV16mi, FrameIndex, MI);
|
||||
else if (MI->getOpcode() == X86::MOV32r0)
|
||||
return MakeM0Inst(X86::MOV32mi, FrameIndex, MI);
|
||||
return MakeM0Inst(TII, X86::MOV32mi, FrameIndex, MI);
|
||||
else if (MI->getOpcode() == X86::MOV64r0)
|
||||
return MakeM0Inst(X86::MOV64mi32, FrameIndex, MI);
|
||||
return MakeM0Inst(TII, X86::MOV64mi32, FrameIndex, MI);
|
||||
else if (MI->getOpcode() == X86::MOV8r0)
|
||||
return MakeM0Inst(X86::MOV8mi, FrameIndex, MI);
|
||||
return MakeM0Inst(TII, X86::MOV8mi, FrameIndex, MI);
|
||||
|
||||
static const TableEntry OpcodeTable[] = {
|
||||
{ X86::CMP16ri, X86::CMP16mi },
|
||||
@ -899,7 +900,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||
|
||||
MachineInstr *New = 0;
|
||||
if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
|
||||
New=BuildMI(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri, 1, StackPtr)
|
||||
New=BuildMI(TII, Is64Bit ? X86::SUB64ri32 : X86::SUB32ri, 1, StackPtr)
|
||||
.addReg(StackPtr).addImm(Amount);
|
||||
} else {
|
||||
assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
|
||||
@ -910,7 +911,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||
unsigned Opc = (Amount < 128) ?
|
||||
(Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
|
||||
(Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
|
||||
New = BuildMI(Opc, 1, StackPtr).addReg(StackPtr).addImm(Amount);
|
||||
New = BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(Amount);
|
||||
}
|
||||
}
|
||||
|
||||
@ -926,7 +927,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||
(Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
|
||||
(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
|
||||
MachineInstr *New =
|
||||
BuildMI(Opc, 1, StackPtr).addReg(StackPtr).addImm(CalleeAmt);
|
||||
BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(CalleeAmt);
|
||||
MBB.insert(I, New);
|
||||
}
|
||||
}
|
||||
@ -1003,15 +1004,15 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||
// more than 4k bytes in one go. Touching the stack at 4K increments is
|
||||
// necessary to ensure that the guard pages used by the OS virtual memory
|
||||
// manager are allocated in correct sequence.
|
||||
MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(NumBytes);
|
||||
MI = BuildMI(TII, X86::MOV32ri, 2, X86::EAX).addImm(NumBytes);
|
||||
MBB.insert(MBBI, MI);
|
||||
MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("_alloca");
|
||||
MI = BuildMI(TII, X86::CALLpcrel32, 1).addExternalSymbol("_alloca");
|
||||
MBB.insert(MBBI, MI);
|
||||
} else {
|
||||
unsigned Opc = (NumBytes < 128) ?
|
||||
(Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
|
||||
(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
|
||||
MI= BuildMI(Opc, 1, StackPtr).addReg(StackPtr).addImm(NumBytes);
|
||||
MI= BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(NumBytes);
|
||||
MBB.insert(MBBI, MI);
|
||||
}
|
||||
}
|
||||
@ -1023,16 +1024,16 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||
|
||||
// Save EBP into the appropriate stack slot...
|
||||
// mov [ESP-<offset>], EBP
|
||||
MI = addRegOffset(BuildMI(Is64Bit ? X86::MOV64mr : X86::MOV32mr, 5),
|
||||
MI = addRegOffset(BuildMI(TII, Is64Bit ? X86::MOV64mr : X86::MOV32mr, 5),
|
||||
StackPtr, EBPOffset+NumBytes).addReg(FramePtr);
|
||||
MBB.insert(MBBI, MI);
|
||||
|
||||
// Update EBP with the new base value...
|
||||
if (NumBytes == SlotSize) // mov EBP, ESP
|
||||
MI = BuildMI(Is64Bit ? X86::MOV64rr : X86::MOV32rr, 2, FramePtr).
|
||||
MI = BuildMI(TII, Is64Bit ? X86::MOV64rr : X86::MOV32rr, 2, FramePtr).
|
||||
addReg(StackPtr);
|
||||
else // lea EBP, [ESP+StackSize]
|
||||
MI = addRegOffset(BuildMI(Is64Bit ? X86::LEA64r : X86::LEA32r,
|
||||
MI = addRegOffset(BuildMI(TII, Is64Bit ? X86::LEA64r : X86::LEA32r,
|
||||
5, FramePtr), StackPtr, NumBytes-SlotSize);
|
||||
|
||||
MBB.insert(MBBI, MI);
|
||||
@ -1041,13 +1042,13 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||
// If it's main() on Cygwin\Mingw32 we should align stack as well
|
||||
if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
|
||||
Subtarget->isTargetCygwin()) {
|
||||
MI = BuildMI(X86::AND32ri, 2, X86::ESP).addReg(X86::ESP).addImm(-Align);
|
||||
MI= BuildMI(TII, X86::AND32ri, 2, X86::ESP).addReg(X86::ESP).addImm(-Align);
|
||||
MBB.insert(MBBI, MI);
|
||||
|
||||
// Probe the stack
|
||||
MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(Align);
|
||||
MI = BuildMI(TII, X86::MOV32ri, 2, X86::EAX).addImm(Align);
|
||||
MBB.insert(MBBI, MI);
|
||||
MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("_alloca");
|
||||
MI = BuildMI(TII, X86::CALLpcrel32, 1).addExternalSymbol("_alloca");
|
||||
MBB.insert(MBBI, MI);
|
||||
}
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user