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Handle some non-exit blocks in tail merging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36907 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -50,11 +50,14 @@ namespace {
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private:
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// Tail Merging.
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bool TailMergeBlocks(MachineFunction &MF);
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bool TryMergeBlocks(MachineBasicBlock* SuccBB,
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MachineBasicBlock* PredBB);
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void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
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MachineBasicBlock *NewDest);
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MachineBasicBlock *SplitMBBAt(MachineBasicBlock &CurMBB,
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MachineBasicBlock::iterator BBI1);
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std::vector<std::pair<unsigned,MachineBasicBlock*> > MergePotentials;
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const MRegisterInfo *RegInfo;
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RegScavenger *RS;
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// Branch optzn.
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@ -346,18 +349,18 @@ static bool ShouldSplitFirstBlock(MachineBasicBlock *MBB1,
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return MBB1Time < MBB2Time;
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}
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bool BranchFolder::TailMergeBlocks(MachineFunction &MF) {
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// See if any of the blocks in MergePotentials (which all have a common single
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// successor, or all have no successor) can be tail-merged. If there is a
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// successor, any blocks in MergePotentials that are not tail-merged and
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// are not immediately before Succ must have an unconditional branch to
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// Succ added (but the predecessor/successor lists need no adjustment).
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// The lone predecessor of Succ that falls through into Succ,
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// if any, is given in PredBB.
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bool BranchFolder::TryMergeBlocks(MachineBasicBlock *SuccBB,
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MachineBasicBlock* PredBB) {
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MadeChange = false;
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if (!EnableTailMerge) return false;
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// Find blocks with no successors.
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std::vector<std::pair<unsigned,MachineBasicBlock*> > MergePotentials;
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
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if (I->succ_empty())
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MergePotentials.push_back(std::make_pair(HashEndOfMBB(I), I));
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}
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// Sort by hash value so that blocks with identical end sequences sort
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// together.
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std::stable_sort(MergePotentials.begin(), MergePotentials.end());
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@ -371,6 +374,8 @@ bool BranchFolder::TailMergeBlocks(MachineFunction &MF) {
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// If there is nothing that matches the hash of the current basic block,
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// give up.
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if (CurHash != PrevHash) {
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if (SuccBB && CurMBB != PredBB)
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TII->InsertBranch(*CurMBB, SuccBB, NULL, std::vector<MachineOperand>());
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MergePotentials.pop_back();
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continue;
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}
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@ -401,6 +406,9 @@ bool BranchFolder::TailMergeBlocks(MachineFunction &MF) {
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// If we didn't find anything that has at least two instructions matching
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// this one, bail out.
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if (FoundMatch == ~0U) {
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// Put the unconditional branch back, if we need one.
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if (SuccBB && CurMBB != PredBB)
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TII->InsertBranch(*CurMBB, SuccBB, NULL, std::vector<MachineOperand>());
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MergePotentials.pop_back();
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continue;
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}
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@ -445,10 +453,72 @@ bool BranchFolder::TailMergeBlocks(MachineFunction &MF) {
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}
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MadeChange = true;
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}
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return MadeChange;
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}
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bool BranchFolder::TailMergeBlocks(MachineFunction &MF) {
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MadeChange = false;
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if (!EnableTailMerge) return false;
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// First find blocks with no successors.
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
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if (I->succ_empty())
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MergePotentials.push_back(std::make_pair(HashEndOfMBB(I), I));
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}
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// See if we can do any crossjumping on those.
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MadeChange |= TryMergeBlocks(NULL, NULL);
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MergePotentials.clear();
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// Look at blocks with two predecessors, where each predecessor has either:
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// - a single successor, or
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// - two successors, where successor I is reached either by ubr or fallthrough.
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// The two-successor case where successor I is reached by cbr
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// from both blocks is handled by the preceding case (when we consider the
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// other, fallthough block).
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// FIXME: The two-successor case where I is reached by cbr
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// from one block, and by fallthrough/ubr from the other, is not handled yet.
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// Beware that sometimes blocks are in the predecessor list, but can't really
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// jump to the "successor" we're looking at. Tolerate this.
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
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if (!I->succ_empty() && I->pred_size() >= 2) {
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MachineBasicBlock *IBB = I;
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MachineBasicBlock *PredBB = prior(I);
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for (MachineBasicBlock::pred_iterator P = I->pred_begin(), E2 = I->pred_end();
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P != E2; ++P) {
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MachineBasicBlock* PBB = *P;
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MachineBasicBlock *TBB = 0, *FBB = 0;
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std::vector<MachineOperand> Cond;
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// Remove the unconditional branch at the end, if any.
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if (!TII->AnalyzeBranch(*PBB, TBB, FBB, Cond) &&
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((!FBB && Cond.size()==0) || // single successor
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(!FBB && TBB!=IBB) || // cbr elsewhere, fallthrough to I
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(FBB && FBB==IBB))) { // cbr then branch to I
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if (TBB) {
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TII->RemoveBranch(*PBB);
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if (TBB!=IBB)
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// reinsert conditional branch only, for now
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TII->InsertBranch(*PBB, TBB, 0, Cond);
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}
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MergePotentials.push_back(std::make_pair(HashEndOfMBB(PBB), *P));
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}
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}
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if (MergePotentials.size() >= 2)
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MadeChange |= TryMergeBlocks(I, PredBB);
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// Reinsert an unconditional branch if needed.
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// The 1 below can be either an original single predecessor, or a result
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// of removing blocks in TryMergeBlocks.
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if (MergePotentials.size()==1 &&
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(MergePotentials.begin())->second != PredBB)
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TII->InsertBranch(*((MergePotentials.begin())->second), I, NULL,
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std::vector<MachineOperand>());
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MergePotentials.clear();
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}
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}
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return MadeChange;
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}
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//===----------------------------------------------------------------------===//
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// Branch Optimization
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65
test/CodeGen/Generic/2007-05-07-tailmerge-1.c
Normal file
65
test/CodeGen/Generic/2007-05-07-tailmerge-1.c
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@ -0,0 +1,65 @@
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; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge | grep bl.*baz | wc -l | grep 1
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; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge | grep bl.*quux | wc -l | grep 1
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; Check that calls to baz and quux are tail-merged.
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; ModuleID = 'tail.c'
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
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target triple = "i686-apple-darwin8"
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define i32 @f(i32 %i, i32 %q) {
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entry:
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%i_addr = alloca i32 ; <i32*> [#uses=2]
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%q_addr = alloca i32 ; <i32*> [#uses=2]
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%retval = alloca i32, align 4 ; <i32*> [#uses=1]
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"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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store i32 %i, i32* %i_addr
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store i32 %q, i32* %q_addr
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%tmp = load i32* %i_addr ; <i32> [#uses=1]
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%tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1]
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%tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1]
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%toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1]
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br i1 %toBool, label %cond_true, label %cond_false
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cond_true: ; preds = %entry
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%tmp3 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
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%tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
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br label %cond_next
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cond_false: ; preds = %entry
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%tmp5 = call i32 (...)* @foo( ) ; <i32> [#uses=0]
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%tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
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br label %cond_next
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cond_next: ; preds = %cond_false, %cond_true
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%tmp7 = load i32* %q_addr ; <i32> [#uses=1]
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%tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1]
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%tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1]
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%toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1]
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br i1 %toBool10, label %cond_true11, label %cond_false15
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cond_true11: ; preds = %cond_next
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%tmp13 = call i32 (...)* @foo( ) ; <i32> [#uses=0]
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%tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
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br label %cond_next18
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cond_false15: ; preds = %cond_next
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%tmp16 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
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%tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
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br label %cond_next18
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cond_next18: ; preds = %cond_false15, %cond_true11
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%tmp19 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
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br label %return
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return: ; preds = %cond_next18
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%retval20 = load i32* %retval ; <i32> [#uses=1]
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ret i32 %retval20
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}
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declare i32 @bar(...)
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declare i32 @baz(...)
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declare i32 @foo(...)
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declare i32 @quux(...)
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