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ARMLoadStoreOptimizer: Fix errata 602117 handling and make testcase actually test for it
This fixes PR23912 Differential Revision: http://reviews.llvm.org/D10620 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240582 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun
@@ -1464,119 +1464,124 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI) {
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MachineInstr *MI = &*MBBI;
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unsigned Opcode = MI->getOpcode();
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if (Opcode == ARM::LDRD || Opcode == ARM::STRD) {
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const MachineOperand &BaseOp = MI->getOperand(2);
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unsigned BaseReg = BaseOp.getReg();
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unsigned EvenReg = MI->getOperand(0).getReg();
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unsigned OddReg = MI->getOperand(1).getReg();
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unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false);
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unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false);
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// ARM errata 602117: LDRD with base in list may result in incorrect base
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// register when interrupted or faulted.
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bool Errata602117 = EvenReg == BaseReg && STI->isCortexM3();
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if (!Errata602117 &&
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((EvenRegNum & 1) == 0 && (EvenRegNum + 1) == OddRegNum))
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return false;
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if (Opcode != ARM::LDRD && Opcode != ARM::STRD && Opcode != ARM::t2LDRDi8)
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return false;
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MachineBasicBlock::iterator NewBBI = MBBI;
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bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8;
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bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;
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bool EvenDeadKill = isLd ?
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MI->getOperand(0).isDead() : MI->getOperand(0).isKill();
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bool EvenUndef = MI->getOperand(0).isUndef();
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bool OddDeadKill = isLd ?
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MI->getOperand(1).isDead() : MI->getOperand(1).isKill();
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bool OddUndef = MI->getOperand(1).isUndef();
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bool BaseKill = BaseOp.isKill();
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bool BaseUndef = BaseOp.isUndef();
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bool OffKill = isT2 ? false : MI->getOperand(3).isKill();
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bool OffUndef = isT2 ? false : MI->getOperand(3).isUndef();
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int OffImm = getMemoryOpOffset(MI);
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unsigned PredReg = 0;
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ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
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const MachineOperand &BaseOp = MI->getOperand(2);
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unsigned BaseReg = BaseOp.getReg();
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unsigned EvenReg = MI->getOperand(0).getReg();
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unsigned OddReg = MI->getOperand(1).getReg();
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unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false);
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unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false);
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if (OddRegNum > EvenRegNum && OffImm == 0) {
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// Ascending register numbers and no offset. It's safe to change it to a
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// ldm or stm.
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unsigned NewOpc = (isLd)
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? (isT2 ? ARM::t2LDMIA : ARM::LDMIA)
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: (isT2 ? ARM::t2STMIA : ARM::STMIA);
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if (isLd) {
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BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
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.addReg(BaseReg, getKillRegState(BaseKill))
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.addImm(Pred).addReg(PredReg)
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.addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
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.addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill));
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++NumLDRD2LDM;
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} else {
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BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
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.addReg(BaseReg, getKillRegState(BaseKill))
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.addImm(Pred).addReg(PredReg)
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.addReg(EvenReg,
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getKillRegState(EvenDeadKill) | getUndefRegState(EvenUndef))
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.addReg(OddReg,
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getKillRegState(OddDeadKill) | getUndefRegState(OddUndef));
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++NumSTRD2STM;
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}
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NewBBI = std::prev(MBBI);
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// ARM errata 602117: LDRD with base in list may result in incorrect base
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// register when interrupted or faulted.
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bool Errata602117 = EvenReg == BaseReg &&
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(Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8) && STI->isCortexM3();
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// ARM LDRD/STRD needs consecutive registers.
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bool NonConsecutiveRegs = (Opcode == ARM::LDRD || Opcode == ARM::STRD) &&
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(EvenRegNum % 2 != 0 || EvenRegNum + 1 != OddRegNum);
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if (!Errata602117 && !NonConsecutiveRegs)
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return false;
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MachineBasicBlock::iterator NewBBI = MBBI;
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bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8;
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bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;
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bool EvenDeadKill = isLd ?
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MI->getOperand(0).isDead() : MI->getOperand(0).isKill();
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bool EvenUndef = MI->getOperand(0).isUndef();
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bool OddDeadKill = isLd ?
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MI->getOperand(1).isDead() : MI->getOperand(1).isKill();
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bool OddUndef = MI->getOperand(1).isUndef();
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bool BaseKill = BaseOp.isKill();
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bool BaseUndef = BaseOp.isUndef();
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bool OffKill = isT2 ? false : MI->getOperand(3).isKill();
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bool OffUndef = isT2 ? false : MI->getOperand(3).isUndef();
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int OffImm = getMemoryOpOffset(MI);
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unsigned PredReg = 0;
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ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
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if (OddRegNum > EvenRegNum && OffImm == 0) {
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// Ascending register numbers and no offset. It's safe to change it to a
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// ldm or stm.
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unsigned NewOpc = (isLd)
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? (isT2 ? ARM::t2LDMIA : ARM::LDMIA)
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: (isT2 ? ARM::t2STMIA : ARM::STMIA);
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if (isLd) {
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BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
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.addReg(BaseReg, getKillRegState(BaseKill))
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.addImm(Pred).addReg(PredReg)
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.addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
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.addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill));
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++NumLDRD2LDM;
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} else {
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// Split into two instructions.
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unsigned NewOpc = (isLd)
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? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12)
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: (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12);
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// Be extra careful for thumb2. t2LDRi8 can't reference a zero offset,
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// so adjust and use t2LDRi12 here for that.
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unsigned NewOpc2 = (isLd)
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? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12)
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: (isT2 ? (OffImm+4 < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12);
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DebugLoc dl = MBBI->getDebugLoc();
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// If this is a load and base register is killed, it may have been
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// re-defed by the load, make sure the first load does not clobber it.
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if (isLd &&
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(BaseKill || OffKill) &&
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(TRI->regsOverlap(EvenReg, BaseReg))) {
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assert(!TRI->regsOverlap(OddReg, BaseReg));
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InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc2,
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OddReg, OddDeadKill, false,
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BaseReg, false, BaseUndef, false, OffUndef,
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Pred, PredReg, TII, isT2);
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NewBBI = std::prev(MBBI);
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InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
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EvenReg, EvenDeadKill, false,
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BaseReg, BaseKill, BaseUndef, OffKill, OffUndef,
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Pred, PredReg, TII, isT2);
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} else {
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if (OddReg == EvenReg && EvenDeadKill) {
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// If the two source operands are the same, the kill marker is
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// probably on the first one. e.g.
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// t2STRDi8 %R5<kill>, %R5, %R9<kill>, 0, 14, %reg0
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EvenDeadKill = false;
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OddDeadKill = true;
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}
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// Never kill the base register in the first instruction.
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if (EvenReg == BaseReg)
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EvenDeadKill = false;
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InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
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EvenReg, EvenDeadKill, EvenUndef,
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BaseReg, false, BaseUndef, false, OffUndef,
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Pred, PredReg, TII, isT2);
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NewBBI = std::prev(MBBI);
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InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc2,
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OddReg, OddDeadKill, OddUndef,
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BaseReg, BaseKill, BaseUndef, OffKill, OffUndef,
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Pred, PredReg, TII, isT2);
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}
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if (isLd)
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++NumLDRD2LDR;
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else
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++NumSTRD2STR;
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BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
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.addReg(BaseReg, getKillRegState(BaseKill))
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.addImm(Pred).addReg(PredReg)
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.addReg(EvenReg,
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getKillRegState(EvenDeadKill) | getUndefRegState(EvenUndef))
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.addReg(OddReg,
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getKillRegState(OddDeadKill) | getUndefRegState(OddUndef));
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++NumSTRD2STM;
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}
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MBB.erase(MI);
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MBBI = NewBBI;
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return true;
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NewBBI = std::prev(MBBI);
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} else {
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// Split into two instructions.
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unsigned NewOpc = (isLd)
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? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12)
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: (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12);
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// Be extra careful for thumb2. t2LDRi8 can't reference a zero offset,
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// so adjust and use t2LDRi12 here for that.
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unsigned NewOpc2 = (isLd)
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? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12)
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: (isT2 ? (OffImm+4 < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12);
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DebugLoc dl = MBBI->getDebugLoc();
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// If this is a load and base register is killed, it may have been
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// re-defed by the load, make sure the first load does not clobber it.
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if (isLd &&
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(BaseKill || OffKill) &&
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(TRI->regsOverlap(EvenReg, BaseReg))) {
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assert(!TRI->regsOverlap(OddReg, BaseReg));
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InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc2,
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OddReg, OddDeadKill, false,
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BaseReg, false, BaseUndef, false, OffUndef,
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Pred, PredReg, TII, isT2);
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NewBBI = std::prev(MBBI);
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InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
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EvenReg, EvenDeadKill, false,
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BaseReg, BaseKill, BaseUndef, OffKill, OffUndef,
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Pred, PredReg, TII, isT2);
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} else {
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if (OddReg == EvenReg && EvenDeadKill) {
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// If the two source operands are the same, the kill marker is
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// probably on the first one. e.g.
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// t2STRDi8 %R5<kill>, %R5, %R9<kill>, 0, 14, %reg0
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EvenDeadKill = false;
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OddDeadKill = true;
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}
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// Never kill the base register in the first instruction.
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if (EvenReg == BaseReg)
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EvenDeadKill = false;
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InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
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EvenReg, EvenDeadKill, EvenUndef,
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BaseReg, false, BaseUndef, false, OffUndef,
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Pred, PredReg, TII, isT2);
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NewBBI = std::prev(MBBI);
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InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc2,
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OddReg, OddDeadKill, OddUndef,
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BaseReg, BaseKill, BaseUndef, OffKill, OffUndef,
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Pred, PredReg, TII, isT2);
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}
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if (isLd)
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++NumLDRD2LDR;
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else
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++NumSTRD2STR;
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}
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return false;
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MBB.erase(MI);
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MBBI = NewBBI;
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return true;
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}
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/// An optimization pass to turn multiple LDR / STR ops of the same base and
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