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Add a quick pass to optimize sign / zero extension instructions. For targets where the pre-extension values are available in the subreg of the result of the extension, replace the uses of the pre-extension value with the result + extract_subreg.
For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93278 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -170,6 +170,10 @@ namespace llvm {
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/// instructions.
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FunctionPass *createMachineSinkingPass();
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/// createOptimizeExtsPass - This pass performs sign / zero extension
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/// optimization by increasing uses of extended values.
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FunctionPass *createOptimizeExtsPass();
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/// createStackSlotColoringPass - This pass performs stack slot coloring.
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FunctionPass *createStackSlotColoringPass(bool);
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@ -149,16 +149,15 @@ public:
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return false;
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}
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/// isCoalescableInstr - Return true if the instruction is "coalescable". That
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/// is, it's like a copy where it's legal for the source to overlap the
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/// destination. e.g. X86::MOVSX64rr32.
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virtual bool isCoalescableInstr(const MachineInstr &MI, bool &isCopy,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
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if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
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isCopy = true;
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return true;
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}
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/// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
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/// extension instruction. That is, it's like a copy where it's legal for the
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/// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
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/// true, then it's expected the pre-extension value is available as a subreg
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/// of the result register. This also returns the sub-register index in
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/// SubIdx.
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virtual bool isCoalescableExtInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SubIdx) const {
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return false;
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}
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@ -62,6 +62,10 @@ static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
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cl::desc("Verify generated machine code"),
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cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
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#if 1
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static cl::opt<bool> XX("xx", cl::Hidden);
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#endif
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// Enable or disable FastISel. Both options are needed, because
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// FastISel is enabled by default with -fast, and we wish to be
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// able to enable or disable fast-isel independently from -O0.
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@ -324,6 +328,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
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/* allowDoubleDefs= */ true);
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if (OptLevel != CodeGenOpt::None) {
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PM.add(createOptimizeExtsPass());
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if (!DisableMachineLICM)
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PM.add(createMachineLICMPass());
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if (!DisableMachineSink)
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149
lib/CodeGen/OptimizeExts.cpp
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149
lib/CodeGen/OptimizeExts.cpp
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@ -0,0 +1,149 @@
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//===-- OptimizeExts.cpp - Optimize sign / zero extension instrs -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "ext-opt"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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static cl::opt<bool> Aggressive("aggressive-ext-opt", cl::Hidden,
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cl::desc("Aggressive extension optimization"));
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STATISTIC(NumReuse, "Number of extension results reused");
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namespace {
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class OptimizeExts : public MachineFunctionPass {
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const TargetMachine *TM;
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const TargetInstrInfo *TII;
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MachineRegisterInfo *MRI;
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MachineDominatorTree *DT; // Machine dominator tree
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public:
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static char ID; // Pass identification
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OptimizeExts() : MachineFunctionPass(&ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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}
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};
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}
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char OptimizeExts::ID = 0;
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static RegisterPass<OptimizeExts>
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X("opt-exts", "Optimize sign / zero extensions");
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FunctionPass *llvm::createOptimizeExtsPass() { return new OptimizeExts(); }
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bool OptimizeExts::runOnMachineFunction(MachineFunction &MF) {
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TM = &MF.getTarget();
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TII = TM->getInstrInfo();
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MRI = &MF.getRegInfo();
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DT = &getAnalysis<MachineDominatorTree>();
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bool Changed = false;
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SmallPtrSet<MachineInstr*, 8> LocalMIs;
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
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MachineBasicBlock *MBB = &*I;
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for (MachineBasicBlock::iterator MII = I->begin(), ME = I->end(); MII != ME;
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++MII) {
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MachineInstr *MI = &*MII;
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LocalMIs.insert(MI);
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unsigned SrcReg, DstReg, SubIdx;
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if (TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) {
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if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
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TargetRegisterInfo::isPhysicalRegister(SrcReg))
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continue;
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MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg);
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if (++UI == MRI->use_end())
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// No other uses.
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continue;
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// Ok, the source has other uses. See if we can replace the other uses
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// with use of the result of the extension.
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SmallPtrSet<MachineBasicBlock*, 4> ReachedBBs;
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UI = MRI->use_begin(DstReg);
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for (MachineRegisterInfo::use_iterator UE = MRI->use_end(); UI != UE;
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++UI)
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ReachedBBs.insert(UI->getParent());
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bool ExtendLife = true;
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SmallVector<MachineOperand*, 8> Uses;
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SmallVector<MachineOperand*, 8> ExtendedUses;
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UI = MRI->use_begin(SrcReg);
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for (MachineRegisterInfo::use_iterator UE = MRI->use_end(); UI != UE;
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++UI) {
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MachineOperand &UseMO = UI.getOperand();
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MachineInstr *UseMI = &*UI;
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if (UseMI == MI)
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continue;
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MachineBasicBlock *UseMBB = UseMI->getParent();
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if (UseMBB == MBB) {
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// Local uses that come after the extension.
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if (!LocalMIs.count(UseMI))
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Uses.push_back(&UseMO);
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} else if (ReachedBBs.count(UseMBB))
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// Non-local uses where the result of extension is used. Always
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// replace these.
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Uses.push_back(&UseMO);
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else if (Aggressive && DT->dominates(MBB, UseMBB))
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// We may want to extend live range of the extension result in order
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// to replace these uses.
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ExtendedUses.push_back(&UseMO);
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else {
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// Both will be live out of the def MBB anyway. Don't extend live
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// range of the extension result.
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ExtendLife = false;
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break;
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}
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}
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if (ExtendLife && !ExtendedUses.empty())
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// Ok, we'll extend the liveness of the extension result.
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std::copy(ExtendedUses.begin(), ExtendedUses.end(),
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std::back_inserter(Uses));
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// Now replace all uses.
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if (!Uses.empty()) {
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const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
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for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
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MachineOperand *UseMO = Uses[i];
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MachineInstr *UseMI = UseMO->getParent();
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MachineBasicBlock *UseMBB = UseMI->getParent();
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unsigned NewVR = MRI->createVirtualRegister(RC);
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BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
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TII->get(TargetInstrInfo::EXTRACT_SUBREG), NewVR)
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.addReg(DstReg).addImm(SubIdx);
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UseMO->setReg(NewVR);
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++NumReuse;
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Changed = true;
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}
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}
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}
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}
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}
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return Changed;
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}
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@ -713,9 +713,9 @@ bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
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}
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bool
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X86InstrInfo::isCoalescableInstr(const MachineInstr &MI, bool &isCopy,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
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X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SubIdx) const {
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switch (MI.getOpcode()) {
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default: break;
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case X86::MOVSX16rr8:
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@ -733,10 +733,8 @@ X86InstrInfo::isCoalescableInstr(const MachineInstr &MI, bool &isCopy,
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if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
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// Be conservative.
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return false;
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isCopy = false;
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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DstSubIdx = 0;
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switch (MI.getOpcode()) {
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default:
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llvm_unreachable(0);
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@ -747,22 +745,23 @@ X86InstrInfo::isCoalescableInstr(const MachineInstr &MI, bool &isCopy,
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case X86::MOVZX32rr8:
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case X86::MOVSX64rr8:
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case X86::MOVZX64rr8:
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SrcSubIdx = 1;
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SubIdx = 1;
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break;
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case X86::MOVSX32rr16:
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case X86::MOVZX32rr16:
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case X86::MOVSX64rr16:
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case X86::MOVZX64rr16:
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SrcSubIdx = 3;
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SubIdx = 3;
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break;
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case X86::MOVSX64rr32:
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case X86::MOVZX64rr32:
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SrcSubIdx = 4;
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SubIdx = 4;
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break;
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}
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return true;
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}
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}
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return isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
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return false;
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}
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/// isFrameOperand - Return true and the FrameIndex if the specified
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
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/// isCoalescableInstr - Return true if the instruction is "coalescable". That
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/// is, it's like a copy where it's legal for the source to overlap the
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/// destination. e.g. X86::MOVSX64rr32.
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virtual bool isCoalescableInstr(const MachineInstr &MI, bool &isCopy,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
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/// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
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/// extension instruction. That is, it's like a copy where it's legal for the
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/// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
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/// true, then it's expected the pre-extension value is available as a subreg
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/// of the result register. This also returns the sub-register index in
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/// SubIdx.
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virtual bool isCoalescableExtInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SubIdx) const;
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unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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/// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
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@ -1,4 +1,4 @@
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; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim -stats |& grep asm-printer | grep 58
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; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim -stats |& grep asm-printer | grep 57
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; PR2568
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@g_3 = external global i16 ; <i16*> [#uses=1]
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17
test/CodeGen/X86/sext-subreg.ll
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17
test/CodeGen/X86/sext-subreg.ll
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@ -0,0 +1,17 @@
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; RUN: llc < %s -march=x86-64 | FileCheck %s
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; rdar://7529457
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define i64 @t(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
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; CHECK: t:
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; CHECK: movslq %e{{.*}}, %rax
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; CHECK: movq %rax
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; CHECK: movl %eax
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%C = add i64 %A, %B
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%D = trunc i64 %C to i32
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volatile store i32 %D, i32* %P
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%E = shl i64 %C, 32
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%F = ashr i64 %E, 32
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volatile store i64 %F, i64 *%P2
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volatile store i32 %D, i32* %P
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ret i64 undef
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}
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@ -1,5 +1,5 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t
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; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 6
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; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 9
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type { [62 x %struct.Bitvec*] } ; type %0
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type { i8* } ; type %1
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