6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-19 04:29:21 +00:00
Code Issues Projects Releases Wiki Activity

Use target specific interface instead of forcing it to be target-generic

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7413 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2003-07-30 05:33:48 +00:00
parent 92988ecdb6
commit 7db1fa9802
2 changed files with 12 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/X86/InstSelectSimple.cpp
View File

@ -219,9 +219,12 @@ namespace {
/// of the long value.
///
unsigned makeAnotherReg(const Type *Ty) {
assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
"Current target doesn't have X86 reg info??");
const X86RegisterInfo *MRI =
static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
if (Ty == Type::LongTy || Ty == Type::ULongTy) {
const TargetRegisterClass *RC =
TM.getRegisterInfo()->getRegClassForType(Type::IntTy);
const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
// Create the lower part
F->getSSARegMap()->createVirtualRegister(RC);
// Create the upper part.
@ -229,8 +232,7 @@ namespace {
}
// Add the mapping of regnumber => reg class to MachineFunction
const TargetRegisterClass *RC =
TM.getRegisterInfo()->getRegClassForType(Ty);
const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
return F->getSSARegMap()->createVirtualRegister(RC);
}

10
lib/Target/X86/X86ISelSimple.cpp
View File

@ -219,9 +219,12 @@ namespace {
/// of the long value.
///
unsigned makeAnotherReg(const Type *Ty) {
assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
"Current target doesn't have X86 reg info??");
const X86RegisterInfo *MRI =
static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
if (Ty == Type::LongTy || Ty == Type::ULongTy) {
const TargetRegisterClass *RC =
TM.getRegisterInfo()->getRegClassForType(Type::IntTy);
const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
// Create the lower part
F->getSSARegMap()->createVirtualRegister(RC);
// Create the upper part.
@ -229,8 +232,7 @@ namespace {
}
// Add the mapping of regnumber => reg class to MachineFunction
const TargetRegisterClass *RC =
TM.getRegisterInfo()->getRegClassForType(Ty);
const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
return F->getSSARegMap()->createVirtualRegister(RC);
}