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Use target specific interface instead of forcing it to be target-generic

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7413 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2003-07-30 05:33:48 +00:00
parent 92988ecdb6
commit 7db1fa9802
2 changed files with 12 additions and 8 deletions
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10
lib/Target/X86/InstSelectSimple.cpp
View File

@ -219,9 +219,12 @@ namespace {
/// of the long value. /// of the long value.
/// ///
unsigned makeAnotherReg(const Type *Ty) { unsigned makeAnotherReg(const Type *Ty) {
assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
"Current target doesn't have X86 reg info??");
const X86RegisterInfo *MRI =
static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
if (Ty == Type::LongTy || Ty == Type::ULongTy) { if (Ty == Type::LongTy || Ty == Type::ULongTy) {
const TargetRegisterClass *RC = const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
TM.getRegisterInfo()->getRegClassForType(Type::IntTy);
// Create the lower part // Create the lower part
F->getSSARegMap()->createVirtualRegister(RC); F->getSSARegMap()->createVirtualRegister(RC);
// Create the upper part. // Create the upper part.
@ -229,8 +232,7 @@ namespace {
} }
// Add the mapping of regnumber => reg class to MachineFunction // Add the mapping of regnumber => reg class to MachineFunction
const TargetRegisterClass *RC = const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
TM.getRegisterInfo()->getRegClassForType(Ty);
return F->getSSARegMap()->createVirtualRegister(RC); return F->getSSARegMap()->createVirtualRegister(RC);
} }

10
lib/Target/X86/X86ISelSimple.cpp
View File

@ -219,9 +219,12 @@ namespace {
/// of the long value. /// of the long value.
/// ///
unsigned makeAnotherReg(const Type *Ty) { unsigned makeAnotherReg(const Type *Ty) {
assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
"Current target doesn't have X86 reg info??");
const X86RegisterInfo *MRI =
static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
if (Ty == Type::LongTy || Ty == Type::ULongTy) { if (Ty == Type::LongTy || Ty == Type::ULongTy) {
const TargetRegisterClass *RC = const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
TM.getRegisterInfo()->getRegClassForType(Type::IntTy);
// Create the lower part // Create the lower part
F->getSSARegMap()->createVirtualRegister(RC); F->getSSARegMap()->createVirtualRegister(RC);
// Create the upper part. // Create the upper part.
@ -229,8 +232,7 @@ namespace {
} }
// Add the mapping of regnumber => reg class to MachineFunction // Add the mapping of regnumber => reg class to MachineFunction
const TargetRegisterClass *RC = const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
TM.getRegisterInfo()->getRegClassForType(Ty);
return F->getSSARegMap()->createVirtualRegister(RC); return F->getSSARegMap()->createVirtualRegister(RC);
} }