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Add AVX SHUF{PS,PD}{rr,rm} instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106672 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1394,33 +1394,37 @@ def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
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(CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
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// Shuffle and unpack instructions
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multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
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ValueType vt, string asm, PatFrag mem_frag,
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Domain d, bit IsConvertibleToThreeAddress = 0> {
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def rmi : PIi8<0xC6, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, i8imm:$src3), asm,
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[(set VR128:$dst, (vt (shufp:$src3
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VR128:$src1, (mem_frag addr:$src2))))], d>;
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let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
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def rri : PIi8<0xC6, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3), asm,
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[(set VR128:$dst,
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(vt (shufp:$src3 VR128:$src1, VR128:$src2)))], d>;
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}
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let Constraints = "$src1 = $dst" in {
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let isConvertibleToThreeAddress = 1 in // Convert to pshufd
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def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1,
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VR128:$src2, i8imm:$src3),
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"shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set VR128:$dst,
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(v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
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def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1,
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f128mem:$src2, i8imm:$src3),
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"shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set VR128:$dst,
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(v4f32 (shufp:$src3
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VR128:$src1, (memopv4f32 addr:$src2))))]>;
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def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
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"shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set VR128:$dst,
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(v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
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def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1,
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f128mem:$src2, i8imm:$src3),
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"shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set VR128:$dst,
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(v2f64 (shufp:$src3
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VR128:$src1, (memopv2f64 addr:$src2))))]>;
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defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
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"shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
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TB;
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defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
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"shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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memopv2f64, SSEPackedDouble>, TB, OpSize;
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let Constraints = "", isAsmParserOnly = 1 in {
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defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
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"shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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memopv4f32, SSEPackedSingle>, VEX_4V;
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defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
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"shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
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memopv2f64, SSEPackedDouble>, OpSize, VEX_4V;
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}
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let AddedComplexity = 10 in {
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let Constraints = "", isAsmParserOnly = 1 in {
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@ -10374,3 +10374,19 @@
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// CHECK: encoding: [0xc5,0xc9,0xc2,0xc8,0x07]
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vcmppd $7, %xmm0, %xmm6, %xmm1
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// CHECK: vshufps $8, %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe8,0xc6,0xd9,0x08]
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vshufps $8, %xmm1, %xmm2, %xmm3
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// CHECK: vshufps $8, -4(%ebx,%ecx,8), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe8,0xc6,0x5c,0xcb,0xfc,0x08]
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vshufps $8, -4(%ebx,%ecx,8), %xmm2, %xmm3
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// CHECK: vshufpd $8, %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xc6,0xd9,0x08]
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vshufpd $8, %xmm1, %xmm2, %xmm3
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// CHECK: vshufpd $8, -4(%ebx,%ecx,8), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xc6,0x5c,0xcb,0xfc,0x08]
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vshufpd $8, -4(%ebx,%ecx,8), %xmm2, %xmm3
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@ -438,3 +438,19 @@ pshufb CPI1_0(%rip), %xmm1
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// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xfa,0x07]
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vcmppd $7, %xmm10, %xmm12, %xmm15
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// CHECK: vshufps $8, %xmm11, %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x41,0x18,0xc6,0xeb,0x08]
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vshufps $8, %xmm11, %xmm12, %xmm13
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// CHECK: vshufps $8, -4(%rbx,%rcx,8), %xmm12, %xmm13
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// CHECK: encoding: [0xc5,0x18,0xc6,0x6c,0xcb,0xfc,0x08]
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vshufps $8, -4(%rbx,%rcx,8), %xmm12, %xmm13
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// CHECK: vshufpd $8, %xmm11, %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x41,0x19,0xc6,0xeb,0x08]
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vshufpd $8, %xmm11, %xmm12, %xmm13
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// CHECK: vshufpd $8, -4(%rbx,%rcx,8), %xmm12, %xmm13
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// CHECK: encoding: [0xc5,0x19,0xc6,0x6c,0xcb,0xfc,0x08]
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vshufpd $8, -4(%rbx,%rcx,8), %xmm12, %xmm13
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