mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-12 17:32:19 +00:00
(1) Major fix to the way unused regs. are marked and found for the FP
Single and FP double reg types (which share the same reg class).
Now all methods marking/finding unused regs consider the regType
within the reg class, and SparcFloatRegClass specializes this code.
(2) Remove machine-specific regalloc. methods that are no longer needed.
In particular, arguments and return value from a call do not need
machine-specific code for allocation.
(3) Rename TargetRegInfo::getRegType variants to avoid unintentional
overloading when an include file is omitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7334 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve
parent
8d6b9fe242
commit
7dc7de5391
@ -385,13 +385,13 @@ public:
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void colorMethodArgs(const Function *Meth, LiveRangeInfo &LRI,
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AddedInstrns *FirstAI) const;
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void colorCallArgs(MachineInstr *CallMI, LiveRangeInfo &LRI,
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AddedInstrns *CallAI, PhyRegAlloc &PRA,
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const BasicBlock *BB) const;
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void colorRetValue(MachineInstr *RetI, LiveRangeInfo& LRI,
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AddedInstrns *RetAI) const;
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// This method inserts the caller saving code for call instructions
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//
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void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
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std::vector<MachineInstr*>& instrnsAfter,
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MachineInstr *CallMI,
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const BasicBlock *BB,
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PhyRegAlloc &PRA ) const;
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// method used for printing a register for debugging purposes
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//
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@ -452,19 +452,15 @@ public:
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}
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// Get the register type for a register identified different ways.
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int getRegType(const Type* type) const;
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int getRegType(const LiveRange *LR) const;
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// Note that getRegTypeForLR(LR) != getRegTypeForDataType(LR->getType())!
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// The reg class of a LR depends both on the Value types in it and whether
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// they are CC registers or not (for example).
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int getRegTypeForDataType(const Type* type) const;
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int getRegTypeForLR(const LiveRange *LR) const;
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int getRegType(int unifiedRegNum) const;
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virtual unsigned getFramePointer() const;
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virtual unsigned getStackPointer() const;
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// This method inserts the caller saving code for call instructions
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//
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void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
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std::vector<MachineInstr*>& instrnsAfter,
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MachineInstr *MInst,
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const BasicBlock *BB, PhyRegAlloc &PRA ) const;
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};
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@ -5,6 +5,7 @@
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//===----------------------------------------------------------------------===//
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#include "SparcRegClassInfo.h"
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#include "SparcInternals.h"
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#include "llvm/Type.h"
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#include "../../CodeGen/RegAlloc/RegAllocCommon.h" // FIXME!
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@ -22,7 +23,7 @@
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//
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//-----------------------------------------------------------------------------
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void SparcIntRegClass::colorIGNode(IGNode * Node,
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std::vector<bool> &IsColorUsedArr) const
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const std::vector<bool> &IsColorUsedArr) const
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{
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LiveRange *LR = Node->getParentLR();
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@ -129,7 +130,7 @@ void SparcIntRegClass::colorIGNode(IGNode * Node,
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// depends solely on the opcode, so the name can be chosen in EmitAssembly.
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//-----------------------------------------------------------------------------
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void SparcIntCCRegClass::colorIGNode(IGNode *Node,
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std::vector<bool> &IsColorUsedArr) const
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const std::vector<bool> &IsColorUsedArr) const
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{
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if (Node->getNumOfNeighbors() > 0)
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Node->getParentLR()->markForSpill();
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@ -177,13 +178,21 @@ void SparcIntCCRegClass::colorIGNode(IGNode *Node,
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//
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//----------------------------------------------------------------------------
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void SparcFloatRegClass::colorIGNode(IGNode * Node,
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std::vector<bool> &IsColorUsedArr) const
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const std::vector<bool> &IsColorUsedArr) const
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{
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LiveRange *LR = Node->getParentLR();
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// Mark the second color for double-precision registers:
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// This is UGLY and should be merged into nearly identical code
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// in RegClass::colorIGNode that handles the first color.
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#ifndef NDEBUG
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// Check that the correct colors have been are marked for fp-doubles.
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//
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// FIXME: This is old code that is no longer needed. Temporarily converting
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// it into a big assertion just to check that the replacement logic
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// (invoking SparcFloatRegClass::markColorsUsed() directly from
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// RegClass::colorIGNode) works correctly.
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//
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// In fact, this entire function should be identical to
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// SparcIntRegClass::colorIGNode(), and perhaps can be
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// made into a general case in CodeGen/RegAlloc/RegClass.cpp.
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//
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unsigned NumNeighbors = Node->getNumOfNeighbors(); // total # of neighbors
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for(unsigned n=0; n < NumNeighbors; n++) { // for each neigh
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@ -192,17 +201,19 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,
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if (NeighLR->hasColor() &&
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NeighLR->getType() == Type::DoubleTy) {
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IsColorUsedArr[ (NeighLR->getColor()) + 1 ] = true;
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assert(IsColorUsedArr[ NeighLR->getColor() ] &&
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IsColorUsedArr[ NeighLR->getColor()+1 ]);
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} else if (NeighLR->hasSuggestedColor() &&
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NeighLR-> isSuggestedColorUsable() ) {
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// if the neighbour can use the suggested color
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IsColorUsedArr[ NeighLR->getSuggestedColor() ] = true;
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assert(IsColorUsedArr[ NeighLR->getSuggestedColor() ]);
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if (NeighLR->getType() == Type::DoubleTy)
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IsColorUsedArr[ (NeighLR->getSuggestedColor()) + 1 ] = true;
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assert(IsColorUsedArr[ NeighLR->getSuggestedColor()+1 ]);
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}
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}
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#endif
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// **NOTE: We don't check for call interferences in allocating suggested
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// color in this class since ALL registers are volatile. If this fact
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@ -275,6 +286,58 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,
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}
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}
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//-----------------------------------------------------------------------------
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// This method marks the registers used for a given register number.
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// This marks a single register for Float regs, but the R,R+1 pair
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// for double-precision registers.
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//-----------------------------------------------------------------------------
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void SparcFloatRegClass::markColorsUsed(unsigned RegInClass,
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int UserRegType,
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int RegTypeWanted,
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std::vector<bool> &IsColorUsedArr) const
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{
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if (UserRegType == UltraSparcRegInfo::FPDoubleRegType ||
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RegTypeWanted == UltraSparcRegInfo::FPDoubleRegType) {
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// This register is used as or is needed as a double-precision reg.
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// We need to mark the [even,odd] pair corresponding to this reg.
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// Get the even numbered register corresponding to this reg.
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unsigned EvenRegInClass = RegInClass & ~1u;
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assert(EvenRegInClass+1 < NumOfAllRegs &&
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EvenRegInClass+1 < IsColorUsedArr.size());
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IsColorUsedArr[EvenRegInClass] = true;
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IsColorUsedArr[EvenRegInClass+1] = true;
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}
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else {
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assert(RegInClass < NumOfAllRegs && RegInClass < IsColorUsedArr.size());
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assert(UserRegType == RegTypeWanted
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&& "Something other than FP single/double types share a reg class?");
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IsColorUsedArr[RegInClass] = true;
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}
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}
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// This method finds unused registers of the specified register type,
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// using the given "used" flag array IsColorUsedArr. It checks a single
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// entry in the array directly for float regs, and checks the pair [R,R+1]
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// for double-precision registers
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// It returns -1 if no unused color is found.
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//
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int SparcFloatRegClass::findUnusedColor(int RegTypeWanted,
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const std::vector<bool> &IsColorUsedArr) const
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{
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if (RegTypeWanted == UltraSparcRegInfo::FPDoubleRegType) {
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unsigned NC = 2 * this->getNumOfAvailRegs();
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assert(IsColorUsedArr.size() == NC && "Invalid colors-used array");
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for (unsigned c = 0; c < NC; c+=2)
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if (!IsColorUsedArr[c]) {
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assert(!IsColorUsedArr[c+1] && "Incorrect used regs for FP double!");
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return c;
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}
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return -1;
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}
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else
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return TargetRegClassInfo::findUnusedColor(RegTypeWanted, IsColorUsedArr);
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}
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//-----------------------------------------------------------------------------
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// Helper method for coloring a node of Float Reg class.
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@ -285,22 +348,24 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,
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int SparcFloatRegClass::findFloatColor(const LiveRange *LR,
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unsigned Start,
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unsigned End,
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std::vector<bool> &IsColorUsedArr) const
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const std::vector<bool> &IsColorUsedArr) const
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{
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bool ColorFound = false;
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unsigned c;
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if (LR->getType() == Type::DoubleTy) {
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// find first unused color for a double
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for (c=Start; c < End ; c+= 2)
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if (!IsColorUsedArr[c] && !IsColorUsedArr[c+1])
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assert(Start % 2 == 0 && "Odd register number could be used for double!");
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for (unsigned c=Start; c < End ; c+= 2)
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if (!IsColorUsedArr[c]) {
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assert(!IsColorUsedArr[c+1] &&
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"Incorrect marking of used regs for Sparc FP double!");
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return c;
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}
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} else {
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// find first unused color for a single
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for (c = Start; c < End; c++)
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for (unsigned c = Start; c < End; c++)
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if (!IsColorUsedArr[c])
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return c;
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}
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return -1;
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}
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@ -19,7 +19,8 @@ struct SparcIntRegClass : public TargetRegClassInfo {
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SparcIntRegClass(unsigned ID)
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: TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { }
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void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
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void colorIGNode(IGNode *Node,
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const std::vector<bool> &IsColorUsedArr) const;
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inline bool isRegVolatile(int Reg) const {
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return (Reg < (int)StartOfNonVolatileRegs);
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@ -81,12 +82,32 @@ struct SparcIntRegClass : public TargetRegClassInfo {
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class SparcFloatRegClass : public TargetRegClassInfo {
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int findFloatColor(const LiveRange *LR, unsigned Start,
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unsigned End, std::vector<bool> &IsColorUsedArr) const;
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unsigned End,
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const std::vector<bool> &IsColorUsedArr) const;
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public:
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SparcFloatRegClass(unsigned ID)
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: TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
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void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
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// This method marks the registers used for a given register number.
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// This marks a single register for Float regs, but the R,R+1 pair
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// for double-precision registers.
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//
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virtual void markColorsUsed(unsigned RegInClass,
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int UserRegType,
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int RegTypeWanted,
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std::vector<bool> &IsColorUsedArr) const;
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// This method finds unused registers of the specified register type,
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// using the given "used" flag array IsColorUsedArr. It checks a single
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// entry in the array directly for float regs, and checks the pair [R,R+1]
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// for double-precision registers
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// It returns -1 if no unused color is found.
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//
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virtual int findUnusedColor(int RegTypeWanted,
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const std::vector<bool> &IsColorUsedArr) const;
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void colorIGNode(IGNode *Node,
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const std::vector<bool> &IsColorUsedArr) const;
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// according to Sparc 64 ABI, all %fp regs are volatile
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inline bool isRegVolatile(int Reg) const { return true; }
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@ -129,7 +150,8 @@ struct SparcIntCCRegClass : public TargetRegClassInfo {
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SparcIntCCRegClass(unsigned ID)
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: TargetRegClassInfo(ID, 1, 3) { }
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void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
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void colorIGNode(IGNode *Node,
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const std::vector<bool> &IsColorUsedArr) const;
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// according to Sparc 64 ABI, %ccr is volatile
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//
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@ -143,8 +165,6 @@ struct SparcIntCCRegClass : public TargetRegClassInfo {
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};
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//-----------------------------------------------------------------------------
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// Float CC Register Class
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// Only 4 Float CC registers are available for allocation.
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@ -154,7 +174,8 @@ struct SparcFloatCCRegClass : public TargetRegClassInfo {
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SparcFloatCCRegClass(unsigned ID)
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: TargetRegClassInfo(ID, 4, 5) { }
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void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
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void colorIGNode(IGNode *Node,
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const std::vector<bool> &IsColorUsedArr) const {
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for(unsigned c = 0; c != 4; ++c)
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if (!IsColorUsedArr[c]) { // find unused color
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Node->setColor(c);
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@ -184,7 +205,8 @@ struct SparcSpecialRegClass : public TargetRegClassInfo {
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SparcSpecialRegClass(unsigned ID)
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: TargetRegClassInfo(ID, 0, 1) { }
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void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
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void colorIGNode(IGNode *Node,
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const std::vector<bool> &IsColorUsedArr) const {
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assert(0 && "SparcSpecialRegClass should never be used for allocation");
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}
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@ -229,12 +229,12 @@ int UltraSparcRegInfo::getRegTypeForClassAndType(unsigned regClassID,
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}
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}
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int UltraSparcRegInfo::getRegType(const Type* type) const
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int UltraSparcRegInfo::getRegTypeForDataType(const Type* type) const
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{
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return getRegTypeForClassAndType(getRegClassIDOfType(type), type);
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}
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int UltraSparcRegInfo::getRegType(const LiveRange *LR) const
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int UltraSparcRegInfo::getRegTypeForLR(const LiveRange *LR) const
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{
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return getRegTypeForClassAndType(LR->getRegClassID(), LR->getType());
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}
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@ -355,27 +355,26 @@ UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
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void UltraSparcRegInfo::suggestRegs4MethodArgs(const Function *Meth,
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LiveRangeInfo& LRI) const
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{
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// check if this is a varArgs function. needed for choosing regs.
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// Check if this is a varArgs function. needed for choosing regs.
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bool isVarArgs = isVarArgsFunction(Meth->getType());
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// for each argument. count INT and FP arguments separately.
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unsigned argNo=0, intArgNo=0, fpArgNo=0;
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// Count the arguments, *ignoring* whether they are int or FP args.
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// Use this common arg numbering to pick the right int or fp register.
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unsigned argNo=0;
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for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
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I != E; ++I, ++argNo) {
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// get the LR of arg
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LiveRange *LR = LRI.getLiveRangeForValue(I);
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assert(LR && "No live range found for method arg");
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unsigned regType = getRegType(LR);
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unsigned regClassIDOfArgReg = BadRegClass; // reg class of chosen reg (unused)
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unsigned regType = getRegTypeForLR(LR);
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unsigned regClassIDOfArgReg = BadRegClass; // for chosen reg (unused)
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int regNum = (regType == IntRegType)
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? regNumForIntArg(/*inCallee*/ true, isVarArgs,
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argNo, regClassIDOfArgReg)
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: regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
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argNo, regClassIDOfArgReg);
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? regNumForIntArg(/*inCallee*/ true, isVarArgs, argNo, regClassIDOfArgReg)
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: regNumForFPArg(regType, /*inCallee*/ true, isVarArgs, argNo,
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regClassIDOfArgReg);
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if(regNum != getInvalidRegNum())
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if (regNum != getInvalidRegNum())
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LR->setSuggestedColor(regNum);
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}
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}
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@ -403,7 +402,7 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
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LiveRange *LR = LRI.getLiveRangeForValue(I);
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assert( LR && "No live range found for method arg");
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unsigned regType = getRegType(LR);
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unsigned regType = getRegTypeForLR(LR);
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unsigned RegClassID = LR->getRegClassID();
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// Find whether this argument is coming in a register (if not, on stack)
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@ -601,7 +600,7 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
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if (!LR)
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continue; // no live ranges for constants and labels
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unsigned regType = getRegType(LR);
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unsigned regType = getRegTypeForLR(LR);
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unsigned regClassIDOfArgReg = BadRegClass; // chosen reg class (unused)
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// Choose a register for this arg depending on whether it is
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@ -622,242 +621,6 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
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}
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//---------------------------------------------------------------------------
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// Helper method for UltraSparcRegInfo::colorCallArgs().
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//---------------------------------------------------------------------------
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void
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UltraSparcRegInfo::InitializeOutgoingArg(MachineInstr* CallMI,
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AddedInstrns *CallAI,
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PhyRegAlloc &PRA, LiveRange* LR,
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unsigned regType, unsigned RegClassID,
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int UniArgRegOrNone, unsigned argNo,
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std::vector<MachineInstr*> &AddedInstrnsBefore)
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const
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{
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assert(0 && "Should never get here because we are now using precopying!");
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MachineInstr *AdMI;
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bool isArgInReg = false;
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unsigned UniArgReg = BadRegClass; // unused unless initialized below
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if (UniArgRegOrNone != getInvalidRegNum())
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{
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isArgInReg = true;
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UniArgReg = (unsigned) UniArgRegOrNone;
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}
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if (! LR->isMarkedForSpill()) {
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unsigned UniLRReg = getUnifiedRegNum(RegClassID, LR->getColor());
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// if LR received the correct color, nothing to do
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if( isArgInReg && UniArgReg == UniLRReg )
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return;
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// The LR is allocated to a register UniLRReg and must be copied
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// to UniArgReg or to the stack slot.
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//
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if( isArgInReg ) {
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// Copy UniLRReg to UniArgReg
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cpReg2RegMI(AddedInstrnsBefore, UniLRReg, UniArgReg, regType);
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}
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else {
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// Copy UniLRReg to the stack to pass the arg on stack.
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const TargetFrameInfo& frameInfo = target.getFrameInfo();
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int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo);
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cpReg2MemMI(CallAI->InstrnsBefore,
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UniLRReg, getStackPointer(), argOffset, regType);
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}
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|
||||
} else { // LR is not colored (i.e., spilled)
|
||||
|
||||
if( isArgInReg ) {
|
||||
// Insert a load instruction to load the LR to UniArgReg
|
||||
cpMem2RegMI(AddedInstrnsBefore, getFramePointer(),
|
||||
LR->getSpillOffFromFP(), UniArgReg, regType);
|
||||
// Now add the instruction
|
||||
}
|
||||
|
||||
else {
|
||||
// Now, we have to pass the arg on stack. Since LR also did NOT
|
||||
// receive a register we have to move an argument in memory to
|
||||
// outgoing parameter on stack.
|
||||
// Use TReg to load and store the value.
|
||||
// Use TmpOff to save TReg, since that may have a live value.
|
||||
//
|
||||
int TReg = PRA.getUniRegNotUsedByThisInst(LR->getRegClass(), CallMI);
|
||||
int TmpOff = PRA.MF.getInfo()->
|
||||
pushTempValue(getSpilledRegSize(getRegType(LR)));
|
||||
const TargetFrameInfo& frameInfo = target.getFrameInfo();
|
||||
int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo);
|
||||
|
||||
MachineInstr *Ad1, *Ad2, *Ad3, *Ad4;
|
||||
|
||||
// Sequence:
|
||||
// (1) Save TReg on stack
|
||||
// (2) Load LR value into TReg from stack pos of LR
|
||||
// (3) Store Treg on outgoing Arg pos on stack
|
||||
// (4) Load the old value of TReg from stack to TReg (restore it)
|
||||
//
|
||||
// OPTIMIZE THIS:
|
||||
// When reverse pointers in MahineInstr are introduced:
|
||||
// Call PRA.getUnusedRegAtMI(....) to get an unused reg. Step 1 is
|
||||
// needed only if this fails. Currently, we cannot call the
|
||||
// above method since we cannot find LVSetBefore without the BB
|
||||
//
|
||||
// NOTE: We directly add to CallAI->InstrnsBefore instead of adding to
|
||||
// AddedInstrnsBefore since these instructions must not be reordered.
|
||||
cpReg2MemMI(CallAI->InstrnsBefore,
|
||||
TReg, getFramePointer(), TmpOff, regType);
|
||||
cpMem2RegMI(CallAI->InstrnsBefore,
|
||||
getFramePointer(), LR->getSpillOffFromFP(), TReg, regType);
|
||||
cpReg2MemMI(CallAI->InstrnsBefore,
|
||||
TReg, getStackPointer(), argOffset, regType);
|
||||
cpMem2RegMI(CallAI->InstrnsBefore,
|
||||
getFramePointer(), TmpOff, TReg, regType);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// After graph coloring, we have call this method to see whehter the return
|
||||
// value and the call args received the correct colors. If not, we have
|
||||
// to instert copy instructions.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI,
|
||||
LiveRangeInfo &LRI,
|
||||
AddedInstrns *CallAI,
|
||||
PhyRegAlloc &PRA,
|
||||
const BasicBlock *BB) const {
|
||||
|
||||
assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
|
||||
|
||||
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
|
||||
|
||||
// First color the return value of the call.
|
||||
// If there is a LR for the return value, it means this
|
||||
// method returns a value
|
||||
|
||||
MachineInstr *AdMI;
|
||||
|
||||
const Value *RetVal = argDesc->getReturnValue();
|
||||
|
||||
if (RetVal) {
|
||||
LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
|
||||
assert(RetValLR && "ERROR: No LR for non-void return value");
|
||||
|
||||
// Mark the return value register as used by this instruction
|
||||
unsigned RegClassID = RetValLR->getRegClassID();
|
||||
unsigned CorrectCol = (RegClassID == IntRegClassID
|
||||
? (unsigned) SparcIntRegClass::o0
|
||||
: (unsigned) SparcFloatRegClass::f0);
|
||||
|
||||
CallMI->insertUsedReg(getUnifiedRegNum(RegClassID, CorrectCol));
|
||||
|
||||
} // if there a return value
|
||||
|
||||
|
||||
//-------------------------------------------
|
||||
// Now color all args of the call instruction
|
||||
//-------------------------------------------
|
||||
|
||||
std::vector<MachineInstr*> AddedInstrnsBefore;
|
||||
|
||||
unsigned NumOfCallArgs = argDesc->getNumArgs();
|
||||
|
||||
for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
|
||||
i < NumOfCallArgs; ++i, ++argNo) {
|
||||
|
||||
const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
|
||||
unsigned regType = getRegType(CallArg->getType());
|
||||
|
||||
// Find whether this argument is coming in a register (if not, on stack)
|
||||
// Also find the correct register the argument must use (UniArgReg)
|
||||
//
|
||||
bool isArgInReg = false;
|
||||
int UniArgReg = getInvalidRegNum(); // reg that LR MUST be colored with
|
||||
unsigned regClassIDOfArgReg = BadRegClass; // reg class of chosen reg
|
||||
|
||||
// Find the register that must be used for this arg, depending on
|
||||
// whether it is an INT or FP value. Here we ignore whether or not it
|
||||
// is a varargs calls, because FP arguments will be explicitly copied
|
||||
// to an integer Value and handled under (argCopy != NULL) below.
|
||||
//
|
||||
int regNum = (regType == IntRegType)
|
||||
? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
|
||||
argNo, regClassIDOfArgReg)
|
||||
: regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
|
||||
argNo, regClassIDOfArgReg);
|
||||
|
||||
if (regNum != getInvalidRegNum()) {
|
||||
isArgInReg = true;
|
||||
UniArgReg = getUnifiedRegNum(regClassIDOfArgReg, regNum);
|
||||
CallMI->insertUsedReg(UniArgReg); // mark the reg as used
|
||||
}
|
||||
|
||||
// Repeat for the second copy of the argument, which would be
|
||||
// an FP argument being passed to a function with no prototype.
|
||||
// It may either be passed as a copy in an integer register
|
||||
// (in argCopy), or on the stack (useStackSlot).
|
||||
int argCopyReg = argDesc->getArgInfo(i).getArgCopy();
|
||||
if (argCopyReg != TargetRegInfo::getInvalidRegNum())
|
||||
{
|
||||
CallMI->insertUsedReg(argCopyReg); // mark the reg as used
|
||||
}
|
||||
} // for each parameter in call instruction
|
||||
|
||||
// If we added any instruction before the call instruction, verify
|
||||
// that they are in the proper order and if not, reorder them
|
||||
//
|
||||
std::vector<MachineInstr*> ReorderedVec;
|
||||
if (!AddedInstrnsBefore.empty()) {
|
||||
|
||||
if (DEBUG_RA) {
|
||||
std::cerr << "\nCalling reorder with instrns: \n";
|
||||
for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
|
||||
std::cerr << *(AddedInstrnsBefore[i]);
|
||||
}
|
||||
|
||||
OrderAddedInstrns(AddedInstrnsBefore, ReorderedVec, PRA);
|
||||
assert(ReorderedVec.size() >= AddedInstrnsBefore.size()
|
||||
&& "Dropped some instructions when reordering!");
|
||||
|
||||
if (DEBUG_RA) {
|
||||
std::cerr << "\nAfter reordering instrns: \n";
|
||||
for(unsigned i = 0; i < ReorderedVec.size(); i++)
|
||||
std::cerr << *ReorderedVec[i];
|
||||
}
|
||||
}
|
||||
|
||||
// Now insert caller saving code for this call instruction
|
||||
//
|
||||
insertCallerSavingCode(CallAI->InstrnsBefore, CallAI->InstrnsAfter,
|
||||
CallMI, BB, PRA);
|
||||
|
||||
// Then insert the final reordered code for the call arguments.
|
||||
//
|
||||
for(unsigned i=0; i < ReorderedVec.size(); i++)
|
||||
CallAI->InstrnsBefore.push_back( ReorderedVec[i] );
|
||||
|
||||
#ifndef NDEBUG
|
||||
// Temporary sanity checking code to detect whether the same machine
|
||||
// instruction is ever inserted twice before/after a call.
|
||||
// I suspect this is happening but am not sure. --Vikram, 7/1/03.
|
||||
//
|
||||
std::set<const MachineInstr*> instrsSeen;
|
||||
for (int i = 0, N = CallAI->InstrnsBefore.size(); i < N; ++i) {
|
||||
assert(instrsSeen.find(CallAI->InstrnsBefore[i]) == instrsSeen.end() &&
|
||||
"Duplicate machine instruction in InstrnsBefore!");
|
||||
instrsSeen.insert(CallAI->InstrnsBefore[i]);
|
||||
}
|
||||
for (int i = 0, N = CallAI->InstrnsAfter.size(); i < N; ++i) {
|
||||
assert(instrsSeen.find(CallAI->InstrnsAfter[i]) == instrsSeen.end() &&
|
||||
"Duplicate machine instruction in InstrnsBefore/After!");
|
||||
instrsSeen.insert(CallAI->InstrnsAfter[i]);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// this method is called for an LLVM return instruction to identify which
|
||||
// values will be returned from this method and to suggest colors.
|
||||
@ -880,41 +643,6 @@ void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
|
||||
: (unsigned) SparcFloatRegClass::f0);
|
||||
}
|
||||
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Colors the return value of a method to %i0 or %f0, if possible. If it is
|
||||
// not possilbe to directly color the LR, insert a copy instruction to move
|
||||
// the LR to %i0 or %f0. When the LR is spilled, instead of the copy, we
|
||||
// have to put a load instruction.
|
||||
//---------------------------------------------------------------------------
|
||||
void UltraSparcRegInfo::colorRetValue(MachineInstr *RetMI,
|
||||
LiveRangeInfo &LRI,
|
||||
AddedInstrns *RetAI) const {
|
||||
|
||||
assert((target.getInstrInfo()).isReturn( RetMI->getOpCode()));
|
||||
|
||||
// To find the return value (if any), we can get the LLVM return instr.
|
||||
// from the return address register, which is the first operand
|
||||
Value* tmpI = RetMI->getOperand(0).getVRegValue();
|
||||
ReturnInst* retI=cast<ReturnInst>(cast<TmpInstruction>(tmpI)->getOperand(0));
|
||||
if (const Value *RetVal = retI->getReturnValue()) {
|
||||
|
||||
unsigned RegClassID = getRegClassIDOfType(RetVal->getType());
|
||||
unsigned regType = getRegType(RetVal->getType());
|
||||
unsigned CorrectCol = (RegClassID == IntRegClassID
|
||||
? (unsigned) SparcIntRegClass::i0
|
||||
: (unsigned) SparcFloatRegClass::f0);
|
||||
|
||||
// convert to unified number
|
||||
unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
|
||||
|
||||
// Mark the register as used by this instruction
|
||||
RetMI->insertUsedReg(UniRetReg);
|
||||
} // if there is a return value
|
||||
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Check if a specified register type needs a scratch register to be
|
||||
// copied to/from memory. If it does, the reg. type that must be used
|
||||
@ -1126,7 +854,7 @@ UltraSparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
|
||||
void
|
||||
UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest,
|
||||
std::vector<MachineInstr*>& mvec) const {
|
||||
int RegType = getRegType(Src->getType());
|
||||
int RegType = getRegTypeForDataType(Src->getType());
|
||||
MachineInstr * MI = NULL;
|
||||
|
||||
switch( RegType ) {
|
||||
@ -1251,7 +979,7 @@ UltraSparcRegInfo::insertCallerSavingCode
|
||||
|
||||
// if we haven't already pushed that register
|
||||
|
||||
unsigned RegType = getRegType(LR);
|
||||
unsigned RegType = getRegTypeForLR(LR);
|
||||
|
||||
// Now get two instructions - to push on stack and pop from stack
|
||||
// and add them to InstrnsBefore and InstrnsAfter of the
|
||||
@ -1370,240 +1098,3 @@ void UltraSparcRegInfo::printReg(const LiveRange *LR) const {
|
||||
std::cerr << "+" << getUnifiedRegName(uRegName+1);
|
||||
std::cerr << "]\n";
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// This method examines instructions inserted by RegAlloc code before a
|
||||
// machine instruction to detect invalid orders that destroy values before
|
||||
// they are used. If it detects such conditions, it reorders the instructions.
|
||||
//
|
||||
// The unordered instructions come in the UnordVec. These instructions are
|
||||
// instructions inserted by RegAlloc. All such instruction MUST have
|
||||
// their USES BEFORE THE DEFS after reordering.
|
||||
//
|
||||
// The UnordVec & OrdVec must be DISTINCT. The OrdVec must be empty when
|
||||
// this method is called.
|
||||
//
|
||||
// This method uses two vectors for efficiency in accessing
|
||||
//
|
||||
// Since instructions are inserted in RegAlloc, this assumes that the
|
||||
// first operand is the source reg and the last operand is the dest reg.
|
||||
// It also does not consider operands that are both use and def.
|
||||
//
|
||||
// All the uses are before THE def to a register
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr*> &UnordVec,
|
||||
std::vector<MachineInstr*> &OrdVec,
|
||||
PhyRegAlloc &PRA) const{
|
||||
|
||||
/*
|
||||
Problem: We can have instructions inserted by RegAlloc like
|
||||
1. add %ox %g0 %oy
|
||||
2. add %oy %g0 %oz, where z!=x or z==x
|
||||
|
||||
This is wrong since %oy used by 2 is overwritten by 1
|
||||
|
||||
Solution:
|
||||
We re-order the instructions so that the uses are before the defs
|
||||
|
||||
Algorithm:
|
||||
|
||||
do
|
||||
for each instruction 'DefInst' in the UnOrdVec
|
||||
for each instruction 'UseInst' that follows the DefInst
|
||||
if the reg defined by DefInst is used by UseInst
|
||||
mark DefInst as not movable in this iteration
|
||||
If DefInst is not marked as not-movable, move DefInst to OrdVec
|
||||
while all instructions in DefInst are moved to OrdVec
|
||||
|
||||
For moving, we call the move2OrdVec(). It checks whether there is a def
|
||||
in it for the uses in the instruction to be added to OrdVec. If there
|
||||
are no preceding defs, it just appends the instruction. If there is a
|
||||
preceding def, it puts two instructions to save the reg on stack before
|
||||
the load and puts a restore at use.
|
||||
|
||||
*/
|
||||
|
||||
bool CouldMoveAll;
|
||||
bool DebugPrint = false;
|
||||
|
||||
do {
|
||||
CouldMoveAll = true;
|
||||
std::vector<MachineInstr*>::iterator DefIt = UnordVec.begin();
|
||||
|
||||
for( ; DefIt != UnordVec.end(); ++DefIt ) {
|
||||
|
||||
// for each instruction in the UnordVec do ...
|
||||
|
||||
MachineInstr *DefInst = *DefIt;
|
||||
|
||||
if( DefInst == NULL) continue;
|
||||
|
||||
//std::cerr << "\nInst in UnordVec = " << *DefInst;
|
||||
|
||||
// last operand is the def (unless for a store which has no def reg)
|
||||
MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
|
||||
|
||||
if ((DefOp.opIsDefOnly() || DefOp.opIsDefAndUse()) &&
|
||||
DefOp.getType() == MachineOperand::MO_MachineRegister) {
|
||||
|
||||
// If the operand in DefInst is a def ...
|
||||
bool DefEqUse = false;
|
||||
|
||||
std::vector<MachineInstr*>::iterator UseIt = DefIt;
|
||||
UseIt++;
|
||||
|
||||
for( ; UseIt != UnordVec.end(); ++UseIt ) {
|
||||
|
||||
MachineInstr *UseInst = *UseIt;
|
||||
if( UseInst == NULL) continue;
|
||||
|
||||
// for each inst (UseInst) that is below the DefInst do ...
|
||||
MachineOperand& UseOp = UseInst->getOperand(0);
|
||||
|
||||
if (!UseOp.opIsDefOnly() &&
|
||||
UseOp.getType() == MachineOperand::MO_MachineRegister) {
|
||||
|
||||
// if use is a register ...
|
||||
|
||||
if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
|
||||
|
||||
// if Def and this use are the same, it means that this use
|
||||
// is destroyed by a def before it is used
|
||||
|
||||
// std::cerr << "\nCouldn't move " << *DefInst;
|
||||
|
||||
DefEqUse = true;
|
||||
CouldMoveAll = false;
|
||||
DebugPrint = true;
|
||||
break;
|
||||
} // if two registers are equal
|
||||
|
||||
} // if use is a register
|
||||
|
||||
}// for all use instructions
|
||||
|
||||
if( ! DefEqUse ) {
|
||||
|
||||
// after examining all the instructions that follow the DefInst
|
||||
// if there are no dependencies, we can move it to the OrdVec
|
||||
|
||||
// std::cerr << "Moved to Ord: " << *DefInst;
|
||||
|
||||
moveInst2OrdVec(OrdVec, DefInst, PRA);
|
||||
|
||||
//OrdVec.push_back(DefInst);
|
||||
|
||||
// mark the pos of DefInst with NULL to indicate that it is
|
||||
// empty
|
||||
*DefIt = NULL;
|
||||
}
|
||||
|
||||
} // if Def is a machine register
|
||||
|
||||
} // for all instructions in the UnordVec
|
||||
|
||||
|
||||
} while(!CouldMoveAll);
|
||||
|
||||
if (DebugPrint && DEBUG_RA) {
|
||||
std::cerr << "\nAdded instructions were reordered to:\n";
|
||||
for(unsigned i=0; i < OrdVec.size(); i++)
|
||||
std::cerr << *OrdVec[i];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr*> &OrdVec,
|
||||
MachineInstr *UnordInst,
|
||||
PhyRegAlloc &PRA) const {
|
||||
MachineOperand& UseOp = UnordInst->getOperand(0);
|
||||
|
||||
if (!UseOp.opIsDefOnly() &&
|
||||
UseOp.getType() == MachineOperand::MO_MachineRegister) {
|
||||
|
||||
// for the use of UnordInst, see whether there is a defining instr
|
||||
// before in the OrdVec
|
||||
bool DefEqUse = false;
|
||||
|
||||
std::vector<MachineInstr*>::iterator OrdIt = OrdVec.begin();
|
||||
|
||||
for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
|
||||
|
||||
MachineInstr *OrdInst = *OrdIt ;
|
||||
|
||||
MachineOperand& DefOp =
|
||||
OrdInst->getOperand(OrdInst->getNumOperands()-1);
|
||||
|
||||
if( (DefOp.opIsDefOnly() || DefOp.opIsDefAndUse()) &&
|
||||
DefOp.getType() == MachineOperand::MO_MachineRegister) {
|
||||
|
||||
//std::cerr << "\nDefining Ord Inst: " << *OrdInst;
|
||||
|
||||
if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
|
||||
|
||||
// we are here because there is a preceding def in the OrdVec
|
||||
// for the use in this intr we are going to insert. This
|
||||
// happened because the original code was like:
|
||||
// 1. add %ox %g0 %oy
|
||||
// 2. add %oy %g0 %ox
|
||||
// In Round1, we added 2 to OrdVec but 1 remained in UnordVec
|
||||
// Now we are processing %ox of 1.
|
||||
// We have to
|
||||
|
||||
int UReg = DefOp.getMachineRegNum();
|
||||
int RegType = getRegType(UReg);
|
||||
MachineInstr *AdIBef, *AdIAft;
|
||||
|
||||
int StackOff =
|
||||
PRA.MF.getInfo()->pushTempValue(getSpilledRegSize(RegType));
|
||||
|
||||
// Save the UReg (%ox) on stack before it's destroyed
|
||||
std::vector<MachineInstr*> mvec;
|
||||
cpReg2MemMI(mvec, UReg, getFramePointer(), StackOff, RegType);
|
||||
for (std::vector<MachineInstr*>::iterator MI=mvec.begin();
|
||||
MI != mvec.end(); ++MI)
|
||||
OrdIt = 1+OrdVec.insert(OrdIt, *MI);
|
||||
|
||||
// Load directly into DReg (%oy)
|
||||
MachineOperand& DOp=
|
||||
(UnordInst->getOperand(UnordInst->getNumOperands()-1));
|
||||
assert((DOp.opIsDefOnly() || DefOp.opIsDefAndUse()) &&
|
||||
"Last operand is not the def");
|
||||
const int DReg = DOp.getMachineRegNum();
|
||||
|
||||
cpMem2RegMI(OrdVec, getFramePointer(), StackOff, DReg, RegType);
|
||||
|
||||
if( DEBUG_RA ) {
|
||||
std::cerr << "\nFixed CIRCULAR references by reordering:";
|
||||
std::cerr << "\nBefore CIRCULAR Reordering:\n";
|
||||
std::cerr << *UnordInst;
|
||||
std::cerr << *OrdInst;
|
||||
|
||||
std::cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
|
||||
for(unsigned i=0; i < OrdVec.size(); i++)
|
||||
std::cerr << *(OrdVec[i]);
|
||||
}
|
||||
|
||||
// Do not copy the UseInst to OrdVec
|
||||
DefEqUse = true;
|
||||
break;
|
||||
|
||||
}// if two registers are equal
|
||||
|
||||
} // if Def is a register
|
||||
|
||||
} // for each instr in OrdVec
|
||||
|
||||
if(!DefEqUse) {
|
||||
|
||||
// We didn't find a def in the OrdVec, so just append this inst
|
||||
OrdVec.push_back( UnordInst );
|
||||
//std::cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
|
||||
}
|
||||
|
||||
}// if the operand in UnordInst is a use
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user