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Fixed load syntax in EmitAssembly

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Fixed cpReg2Mem (store) operand oreder in SparcRegInfo.cpp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@984 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ruchira Sasanka 2001-10-24 22:05:34 +00:00
parent 4a82271451
commit 7dcd61209a
2 changed files with 47 additions and 10 deletions
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39
lib/Target/SparcV9/SparcV9AsmPrinter.cpp
View File

@ -182,10 +182,47 @@ void SparcAsmPrinter::emitMachineInst(const MachineInstr *MI) {
printOperand(MI->getOperand(1));
Out << endl;
return;
default: break;
}
if( Target.getInstrInfo().isLoad(Opcode) ) { // if Load
assert(MI->getNumOperands() == 3 && "Loads must have 3 operands");
Out << "[";
printOperand(MI->getOperand(0));
const MachineOperand& ImmOp = MI->getOperand(1);
if( ImmOp.getImmedValue() >= 0)
Out << "+";
printOperand(ImmOp);
Out << "]";
Out << ", ";
printOperand(MI->getOperand(2));
Out << endl;
return;
}
if( Target.getInstrInfo().isStore(Opcode) ) { // if Store
assert(MI->getNumOperands() == 3 && "Stores must have 3 operands");
printOperand(MI->getOperand(0));
Out << ", ";
Out << "[";
printOperand(MI->getOperand(1));
const MachineOperand& ImmOp = MI->getOperand(2);
if( ImmOp.getImmedValue() >= 0)
Out << "+";
printOperand(ImmOp);
Out << "]";
Out << endl;
return;
}
unsigned Mask = getOperandMask(Opcode);
bool NeedComma = false;

18
lib/Target/SparcV9/SparcV9RegInfo.cpp
View File

@ -775,8 +775,8 @@ MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg,
//---------------------------------------------------------------------------
// Copy from a register to memory. Register number must be the unified
// register number
// Copy from a register to memory (i.e., Store). Register number must
// be the unified register number
//---------------------------------------------------------------------------
@ -794,24 +794,24 @@ MachineInstr * UltraSparcRegInfo::cpReg2MemMI(const unsigned SrcReg,
case IntCCRegType:
case FloatCCRegType:
MI = new MachineInstr(STX, 3);
MI->SetMachineOperand(0, DestPtrReg, false);
MI->SetMachineOperand(1, SrcReg, false);
MI->SetMachineOperand(0, SrcReg, false);
MI->SetMachineOperand(1, DestPtrReg, false);
MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset, false);
break;
case FPSingleRegType:
MI = new MachineInstr(ST, 3);
MI->SetMachineOperand(0, DestPtrReg, false);
MI->SetMachineOperand(1, SrcReg, false);
MI->SetMachineOperand(0, SrcReg, false);
MI->SetMachineOperand(1, DestPtrReg, false);
MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset, false);
break;
case FPDoubleRegType:
MI = new MachineInstr(STD, 3);
MI->SetMachineOperand(0, DestPtrReg, false);
MI->SetMachineOperand(1, SrcReg, false);
MI->SetMachineOperand(0, SrcReg, false);
MI->SetMachineOperand(1, DestPtrReg, false);
MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset, false);
break;
@ -825,7 +825,7 @@ MachineInstr * UltraSparcRegInfo::cpReg2MemMI(const unsigned SrcReg,
//---------------------------------------------------------------------------
// Copy from memory to a reg. Register number must be the unified
// Copy from memory to a reg (i.e., Load) Register number must be the unified
// register number
//---------------------------------------------------------------------------