mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
propagate IR-level fast-math-flags to DAG nodes, disabled by default
This is an updated version of the patch that was checked in at: http://reviews.llvm.org/rL237046 but subsequently reverted because it exposed a bug in the DAG Combiner: http://reviews.llvm.org/D9893 This time, there's an enablement flag ("EnableFMFInDAG") around the code in SelectionDAGBuilder where we copy the set of FP optimization flags from IR instructions to DAG nodes. So, in theory, there should be no functional change from this patch as-is, but it will allow testing with the added functionality to proceed via "-enable-fmf-dag" passed to llc. This patch adds the minimum plumbing necessary to use IR-level fast-math-flags (FMF) in the backend without actually using them for anything yet. This is a follow-on to: http://reviews.llvm.org/rL235997 Differential Revision: http://reviews.llvm.org/D10403 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239828 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -669,7 +669,7 @@ public:
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SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT);
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SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT);
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SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N);
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SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N);
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SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
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SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
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bool nuw = false, bool nsw = false, bool exact = false);
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const SDNodeFlags *Flags = nullptr);
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SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
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SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
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SDValue N3);
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SDValue N3);
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SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
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SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
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@ -990,8 +990,7 @@ public:
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/// Get the specified node if it's already available, or else return NULL.
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/// Get the specified node if it's already available, or else return NULL.
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SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTs, ArrayRef<SDValue> Ops,
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SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTs, ArrayRef<SDValue> Ops,
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bool nuw = false, bool nsw = false,
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const SDNodeFlags *Flags = nullptr);
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bool exact = false);
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/// Creates a SDDbgValue node.
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/// Creates a SDDbgValue node.
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SDDbgValue *getDbgValue(MDNode *Var, MDNode *Expr, SDNode *N, unsigned R,
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SDDbgValue *getDbgValue(MDNode *Var, MDNode *Expr, SDNode *N, unsigned R,
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@ -1253,8 +1252,8 @@ private:
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void allnodes_clear();
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void allnodes_clear();
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BinarySDNode *GetBinarySDNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
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BinarySDNode *GetBinarySDNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
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SDValue N1, SDValue N2, bool nuw, bool nsw,
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SDValue N1, SDValue N2,
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bool exact);
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const SDNodeFlags *Flags = nullptr);
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/// Look up the node specified by ID in CSEMap. If it exists, return it. If
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/// Look up the node specified by ID in CSEMap. If it exists, return it. If
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/// not, return the insertion token that will make insertion faster. This
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/// not, return the insertion token that will make insertion faster. This
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@ -1017,6 +1017,11 @@ static bool isBinOpWithFlags(unsigned Opcode) {
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case ISD::ADD:
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case ISD::ADD:
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case ISD::SUB:
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case ISD::SUB:
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case ISD::SHL:
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case ISD::SHL:
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case ISD::FADD:
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case ISD::FDIV:
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case ISD::FMUL:
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case ISD::FREM:
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case ISD::FSUB:
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return true;
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return true;
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default:
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default:
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return false;
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return false;
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@ -1029,8 +1034,8 @@ class BinaryWithFlagsSDNode : public BinarySDNode {
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public:
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public:
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SDNodeFlags Flags;
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SDNodeFlags Flags;
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BinaryWithFlagsSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,
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BinaryWithFlagsSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,
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SDValue X, SDValue Y)
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SDValue X, SDValue Y, const SDNodeFlags &NodeFlags)
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: BinarySDNode(Opc, Order, dl, VTs, X, Y), Flags() {}
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: BinarySDNode(Opc, Order, dl, VTs, X, Y), Flags(NodeFlags) {}
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static bool classof(const SDNode *N) {
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static bool classof(const SDNode *N) {
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return isBinOpWithFlags(N->getOpcode());
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return isBinOpWithFlags(N->getOpcode());
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}
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}
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@ -1463,12 +1463,9 @@ SDValue DAGCombiner::combine(SDNode *N) {
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if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
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if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
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SDValue Ops[] = {N1, N0};
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SDValue Ops[] = {N1, N0};
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SDNode *CSENode;
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SDNode *CSENode;
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if (const BinaryWithFlagsSDNode *BinNode =
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if (const auto *BinNode = dyn_cast<BinaryWithFlagsSDNode>(N)) {
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dyn_cast<BinaryWithFlagsSDNode>(N)) {
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CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
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CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
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BinNode->Flags.hasNoUnsignedWrap(),
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&BinNode->Flags);
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BinNode->Flags.hasNoSignedWrap(),
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BinNode->Flags.hasExact());
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} else {
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} else {
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CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops);
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CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops);
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}
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}
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@ -400,19 +400,24 @@ static void AddNodeIDOperands(FoldingSetNodeID &ID,
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ID.AddInteger(Op.getResNo());
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ID.AddInteger(Op.getResNo());
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}
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}
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}
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}
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/// Add logical or fast math flag values to FoldingSetNodeID value.
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static void AddNodeIDFlags(FoldingSetNodeID &ID, unsigned Opcode,
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const SDNodeFlags *Flags) {
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if (!Flags || !isBinOpWithFlags(Opcode))
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return;
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static void AddBinaryNodeIDCustom(FoldingSetNodeID &ID, bool nuw, bool nsw,
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unsigned RawFlags = Flags->getRawFlags();
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bool exact) {
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// If no flags are set, do not alter the ID. We must match the ID of nodes
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ID.AddBoolean(nuw);
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// that were created without explicitly specifying flags. This also saves time
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ID.AddBoolean(nsw);
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// and allows a gradual increase in API usage of the optional optimization
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ID.AddBoolean(exact);
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// flags.
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if (RawFlags != 0)
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ID.AddInteger(RawFlags);
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}
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}
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/// AddBinaryNodeIDCustom - Add BinarySDNodes special infos
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static void AddNodeIDFlags(FoldingSetNodeID &ID, const SDNode *N) {
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static void AddBinaryNodeIDCustom(FoldingSetNodeID &ID, unsigned Opcode,
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if (auto *Node = dyn_cast<BinaryWithFlagsSDNode>(N))
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bool nuw, bool nsw, bool exact) {
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AddNodeIDFlags(ID, Node->getOpcode(), &Node->Flags);
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if (isBinOpWithFlags(Opcode))
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AddBinaryNodeIDCustom(ID, nuw, nsw, exact);
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}
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}
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static void AddNodeIDNode(FoldingSetNodeID &ID, unsigned short OpC,
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static void AddNodeIDNode(FoldingSetNodeID &ID, unsigned short OpC,
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@ -507,20 +512,6 @@ static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
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ID.AddInteger(ST->getPointerInfo().getAddrSpace());
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ID.AddInteger(ST->getPointerInfo().getAddrSpace());
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break;
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break;
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}
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}
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::SRA:
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case ISD::SRL:
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case ISD::MUL:
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case ISD::ADD:
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case ISD::SUB:
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case ISD::SHL: {
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const BinaryWithFlagsSDNode *BinNode = cast<BinaryWithFlagsSDNode>(N);
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AddBinaryNodeIDCustom(
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ID, N->getOpcode(), BinNode->Flags.hasNoUnsignedWrap(),
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BinNode->Flags.hasNoSignedWrap(), BinNode->Flags.hasExact());
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break;
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}
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case ISD::ATOMIC_CMP_SWAP:
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case ISD::ATOMIC_CMP_SWAP:
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case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
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case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
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case ISD::ATOMIC_SWAP:
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case ISD::ATOMIC_SWAP:
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@ -564,6 +555,8 @@ static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
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}
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}
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} // end switch (N->getOpcode())
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} // end switch (N->getOpcode())
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AddNodeIDFlags(ID, N);
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// Target specific memory nodes could also have address spaces to check.
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// Target specific memory nodes could also have address spaces to check.
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if (N->isTargetMemoryOpcode())
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if (N->isTargetMemoryOpcode())
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ID.AddInteger(cast<MemSDNode>(N)->getPointerInfo().getAddrSpace());
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ID.AddInteger(cast<MemSDNode>(N)->getPointerInfo().getAddrSpace());
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@ -960,14 +953,16 @@ void SelectionDAG::allnodes_clear() {
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BinarySDNode *SelectionDAG::GetBinarySDNode(unsigned Opcode, SDLoc DL,
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BinarySDNode *SelectionDAG::GetBinarySDNode(unsigned Opcode, SDLoc DL,
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SDVTList VTs, SDValue N1,
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SDVTList VTs, SDValue N1,
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SDValue N2, bool nuw, bool nsw,
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SDValue N2,
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bool exact) {
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const SDNodeFlags *Flags) {
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if (isBinOpWithFlags(Opcode)) {
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if (isBinOpWithFlags(Opcode)) {
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// If no flags were passed in, use a default flags object.
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SDNodeFlags F;
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if (Flags == nullptr)
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Flags = &F;
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BinaryWithFlagsSDNode *FN = new (NodeAllocator) BinaryWithFlagsSDNode(
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BinaryWithFlagsSDNode *FN = new (NodeAllocator) BinaryWithFlagsSDNode(
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Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, N1, N2);
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Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, N1, N2, *Flags);
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FN->Flags.setNoUnsignedWrap(nuw);
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FN->Flags.setNoSignedWrap(nsw);
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FN->Flags.setExact(exact);
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return FN;
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return FN;
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}
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}
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@ -3269,7 +3264,7 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, SDLoc DL, EVT VT,
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}
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}
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SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
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SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
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SDValue N2, bool nuw, bool nsw, bool exact) {
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SDValue N2, const SDNodeFlags *Flags) {
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
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switch (Opcode) {
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switch (Opcode) {
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@ -3756,22 +3751,20 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
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// Memoize this node if possible.
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// Memoize this node if possible.
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BinarySDNode *N;
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BinarySDNode *N;
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SDVTList VTs = getVTList(VT);
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SDVTList VTs = getVTList(VT);
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const bool BinOpHasFlags = isBinOpWithFlags(Opcode);
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if (VT != MVT::Glue) {
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if (VT != MVT::Glue) {
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SDValue Ops[] = {N1, N2};
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SDValue Ops[] = {N1, N2};
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FoldingSetNodeID ID;
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FoldingSetNodeID ID;
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AddNodeIDNode(ID, Opcode, VTs, Ops);
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AddNodeIDNode(ID, Opcode, VTs, Ops);
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if (BinOpHasFlags)
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AddNodeIDFlags(ID, Opcode, Flags);
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AddBinaryNodeIDCustom(ID, Opcode, nuw, nsw, exact);
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void *IP = nullptr;
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void *IP = nullptr;
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if (SDNode *E = FindNodeOrInsertPos(ID, DL.getDebugLoc(), IP))
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if (SDNode *E = FindNodeOrInsertPos(ID, DL.getDebugLoc(), IP))
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return SDValue(E, 0);
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return SDValue(E, 0);
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N = GetBinarySDNode(Opcode, DL, VTs, N1, N2, nuw, nsw, exact);
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N = GetBinarySDNode(Opcode, DL, VTs, N1, N2, Flags);
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CSEMap.InsertNode(N, IP);
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CSEMap.InsertNode(N, IP);
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} else {
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} else {
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N = GetBinarySDNode(Opcode, DL, VTs, N1, N2, nuw, nsw, exact);
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N = GetBinarySDNode(Opcode, DL, VTs, N1, N2, Flags);
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}
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}
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InsertNode(N);
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InsertNode(N);
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@ -6075,13 +6068,12 @@ SelectionDAG::getTargetInsertSubreg(int SRIdx, SDLoc DL, EVT VT,
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/// getNodeIfExists - Get the specified node if it's already available, or
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/// getNodeIfExists - Get the specified node if it's already available, or
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/// else return NULL.
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/// else return NULL.
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SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
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SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
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ArrayRef<SDValue> Ops, bool nuw, bool nsw,
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ArrayRef<SDValue> Ops,
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bool exact) {
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const SDNodeFlags *Flags) {
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if (VTList.VTs[VTList.NumVTs - 1] != MVT::Glue) {
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if (VTList.VTs[VTList.NumVTs - 1] != MVT::Glue) {
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FoldingSetNodeID ID;
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FoldingSetNodeID ID;
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AddNodeIDNode(ID, Opcode, VTList, Ops);
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AddNodeIDNode(ID, Opcode, VTList, Ops);
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if (isBinOpWithFlags(Opcode))
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AddNodeIDFlags(ID, Opcode, Flags);
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AddBinaryNodeIDCustom(ID, nuw, nsw, exact);
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void *IP = nullptr;
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void *IP = nullptr;
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if (SDNode *E = FindNodeOrInsertPos(ID, DebugLoc(), IP))
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if (SDNode *E = FindNodeOrInsertPos(ID, DebugLoc(), IP))
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return E;
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return E;
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@ -78,6 +78,10 @@ LimitFPPrecision("limit-float-precision",
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cl::location(LimitFloatPrecision),
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cl::location(LimitFloatPrecision),
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cl::init(0));
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cl::init(0));
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static cl::opt<bool>
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EnableFMFInDAG("enable-fmf-dag", cl::init(false), cl::Hidden,
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cl::desc("Enable fast-math-flags for DAG nodes"));
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// Limit the width of DAG chains. This is important in general to prevent
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// Limit the width of DAG chains. This is important in general to prevent
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// prevent DAG-based analysis from blowing up. For example, alias analysis and
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// prevent DAG-based analysis from blowing up. For example, alias analysis and
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// load clustering may not complete in reasonable time. It is difficult to
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// load clustering may not complete in reasonable time. It is difficult to
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@ -2148,6 +2152,8 @@ void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
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bool nuw = false;
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bool nuw = false;
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bool nsw = false;
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bool nsw = false;
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bool exact = false;
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bool exact = false;
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FastMathFlags FMF;
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if (const OverflowingBinaryOperator *OFBinOp =
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if (const OverflowingBinaryOperator *OFBinOp =
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dyn_cast<const OverflowingBinaryOperator>(&I)) {
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dyn_cast<const OverflowingBinaryOperator>(&I)) {
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nuw = OFBinOp->hasNoUnsignedWrap();
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nuw = OFBinOp->hasNoUnsignedWrap();
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@ -2156,9 +2162,22 @@ void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
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if (const PossiblyExactOperator *ExactOp =
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if (const PossiblyExactOperator *ExactOp =
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dyn_cast<const PossiblyExactOperator>(&I))
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dyn_cast<const PossiblyExactOperator>(&I))
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exact = ExactOp->isExact();
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exact = ExactOp->isExact();
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if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
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FMF = FPOp->getFastMathFlags();
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SDNodeFlags Flags;
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Flags.setExact(exact);
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Flags.setNoSignedWrap(nsw);
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Flags.setNoUnsignedWrap(nuw);
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if (EnableFMFInDAG) {
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Flags.setAllowReciprocal(FMF.allowReciprocal());
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Flags.setNoInfs(FMF.noInfs());
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Flags.setNoNaNs(FMF.noNaNs());
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Flags.setNoSignedZeros(FMF.noSignedZeros());
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Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
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}
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SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
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SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
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Op1, Op2, nuw, nsw, exact);
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Op1, Op2, &Flags);
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setValue(&I, BinNodeValue);
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setValue(&I, BinNodeValue);
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}
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}
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@ -2206,9 +2225,12 @@ void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
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dyn_cast<const PossiblyExactOperator>(&I))
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dyn_cast<const PossiblyExactOperator>(&I))
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exact = ExactOp->isExact();
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exact = ExactOp->isExact();
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}
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}
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SDNodeFlags Flags;
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Flags.setExact(exact);
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Flags.setNoSignedWrap(nsw);
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Flags.setNoUnsignedWrap(nuw);
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SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
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SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
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nuw, nsw, exact);
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&Flags);
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setValue(&I, Res);
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setValue(&I, Res);
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}
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}
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@ -2671,8 +2671,9 @@ SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
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// TODO: For UDIV use SRL instead of SRA.
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// TODO: For UDIV use SRL instead of SRA.
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SDValue Amt =
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SDValue Amt =
|
||||||
DAG.getConstant(ShAmt, dl, getShiftAmountTy(Op1.getValueType()));
|
DAG.getConstant(ShAmt, dl, getShiftAmountTy(Op1.getValueType()));
|
||||||
Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false,
|
SDNodeFlags Flags;
|
||||||
true);
|
Flags.setExact(true);
|
||||||
|
Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, &Flags);
|
||||||
d = d.ashr(ShAmt);
|
d = d.ashr(ShAmt);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user