6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-30 19:55:11 +00:00
Code Issues Projects Releases Wiki Activity

[X86][MMX] Improve transfer from mmx to i32

Browse Source 
Improve EXTRACT_VECTOR_ELT DAG combine to catch conversion patterns
between x86mmx and i32 with more layers of indirection.

Before:
  movq2dq %mm0, %xmm0
  movd %xmm0, %eax
After:
  movd %mm0, %eax

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227969 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2015-02-03 14:46:49 +00:00
parent ba4bdb4b1b
commit 7df357f552
2 changed files with 27 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
lib/Target/X86/X86ISelLowering.cpp
View File

@ -22764,14 +22764,29 @@ static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
SDValue InputVector = N->getOperand(0);
// Detect whether we are trying to convert from mmx to i32 and the bitcast
// from mmx to v2i32 has a single usage.
if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
N->getValueType(0),
InputVector.getNode()->getOperand(0));
// Detect mmx to i32 conversion through a v2i32 elt extract.
if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
N->getValueType(0) == MVT::i32 &&
InputVector.getValueType() == MVT::v2i32) {
// The bitcast source is a direct mmx result.
SDValue MMXSrc = InputVector.getNode()->getOperand(0);
if (MMXSrc.getValueType() == MVT::x86mmx)
return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
N->getValueType(0),
InputVector.getNode()->getOperand(0));
// The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
SDValue MMXSrcOp = MMXSrc.getOperand(0);
if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
MMXSrcOp.getOpcode() == ISD::BITCAST &&
MMXSrcOp.getValueType() == MVT::v1i64 &&
MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
N->getValueType(0),
MMXSrcOp.getOperand(0));
}
// Only operate on vectors of 4 elements, where the alternative shuffling
// gets to be more expensive.

11
test/CodeGen/X86/vec_extract-mmx.ll
View File

@ -4,8 +4,7 @@ define i32 @test0(<1 x i64>* %v4) {
; CHECK-LABEL: test0:
; CHECK: ## BB#0:
; CHECK-NEXT: pshufw $238, (%rdi), %mm0
; CHECK-NEXT: movq2dq %mm0, %xmm0
; CHECK-NEXT: movd %xmm0, %eax
; CHECK-NEXT: movd %mm0, %eax
; CHECK-NEXT: addl $32, %eax
; CHECK-NEXT: retq
%v5 = load <1 x i64>* %v4, align 8
@ -24,11 +23,10 @@ define i32 @test0(<1 x i64>* %v4) {
define i32 @test1(i32* nocapture readonly %ptr) {
; CHECK-LABEL: test1:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: movd (%rdi), %xmm0
; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: pshufw $232, -{{[0-9]+}}(%rsp), %mm0
; CHECK-NEXT: movq2dq %mm0, %xmm0
; CHECK-NEXT: movd %xmm0, %eax
; CHECK-NEXT: movd %mm0, %eax
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
@ -54,8 +52,7 @@ define i32 @test2(i32* nocapture readonly %ptr) {
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: movq (%rdi), %mm0
; CHECK-NEXT: pshufw $232, %mm0, %mm0
; CHECK-NEXT: movq2dq %mm0, %xmm0
; CHECK-NEXT: movd %xmm0, %eax
; CHECK-NEXT: movd %mm0, %eax
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry: