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[x86] Hoist the logic for extracting the relevant bits of information
from the MachineInstr into the caller which is already doing a switch over the instruction. This will make it more clear how to compute different operands to feed the comment selection for example. Also, in a drive-by-fix, don't append an empty comment string (which is a no-op ultimately). No functionality changed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218361 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -864,22 +864,16 @@ PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
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return --MBBI;
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return --MBBI;
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}
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}
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static std::string getShuffleComment(const MachineInstr &MI) {
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static std::string getShuffleComment(int Opcode, const MachineOperand &DstOp,
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const MachineOperand &SrcOp,
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const MachineOperand &MaskOp,
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ArrayRef<MachineConstantPoolEntry> Constants) {
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std::string Comment;
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std::string Comment;
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SmallVector<int, 16> Mask;
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SmallVector<int, 16> Mask;
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// All of these instructions accept a constant pool operand as their fifth.
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assert(MI.getNumOperands() > 5 &&
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"We should always have at least 5 operands!");
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const MachineOperand &DstOp = MI.getOperand(0);
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const MachineOperand &SrcOp = MI.getOperand(1);
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const MachineOperand &MaskOp = MI.getOperand(5);
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if (!MaskOp.isCPI())
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if (!MaskOp.isCPI())
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return Comment;
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return Comment;
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ArrayRef<MachineConstantPoolEntry> Constants =
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MI.getParent()->getParent()->getConstantPool()->getConstants();
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const MachineConstantPoolEntry &MaskConstantEntry =
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const MachineConstantPoolEntry &MaskConstantEntry =
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Constants[MaskOp.getIndex()];
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Constants[MaskOp.getIndex()];
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@ -895,7 +889,7 @@ static std::string getShuffleComment(const MachineInstr &MI) {
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assert(MaskConstantEntry.getType() == C->getType() &&
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assert(MaskConstantEntry.getType() == C->getType() &&
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"Expected a constant of the same type!");
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"Expected a constant of the same type!");
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switch (MI.getOpcode()) {
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switch (Opcode) {
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case X86::PSHUFBrm:
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case X86::PSHUFBrm:
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case X86::VPSHUFBrm:
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case X86::VPSHUFBrm:
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DecodePSHUFBMask(C, Mask);
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DecodePSHUFBMask(C, Mask);
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@ -1118,17 +1112,27 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
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return;
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return;
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}
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}
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// Lower PSHUFB and VPERMILP normally but add a comment if we can find
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// a constant shuffle mask. We won't be able to do this at the MC layer
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// because the mask isn't an immediate.
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case X86::PSHUFBrm:
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case X86::PSHUFBrm:
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case X86::VPSHUFBrm:
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case X86::VPSHUFBrm:
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case X86::VPERMILPSrm:
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case X86::VPERMILPSrm:
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case X86::VPERMILPDrm:
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case X86::VPERMILPDrm:
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case X86::VPERMILPSYrm:
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case X86::VPERMILPSYrm:
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case X86::VPERMILPDYrm: {
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case X86::VPERMILPDYrm: {
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// Lower PSHUFB and VPERMILP normally but add a comment if we can find
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// All of these instructions accept a constant pool operand as their fifth.
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// a constant shuffle mask. We won't be able to do this at the MC layer
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assert(MI->getNumOperands() > 5 &&
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// because the mask isn't an immediate.
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"We should always have at least 5 operands!");
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std::string Comment = getShuffleComment(*MI);
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const MachineOperand &DstOp = MI->getOperand(0);
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OutStreamer.AddComment(Comment);
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const MachineOperand &SrcOp = MI->getOperand(1);
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const MachineOperand &MaskOp = MI->getOperand(5);
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std::string Comment = getShuffleComment(
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MI->getOpcode(), DstOp, SrcOp, MaskOp,
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MI->getParent()->getParent()->getConstantPool()->getConstants());
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if (!Comment.empty())
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OutStreamer.AddComment(Comment);
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break;
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break;
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}
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}
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}
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}
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