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[x86] Remove a couple of fairly pointless tests. These were merely

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testing that we generated divps and divss but not in a very systematic
way. There are other tests for widening binary operations already that
make these unnecessary.

The second one seems mostly about testing Atom as well as normal X86,
but despite the comment claiming it is testing a different instruction
sequence, it then tests for exactly the same div instruction sequence!
(The sequence of instructions is actually quite different on Atom, but
not the sequence of div instructions....)

And then it has an "execution" test that simply isn't run? Very strange.
Anyways, none of this is really needed so clean this up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218972 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth 2014-10-03 09:43:19 +00:00
parent c75d43e0c0
commit 7e26571a69
2 changed files with 0 additions and 58 deletions
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11
test/CodeGen/X86/v-binop-widen.ll
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@ -1,11 +0,0 @@
; RUN: llc -mcpu=generic -march=x86 -mattr=+sse < %s | FileCheck %s
; CHECK: divps
; CHECK: divps
; CHECK: divss
%vec = type <9 x float>
define %vec @vecdiv( %vec %p1, %vec %p2)
{
%result = fdiv %vec %p1, %p2
ret %vec %result
}

47
test/CodeGen/X86/v-binop-widen2.ll
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@ -1,47 +0,0 @@
; RUN: llc -march=x86 -mcpu=generic -mattr=+sse < %s | FileCheck %s
; RUN: llc -march=x86 -mcpu=atom -mattr=+sse < %s | FileCheck -check-prefix=ATOM %s
%vec = type <6 x float>
; CHECK: divps
; CHECK: divss
; CHECK: divss
; Scheduler causes a different instruction order to be produced on Intel Atom
; ATOM: divps
; ATOM: divss
; ATOM: divss
define %vec @vecdiv( %vec %p1, %vec %p2)
{
%result = fdiv %vec %p1, %p2
ret %vec %result
}
@a = constant %vec < float 2.0, float 4.0, float 8.0, float 16.0, float 32.0, float 64.0 >
@b = constant %vec < float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0 >
; Expected result: < 1.0, 2.0, 4.0, ..., 2.0^(n-1) >
; main() returns 0 if the result is expected and 1 otherwise
; to execute, use llvm-as < %s | lli
define i32 @main() nounwind {
entry:
%avec = load %vec* @a
%bvec = load %vec* @b
%res = call %vec @vecdiv(%vec %avec, %vec %bvec)
br label %loop
loop:
%idx = phi i32 [0, %entry], [%nextInd, %looptail]
%expected = phi float [1.0, %entry], [%nextExpected, %looptail]
%elem = extractelement %vec %res, i32 %idx
%expcmp = fcmp oeq float %elem, %expected
br i1 %expcmp, label %looptail, label %return
looptail:
%nextExpected = fmul float %expected, 2.0
%nextInd = add i32 %idx, 1
%cmp = icmp slt i32 %nextInd, 6
br i1 %cmp, label %loop, label %return
return:
%retval = phi i32 [0, %looptail], [1, %loop]
ret i32 %retval
}