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https://github.com/c64scene-ar/llvm-6502.git
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Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -454,6 +454,9 @@ void ScheduleDAGSDNodes::ComputeOperandLatency(SDNode *Def, SDNode *Use,
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return;
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unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
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if (Use->isMachineOpcode())
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// Adjust the use operand index by num of defs.
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OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
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int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
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if (Latency >= 0)
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dep.setLatency(Latency);
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@ -1823,8 +1823,8 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
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// This may be a def / use of a variable_ops instruction, the operand
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// latency might be determinable dynamically. Let the target try to
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// figure it out.
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bool LdmBypass = false;
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int DefCycle = -1;
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bool LdmBypass = false;
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switch (DefTID.getOpcode()) {
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default:
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DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
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@ -1922,8 +1922,38 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
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? (*DefMI->memoperands_begin())->getAlignment() : 0;
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unsigned UseAlign = UseMI->hasOneMemOperand()
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? (*UseMI->memoperands_begin())->getAlignment() : 0;
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return getOperandLatency(ItinData, DefTID, DefIdx, DefAlign,
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UseTID, UseIdx, UseAlign);
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int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign,
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UseTID, UseIdx, UseAlign);
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if (Latency > 1 &&
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(Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
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// FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
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// variants are one cycle cheaper.
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switch (DefTID.getOpcode()) {
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default: break;
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case ARM::LDRrs:
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case ARM::LDRBrs: {
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unsigned ShOpVal = DefMI->getOperand(3).getImm();
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unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
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if (ShImm == 0 ||
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(ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
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--Latency;
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break;
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}
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case ARM::t2LDRs:
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case ARM::t2LDRBs:
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case ARM::t2LDRHs:
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case ARM::t2LDRSHs: {
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// Thumb2 mode: lsl only.
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unsigned ShAmt = DefMI->getOperand(3).getImm();
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if (ShAmt == 0 || ShAmt == 2)
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--Latency;
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break;
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}
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}
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}
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return Latency;
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}
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int
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@ -1947,8 +1977,40 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
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const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
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unsigned UseAlign = !UseMN->memoperands_empty()
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? (*UseMN->memoperands_begin())->getAlignment() : 0;
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return getOperandLatency(ItinData, DefTID, DefIdx, DefAlign,
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UseTID, UseIdx, UseAlign);
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int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign,
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UseTID, UseIdx, UseAlign);
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if (Latency > 1 &&
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(Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
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// FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
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// variants are one cycle cheaper.
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switch (DefTID.getOpcode()) {
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default: break;
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case ARM::LDRrs:
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case ARM::LDRBrs: {
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unsigned ShOpVal =
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cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
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unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
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if (ShImm == 0 ||
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(ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
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--Latency;
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break;
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}
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case ARM::t2LDRs:
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case ARM::t2LDRBs:
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case ARM::t2LDRHs:
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case ARM::t2LDRSHs: {
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// Thumb2 mode: lsl only.
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unsigned ShAmt =
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cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
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if (ShAmt == 0 || ShAmt == 2)
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--Latency;
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break;
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}
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}
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}
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return Latency;
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}
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bool ARMBaseInstrInfo::
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@ -1438,13 +1438,13 @@ def RFE : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
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// Load
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defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_i, IIC_iLoad_r,
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defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
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UnOpFrag<(load node:$Src)>>;
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defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_r,
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defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
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UnOpFrag<(zextloadi8 node:$Src)>>;
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defm STR : AI_str1<0, "str", IIC_iStore_i, IIC_iStore_r,
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defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
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BinOpFrag<(store node:$LHS, node:$RHS)>>;
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defm STRB : AI_str1<1, "strb", IIC_iStore_bh_i, IIC_iStore_bh_r,
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defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
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BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
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// Special LDR for loads from non-pc-relative constpools.
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@ -574,7 +574,7 @@ multiclass T2I_cmp_irs<bits<4> opcod, string opc,
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/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
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multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
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InstrItinClass iii, InstrItinClass iir, PatFrag opnode> {
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InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
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def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), iii,
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opc, ".w\t$dst, $addr",
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[(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> {
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@ -599,7 +599,7 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
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let Inst{10} = 1; // The P bit.
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let Inst{8} = 0; // The W bit.
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}
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def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), iir,
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def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), iis,
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opc, ".w\t$dst, $addr",
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[(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> {
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let Inst{31-27} = 0b11111;
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@ -626,7 +626,7 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
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/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
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multiclass T2I_st<bits<2> opcod, string opc,
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InstrItinClass iii, InstrItinClass iir, PatFrag opnode> {
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InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
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def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), iii,
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opc, ".w\t$src, $addr",
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[(opnode GPR:$src, t2addrmode_imm12:$addr)]> {
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@ -647,7 +647,7 @@ multiclass T2I_st<bits<2> opcod, string opc,
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let Inst{10} = 1; // The P bit.
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let Inst{8} = 0; // The W bit.
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}
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def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), iir,
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def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), iis,
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opc, ".w\t$src, $addr",
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[(opnode GPR:$src, t2addrmode_so_reg:$addr)]> {
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let Inst{31-27} = 0b11111;
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@ -916,19 +916,19 @@ def t2UDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
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// Load
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let canFoldAsLoad = 1, isReMaterializable = 1 in
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defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_r,
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defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si,
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UnOpFrag<(load node:$Src)>>;
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// Loads with zero extension
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defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_r,
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defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
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UnOpFrag<(zextloadi16 node:$Src)>>;
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defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_r,
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defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
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UnOpFrag<(zextloadi8 node:$Src)>>;
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// Loads with sign extension
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defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_r,
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defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
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UnOpFrag<(sextloadi16 node:$Src)>>;
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defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_r,
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defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
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UnOpFrag<(sextloadi8 node:$Src)>>;
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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@ -1070,11 +1070,11 @@ def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
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def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
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// Store
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defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_r,
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defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si,
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BinOpFrag<(store node:$LHS, node:$RHS)>>;
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defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_r,
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defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
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BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
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defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_r,
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defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
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BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
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// Store doubleword
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InstrStage<1, [A9_DRegsVFP], 0, Required>,
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InstrStage<9, [A9_DRegsN], 0, Reserved>,
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InstrStage<1, [A9_NPipe]>],
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[8, 0, 1, 1]>,
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[8, 1, 1, 1]>,
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//
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// Double-precision FP MAC
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InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
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@ -582,7 +582,7 @@ def CortexA9Itineraries : ProcessorItineraries<
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InstrStage<1, [A9_DRegsVFP], 0, Required>,
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InstrStage<10, [A9_DRegsN], 0, Reserved>,
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InstrStage<2, [A9_NPipe]>],
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[9, 0, 1, 1]>,
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[9, 1, 1, 1]>,
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//
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// Single-precision FP DIV
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InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
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@ -24,4 +24,4 @@ declare float @fabsf(float)
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; CORTEXA8: test:
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; CORTEXA8: vabs.f32 d1, d1
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; CORTEXA9: test:
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; CORTEXA9: vabs.f32 s0, s0
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; CORTEXA9: vabs.f32 s1, s1
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@ -20,4 +20,4 @@ entry:
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; CORTEXA8: test:
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; CORTEXA8: vadd.f32 d0, d1, d0
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; CORTEXA9: test:
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; CORTEXA9: vadd.f32 s0, s0, s1
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; CORTEXA9: vadd.f32 s0, s1, s0
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@ -20,4 +20,4 @@ entry:
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; CORTEXA8: test:
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; CORTEXA8: vdiv.f32 s0, s1, s0
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; CORTEXA9: test:
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; CORTEXA9: vdiv.f32 s0, s0, s1
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; CORTEXA9: vdiv.f32 s0, s1, s0
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@ -21,4 +21,4 @@ entry:
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; CORTEXA8: test:
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; CORTEXA8: vmul.f32 d0, d1, d0
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; CORTEXA9: test:
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; CORTEXA9: vmla.f32 s0, s1, s2
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; CORTEXA9: vmla.f32 s2, s1, s0
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@ -19,6 +19,6 @@ entry:
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; NFP0: vnmls.f32 s2, s1, s0
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; CORTEXA8: test:
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; CORTEXA8: vnmls.f32 s1, s2, s0
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; CORTEXA8: vnmls.f32 s2, s1, s0
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; CORTEXA9: test:
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; CORTEXA9: vnmls.f32 s0, s1, s2
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; CORTEXA9: vnmls.f32 s2, s1, s0
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@ -20,4 +20,4 @@ entry:
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; CORTEXA8: test:
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; CORTEXA8: vmul.f32 d0, d1, d0
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; CORTEXA9: test:
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; CORTEXA9: vmul.f32 s0, s0, s1
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; CORTEXA9: vmul.f32 s0, s1, s0
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@ -36,8 +36,8 @@ entry:
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; lsl #2 is free
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; A9: test3:
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; A9: ldr r1, [r1, r2, lsl #2]
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; A9: ldr r0, [r0, r2, lsl #2]
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; A9: ldr r1, [r1, r2, lsl #2]
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%tmp1 = shl i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i32*
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