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Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like

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the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2010-10-27 23:12:14 +00:00
parent 0bccec368a
commit 7e3383c007
9 changed files with 94 additions and 101 deletions
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lib/Target/ARM/ARMInstrInfo.cpp
+2 -2
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@@ -48,13 +48,13 @@ unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
return ARM::LDRSB;
case ARM::STR_PRE:
case ARM::STR_POST:
return ARM::STR;
return ARM::STRi12;
case ARM::STRH_PRE:
case ARM::STRH_POST:
return ARM::STRH;
case ARM::STRB_PRE:
case ARM::STRB_POST:
return ARM::STRB;
return ARM::STRBi12;
}
return 0;