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Always use either MVT::i1 or getSetCCResultType for
the condition of a SELECT node. Make sure that the correct extension type (any-, sign- or zero-extend) is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57836 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -364,14 +364,18 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
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}
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SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
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MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
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MVT SVT = TLI.getSetCCResultType(N->getOperand(0));
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assert(isTypeLegal(SVT) && "SetCC type not legal??");
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assert(isTypeLegal(SVT) && "Illegal SetCC type!");
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// Get the SETCC result using the canonical SETCC type.
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SDValue SetCC = DAG.getNode(ISD::SETCC, SVT, N->getOperand(0),
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N->getOperand(1), N->getOperand(2));
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// Convert to the expected type.
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MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
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assert(NVT.getSizeInBits() <= SVT.getSizeInBits() &&
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"Integer type overpromoted?");
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return DAG.getNode(ISD::TRUNCATE, NVT,
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DAG.getNode(ISD::SETCC, SVT, N->getOperand(0),
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N->getOperand(1), N->getOperand(2)));
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return DAG.getNode(ISD::TRUNCATE, NVT, SetCC);
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}
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SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
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@ -731,18 +735,50 @@ SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
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SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
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assert(OpNo == 0 && "Only know how to promote condition");
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SDValue Cond = GetPromotedInteger(N->getOperand(0)); // Promote condition.
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assert(N->getOperand(0).getValueType() == MVT::i1 &&
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"SetCC type is not legal??");
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SDValue Cond = GetPromotedInteger(N->getOperand(0));
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// The top bits of the promoted condition are not necessarily zero, ensure
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// that the value is properly zero extended.
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unsigned BitWidth = Cond.getValueSizeInBits();
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if (!DAG.MaskedValueIsZero(Cond,
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APInt::getHighBitsSet(BitWidth, BitWidth-1)))
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Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
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// Promote all the way up to SVT, the canonical SetCC type.
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MVT SVT = TLI.getSetCCResultType(Cond);
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assert(isTypeLegal(SVT) && "Illegal SetCC type!");
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assert(Cond.getValueSizeInBits() <= SVT.getSizeInBits() &&
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"Integer type overpromoted?");
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// The chain (Op#0) and basic block destination (Op#2) are always legal types.
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return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, N->getOperand(1),
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N->getOperand(2));
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// Make sure the extra bits conform to getSetCCResultContents. There are
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// two sets of extra bits: those in Cond, which come from type promotion,
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// and those we need to add to have the final type be SVT (for most targets
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// this last set of bits is empty).
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unsigned CondBits = Cond.getValueSizeInBits();
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ISD::NodeType ExtendCode;
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switch (TLI.getSetCCResultContents()) {
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default:
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assert(false && "Unknown SetCCResultValue!");
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case TargetLowering::UndefinedSetCCResult:
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// Extend to SVT by adding rubbish.
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ExtendCode = ISD::ANY_EXTEND;
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break;
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case TargetLowering::ZeroOrOneSetCCResult:
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ExtendCode = ISD::ZERO_EXTEND;
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if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1)))
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// All extra bits need to be cleared. Do this by zero extending the
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// original MVT::i1 condition value all the way to SVT.
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Cond = N->getOperand(0);
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break;
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case TargetLowering::ZeroOrNegativeOneSetCCResult: {
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ExtendCode = ISD::SIGN_EXTEND;
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unsigned SignBits = DAG.ComputeNumSignBits(Cond);
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if (SignBits != CondBits)
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// All extra bits need to be sign extended. Do this by sign extending the
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// original MVT::i1 condition value all the way to SVT.
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Cond = N->getOperand(0);
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break;
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}
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}
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Cond = DAG.getNode(ExtendCode, SVT, Cond);
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return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
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N->getOperand(1), N->getOperand(2));
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}
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SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
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