mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-03-19 04:31:17 +00:00
[FastISel][AArch64] Don't perform sign-/zero-extension for function arguments that have already been sign-/zero-extended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214844 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
parent
d047a9df7d
commit
7e9c0bc511
@ -2335,9 +2335,31 @@ bool AArch64FastISel::SelectIntExt(const Instruction *I) {
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MVT SrcVT = SrcEVT.getSimpleVT();
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MVT DestVT = DestEVT.getSimpleVT();
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unsigned ResultReg = EmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
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if (ResultReg == 0)
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unsigned ResultReg = 0;
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// Check if it is an argument and if it is already zero/sign-extended.
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if (const auto *Arg = dyn_cast<Argument>(Src)) {
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if ((isZExt && Arg->hasZExtAttr()) || (!isZExt && Arg->hasSExtAttr())) {
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ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
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if (DestVT == MVT::i64)
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AArch64::SUBREG_TO_REG), ResultReg)
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.addImm(0)
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.addReg(SrcReg)
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.addImm(AArch64::sub_32);
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else
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(SrcReg);
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}
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}
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if (!ResultReg)
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ResultReg = EmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
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if (!ResultReg)
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return false;
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UpdateValueMap(I, ResultReg);
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return true;
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}
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@ -3,7 +3,7 @@
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;; Test various conversions.
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define zeroext i32 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
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entry:
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; CHECK: trunc_
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; CHECK-LABEL: trunc_
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; CHECK: sub sp, sp, #16
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; CHECK: strb w0, [sp, #15]
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; CHECK: strh w1, [sp, #12]
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@ -44,7 +44,7 @@ entry:
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define i64 @zext_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
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entry:
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; CHECK: zext_
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; CHECK-LABEL: zext_
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; CHECK: sub sp, sp, #16
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; CHECK: strb w0, [sp, #15]
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; CHECK: strh w1, [sp, #12]
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@ -85,23 +85,25 @@ entry:
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define i32 @zext_i1_i32(i1 zeroext %a) nounwind ssp {
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entry:
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; CHECK: @zext_i1_i32
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; CHECK: and w0, w0, #0x1
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; CHECK-LABEL: zext_i1_i32
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; CHECK-NOT: and w0, w0, #0x1
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; CHECK: ret
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%conv = zext i1 %a to i32
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ret i32 %conv;
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}
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define i64 @zext_i1_i64(i1 zeroext %a) nounwind ssp {
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entry:
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; CHECK: @zext_i1_i64
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; CHECK: and w0, w0, #0x1
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; CHECK-LABEL: zext_i1_i64
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; CHECK-NOT: and w0, w0, #0x1
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; CHECK: ret
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%conv = zext i1 %a to i64
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ret i64 %conv;
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}
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define i64 @sext_(i8 signext %a, i16 signext %b, i32 %c, i64 %d) nounwind ssp {
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entry:
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; CHECK: sext_
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; CHECK-LABEL: sext_
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; CHECK: sub sp, sp, #16
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; CHECK: strb w0, [sp, #15]
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; CHECK: strh w1, [sp, #12]
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@ -161,8 +163,9 @@ define zeroext i64 @sext_i16_i64(i16 zeroext %in) {
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; Test sext i1 to i32
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define i32 @sext_i1_i32(i1 signext %a) nounwind ssp {
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entry:
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; CHECK: sext_i1_i32
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; CHECK: sbfx w0, w0, #0, #1
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; CHECK-LABEL: sext_i1_i32
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; CHECK-NOT: sbfx w0, w0, #0, #1
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; CHECK: ret
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%conv = sext i1 %a to i32
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ret i32 %conv
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}
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@ -170,7 +173,7 @@ entry:
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; Test sext i1 to i16
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define signext i16 @sext_i1_i16(i1 %a) nounwind ssp {
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entry:
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; CHECK: sext_i1_i16
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; CHECK-LABEL: sext_i1_i16
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; CHECK: sbfx w0, w0, #0, #1
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%conv = sext i1 %a to i16
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ret i16 %conv
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@ -179,7 +182,7 @@ entry:
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; Test sext i1 to i8
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define signext i8 @sext_i1_i8(i1 %a) nounwind ssp {
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entry:
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; CHECK: sext_i1_i8
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; CHECK-LABEL: sext_i1_i8
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; CHECK: sbfx w0, w0, #0, #1
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%conv = sext i1 %a to i8
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ret i8 %conv
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@ -188,7 +191,7 @@ entry:
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; Test fpext
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define double @fpext_(float %a) nounwind ssp {
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entry:
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; CHECK: fpext_
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; CHECK-LABEL: fpext_
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; CHECK: fcvt d0, s0
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%conv = fpext float %a to double
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ret double %conv
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@ -197,7 +200,7 @@ entry:
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; Test fptrunc
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define float @fptrunc_(double %a) nounwind ssp {
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entry:
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; CHECK: fptrunc_
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; CHECK-LABEL: fptrunc_
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; CHECK: fcvt s0, d0
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%conv = fptrunc double %a to float
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ret float %conv
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@ -206,7 +209,7 @@ entry:
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; Test fptosi
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define i32 @fptosi_ws(float %a) nounwind ssp {
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entry:
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; CHECK: fptosi_ws
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; CHECK-LABEL: fptosi_ws
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; CHECK: fcvtzs w0, s0
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%conv = fptosi float %a to i32
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ret i32 %conv
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@ -215,7 +218,7 @@ entry:
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; Test fptosi
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define i32 @fptosi_wd(double %a) nounwind ssp {
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entry:
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; CHECK: fptosi_wd
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; CHECK-LABEL: fptosi_wd
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; CHECK: fcvtzs w0, d0
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%conv = fptosi double %a to i32
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ret i32 %conv
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@ -224,7 +227,7 @@ entry:
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; Test fptoui
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define i32 @fptoui_ws(float %a) nounwind ssp {
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entry:
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; CHECK: fptoui_ws
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; CHECK-LABEL: fptoui_ws
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; CHECK: fcvtzu w0, s0
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%conv = fptoui float %a to i32
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ret i32 %conv
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@ -233,7 +236,7 @@ entry:
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; Test fptoui
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define i32 @fptoui_wd(double %a) nounwind ssp {
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entry:
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; CHECK: fptoui_wd
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; CHECK-LABEL: fptoui_wd
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; CHECK: fcvtzu w0, d0
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%conv = fptoui double %a to i32
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ret i32 %conv
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@ -242,7 +245,7 @@ entry:
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; Test sitofp
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define float @sitofp_sw_i1(i1 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_sw_i1
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; CHECK-LABEL: sitofp_sw_i1
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; CHECK: sbfx w0, w0, #0, #1
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; CHECK: scvtf s0, w0
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%conv = sitofp i1 %a to float
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@ -252,7 +255,7 @@ entry:
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; Test sitofp
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define float @sitofp_sw_i8(i8 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_sw_i8
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; CHECK-LABEL: sitofp_sw_i8
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; CHECK: sxtb w0, w0
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; CHECK: scvtf s0, w0
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%conv = sitofp i8 %a to float
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@ -262,9 +265,7 @@ entry:
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; Test sitofp
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define float @sitofp_sw_i16(i16 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_sw_i16
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; CHECK: sxth w0, w0
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; CHECK: scvtf s0, w0
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; CHECK-LABEL: sitofp_sw_i16
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%conv = sitofp i16 %a to float
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ret float %conv
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}
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@ -272,7 +273,7 @@ entry:
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; Test sitofp
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define float @sitofp_sw(i32 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_sw
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; CHECK-LABEL: sitofp_sw
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; CHECK: scvtf s0, w0
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%conv = sitofp i32 %a to float
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ret float %conv
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@ -281,7 +282,7 @@ entry:
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; Test sitofp
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define float @sitofp_sx(i64 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_sx
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; CHECK-LABEL: sitofp_sx
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; CHECK: scvtf s0, x0
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%conv = sitofp i64 %a to float
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ret float %conv
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@ -290,7 +291,7 @@ entry:
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; Test sitofp
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define double @sitofp_dw(i32 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_dw
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; CHECK-LABEL: sitofp_dw
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; CHECK: scvtf d0, w0
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%conv = sitofp i32 %a to double
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ret double %conv
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@ -299,7 +300,7 @@ entry:
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; Test sitofp
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define double @sitofp_dx(i64 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_dx
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; CHECK-LABEL: sitofp_dx
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; CHECK: scvtf d0, x0
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%conv = sitofp i64 %a to double
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ret double %conv
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@ -308,7 +309,7 @@ entry:
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; Test uitofp
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define float @uitofp_sw_i1(i1 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_sw_i1
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; CHECK-LABEL: uitofp_sw_i1
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; CHECK: and w0, w0, #0x1
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; CHECK: ucvtf s0, w0
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%conv = uitofp i1 %a to float
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@ -318,9 +319,7 @@ entry:
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; Test uitofp
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define float @uitofp_sw_i8(i8 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_sw_i8
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; CHECK: uxtb w0, w0
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; CHECK: ucvtf s0, w0
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; CHECK-LABEL: uitofp_sw_i8
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%conv = uitofp i8 %a to float
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ret float %conv
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}
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@ -328,9 +327,7 @@ entry:
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; Test uitofp
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define float @uitofp_sw_i16(i16 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_sw_i16
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; CHECK: uxth w0, w0
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; CHECK: ucvtf s0, w0
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; CHECK-LABEL: uitofp_sw_i16
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%conv = uitofp i16 %a to float
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ret float %conv
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}
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@ -338,7 +335,7 @@ entry:
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; Test uitofp
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define float @uitofp_sw(i32 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_sw
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; CHECK-LABEL: uitofp_sw
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; CHECK: ucvtf s0, w0
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%conv = uitofp i32 %a to float
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ret float %conv
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@ -347,7 +344,7 @@ entry:
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; Test uitofp
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define float @uitofp_sx(i64 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_sx
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; CHECK-LABEL: uitofp_sx
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; CHECK: ucvtf s0, x0
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%conv = uitofp i64 %a to float
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ret float %conv
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@ -356,7 +353,7 @@ entry:
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; Test uitofp
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define double @uitofp_dw(i32 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_dw
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; CHECK-LABEL: uitofp_dw
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; CHECK: ucvtf d0, w0
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%conv = uitofp i32 %a to double
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ret double %conv
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@ -365,7 +362,7 @@ entry:
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; Test uitofp
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define double @uitofp_dx(i64 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_dx
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; CHECK-LABEL: uitofp_dx
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; CHECK: ucvtf d0, x0
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%conv = uitofp i64 %a to double
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ret double %conv
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@ -373,7 +370,7 @@ entry:
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define i32 @i64_trunc_i32(i64 %a) nounwind ssp {
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entry:
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; CHECK: i64_trunc_i32
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; CHECK-LABEL: i64_trunc_i32
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; CHECK: mov x1, x0
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%conv = trunc i64 %a to i32
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ret i32 %conv
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@ -381,7 +378,7 @@ entry:
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define zeroext i16 @i64_trunc_i16(i64 %a) nounwind ssp {
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entry:
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; CHECK: i64_trunc_i16
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; CHECK-LABEL: i64_trunc_i16
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; CHECK: mov x[[REG:[0-9]+]], x0
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; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xffff
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; CHECK: uxth w0, [[REG2]]
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@ -391,7 +388,7 @@ entry:
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define zeroext i8 @i64_trunc_i8(i64 %a) nounwind ssp {
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entry:
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; CHECK: i64_trunc_i8
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; CHECK-LABEL: i64_trunc_i8
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; CHECK: mov x[[REG:[0-9]+]], x0
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; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xff
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; CHECK: uxtb w0, [[REG2]]
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@ -401,7 +398,7 @@ entry:
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define zeroext i1 @i64_trunc_i1(i64 %a) nounwind ssp {
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entry:
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; CHECK: i64_trunc_i1
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; CHECK-LABEL: i64_trunc_i1
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; CHECK: mov x[[REG:[0-9]+]], x0
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; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0x1
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; CHECK: and w0, [[REG2]], #0x1
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@ -411,7 +408,7 @@ entry:
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; rdar://15101939
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define void @stack_trunc() nounwind {
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; CHECK: stack_trunc
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; CHECK-LABEL: stack_trunc
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; CHECK: sub sp, sp, #16
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; CHECK: ldr [[REG:x[0-9]+]], [sp]
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; CHECK: mov x[[REG2:[0-9]+]], [[REG]]
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@ -428,15 +425,15 @@ define void @stack_trunc() nounwind {
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define zeroext i64 @zext_i8_i64(i8 zeroext %in) {
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; CHECK-LABEL: zext_i8_i64:
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; CHECK: mov x[[TMP:[0-9]+]], x0
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; CHECK: ubfx x0, x[[TMP]], #0, #8
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; CHECK-NOT: ubfx x0, {{x[0-9]+}}, #0, #8
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; CHECK: ret
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%big = zext i8 %in to i64
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ret i64 %big
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}
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define zeroext i64 @zext_i16_i64(i16 zeroext %in) {
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; CHECK-LABEL: zext_i16_i64:
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; CHECK: mov x[[TMP:[0-9]+]], x0
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; CHECK: ubfx x0, x[[TMP]], #0, #16
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; CHECK-NOT: ubfx x0, {{x[0-9]+}}, #0, #16
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; CHECK: ret
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%big = zext i16 %in to i64
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ret i64 %big
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}
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