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Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
2011-10-06 06:44:41 +00:00
parent cf2adb945a
commit 7ea16b01fa
6 changed files with 71 additions and 3 deletions
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11
lib/Target/X86/X86InstrInfo.td
View File

@@ -1154,11 +1154,11 @@ def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
"xchg{q}\t{$val, $src|$src, $val}", []>;
}
def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16_NOAX:$src),
"xchg{w}\t{$src, %ax|AX, $src}", []>, OpSize;
def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
"xchg{l}\t{$src, %eax|EAX, $src}", []>;
def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64_NOAX:$src),
"xchg{q}\t{$src, %rax|RAX, $src}", []>;
@@ -1714,3 +1714,8 @@ def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;
// xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16_NOAX:$src)>;
def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32_NOAX:$src)>;
def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64_NOAX:$src)>;

17
lib/Target/X86/X86RegisterInfo.td
View File

@@ -390,6 +390,23 @@ def GR64_NOREX : RegisterClass<"X86", [i64], 64,
(GR32_NOREX sub_32bit)];
}
// GR16_NOAX - GR16 registers except AX.
def GR16_NOAX : RegisterClass<"X86", [i16], 16, (sub GR16, AX)> {
let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi)];
}
// GR32_NOAX - GR32 registers except EAX.
def GR32_NOAX : RegisterClass<"X86", [i32], 32, (sub GR32, EAX)> {
let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16_NOAX sub_16bit)];
}
// GR64_NOAX - GR64 registers except RAX.
def GR64_NOAX : RegisterClass<"X86", [i64], 64, (sub GR64, RAX)> {
let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
(GR16_NOAX sub_16bit),
(GR32_NOAX sub_32bit)];
}
// GR32_NOSP - GR32 registers except ESP.
def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)> {
let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];