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Encoding for ARM LDRSH_POST.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118794 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-11-11 16:55:29 +00:00
parent 03f1b74aed
commit 7eab97f260
4 changed files with 39 additions and 7 deletions
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2
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -202,6 +202,8 @@ namespace {
Binary |= (Reg << 13);
return Binary;
}
uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
const { return 0;}
uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) const
{ return 0; }
uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {

20
lib/Target/ARM/ARMInstrFormats.td
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@ -886,14 +886,20 @@ class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern>
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
opc, asm, cstr,pattern> {
let Inst{4} = 1;
let Inst{5} = 1; // H bit
let Inst{6} = 1; // S bit
let Inst{7} = 1;
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 0; // P bit
bits<10> offset;
bits<4> Rt;
bits<4> Rn;
let Inst{27-25} = 0b000;
let Inst{24} = 0; // P bit
let Inst{23} = offset{8}; // U bit
let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
let Inst{21} = 0; // W bit
let Inst{20} = 1; // L bit
let Inst{19-16} = Rn; // Rn
let Inst{15-12} = Rt; // Rt
let Inst{11-8} = offset{7-4}; // imm7_4/zero
let Inst{7-4} = 0b1111;
let Inst{3-0} = offset{3-0}; // imm3_0/Rm
}
class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern>

1
lib/Target/ARM/ARMInstrInfo.td
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@ -450,6 +450,7 @@ def addrmode3 : Operand<i32>,
def am3offset : Operand<i32>,
ComplexPattern<i32, 2, "SelectAddrMode3Offset",
[], [SDNPWantRoot]> {
string EncoderMethod = "getAddrMode3OffsetOpValue";
let PrintMethod = "printAddrMode3OffsetOperand";
let MIOperandInfo = (ops GPR, i32imm);
}

23
lib/Target/ARM/ARMMCCodeEmitter.cpp
View File

@ -94,6 +94,10 @@ public:
case ARM_AM::ib: return 3;
}
}
/// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const;
/// getAddrMode3OpValue - Return encoding for addrmode3 operands.
uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const;
@ -318,6 +322,25 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
return Binary;
}
uint32_t ARMMCCodeEmitter::
getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const {
// {9} 1 == imm8, 0 == Rm
// {8} isAdd
// {7-4} imm7_4/zero
// {3-0} imm3_0/Rm
const MCOperand &MO = MI.getOperand(OpIdx);
const MCOperand &MO1 = MI.getOperand(OpIdx+1);
unsigned Imm = MO1.getImm();
bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
bool isImm = MO.getReg() == 0;
uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
// if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
if (!isImm)
Imm8 = getARMRegisterNumbering(MO.getReg());
return Imm8 | (isAdd << 8) | (isImm << 9);
}
uint32_t ARMMCCodeEmitter::
getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const {