From 7ebd32a1b87553d98215ae159489c1407e50e34c Mon Sep 17 00:00:00 2001 From: Johnny Chen Date: Mon, 23 Nov 2009 18:16:16 +0000 Subject: [PATCH] Partially revert r89377 by removing NLdStLN class definition from ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt instead of NLdStLN. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89684 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrFormats.td | 11 ----- lib/Target/ARM/ARMInstrNEON.td | 68 +++++++++++++++---------------- 2 files changed, 34 insertions(+), 45 deletions(-) diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index f840770f994..0bbf6960670 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -1248,17 +1248,6 @@ class NLdSt op21_20, bits<4> op11_8, bits<4> op7_4, let Inst{7-4} = op7_4; } -// With selective bit(s) from op7_4 specified by subclasses. -class NLdStLN op21_20, bits<4> op11_8, - dag oops, dag iops, InstrItinClass itin, - string opc, string asm, string cstr, list pattern> - : NeonI { - let Inst{31-24} = 0b11110100; - let Inst{23} = op23; - let Inst{21-20} = op21_20; - let Inst{11-8} = op11_8; -} - class NDataI pattern> : NeonI; // VLD2LN : Vector Load (single 2-element structure to one lane) class VLD2LN op11_8, string OpcodeStr> - : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), - IIC_VLD2, - OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr", - "$src1 = $dst1, $src2 = $dst2", []>; + : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2), + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), + IIC_VLD2, + OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr", + "$src1 = $dst1, $src2 = $dst2", []>; // vld2 to single-spaced registers. def VLD2LNd8 : VLD2LN<0b0001, "vld2.8">; @@ -313,12 +313,12 @@ def VLD2LNq32b: VLD2LN<0b1001, "vld2.32"> { // VLD3LN : Vector Load (single 3-element structure to one lane) class VLD3LN op11_8, string OpcodeStr> - : NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, - nohash_imm:$lane), IIC_VLD3, - OpcodeStr, - "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr", - "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>; + : NLdSt<1,0b10,op11_8,{?,?,?,?}, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, + nohash_imm:$lane), IIC_VLD3, + OpcodeStr, + "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr", + "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>; // vld3 to single-spaced registers. def VLD3LNd8 : VLD3LN<0b0010, "vld3.8"> { @@ -349,13 +349,13 @@ def VLD3LNq32b: VLD3LN<0b1010, "vld3.32"> { // VLD4LN : Vector Load (single 4-element structure to one lane) class VLD4LN op11_8, string OpcodeStr> - : NLdStLN<1,0b10,op11_8, - (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, - nohash_imm:$lane), IIC_VLD4, - OpcodeStr, - "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr", - "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>; + : NLdSt<1,0b10,op11_8,{?,?,?,?}, + (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, + nohash_imm:$lane), IIC_VLD4, + OpcodeStr, + "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr", + "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>; // vld4 to single-spaced registers. def VLD4LNd8 : VLD4LN<0b0011, "vld4.8">; @@ -504,11 +504,11 @@ def VST4q32b : VST4WB<0b1000, "vst4.32">; // VST2LN : Vector Store (single 2-element structure from one lane) class VST2LN op11_8, string OpcodeStr> - : NLdStLN<1,0b00,op11_8, (outs), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), - IIC_VST, - OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr", - "", []>; + : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs), + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), + IIC_VST, + OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr", + "", []>; // vst2 to single-spaced registers. def VST2LNd8 : VST2LN<0b0001, "vst2.8">; @@ -537,11 +537,11 @@ def VST2LNq32b: VST2LN<0b1001, "vst2.32"> { // VST3LN : Vector Store (single 3-element structure from one lane) class VST3LN op11_8, string OpcodeStr> - : NLdStLN<1,0b00,op11_8, (outs), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, - nohash_imm:$lane), IIC_VST, - OpcodeStr, - "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr", "", []>; + : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs), + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, + nohash_imm:$lane), IIC_VST, + OpcodeStr, + "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr", "", []>; // vst3 to single-spaced registers. def VST3LNd8 : VST3LN<0b0010, "vst3.8"> { @@ -572,12 +572,12 @@ def VST3LNq32b: VST3LN<0b1010, "vst3.32"> { // VST4LN : Vector Store (single 4-element structure from one lane) class VST4LN op11_8, string OpcodeStr> - : NLdStLN<1,0b00,op11_8, (outs), - (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, - nohash_imm:$lane), IIC_VST, - OpcodeStr, - "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr", - "", []>; + : NLdSt<1,0b00,op11_8,{?,?,?,?}, (outs), + (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, + nohash_imm:$lane), IIC_VST, + OpcodeStr, + "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr", + "", []>; // vst4 to single-spaced registers. def VST4LNd8 : VST4LN<0b0011, "vst4.8">;