From 7eedd07d5e660c2f261f640e825677b88a065a97 Mon Sep 17 00:00:00 2001
From: Daniel Sanders <daniel.sanders@imgtec.com>
Date: Wed, 18 Feb 2015 16:24:50 +0000
Subject: [PATCH] [mips] Add backend support for Mips32r[35] and Mips64r[35].

Summary:
These ISA's didn't add any instructions so they are almost identical to
Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA
revision in .MIPS.abiflags is 3 or 5 respectively instead of 2.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: tomatabacu, llvm-commits, atanasyan

Differential Revision: http://reviews.llvm.org/D7381


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229695 91177308-0d34-0410-b5e6-96231b3b80d8
---
 include/llvm/Support/ELF.h                    |   4 +-
 lib/Target/Mips/AsmParser/MipsAsmParser.cpp   |  47 ++-
 .../Mips/MCTargetDesc/MipsABIFlagsSection.h   |   8 +
 lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp  |   4 +
 .../Mips/MCTargetDesc/MipsTargetStreamer.cpp  |  32 +-
 lib/Target/Mips/Mips.td                       |  20 +-
 lib/Target/Mips/MipsSubtarget.h               |  14 +-
 lib/Target/Mips/MipsTargetStreamer.h          |   8 +
 test/CodeGen/Mips/llvm-ir/add.ll              |   8 +
 test/CodeGen/Mips/llvm-ir/and.ll              |   8 +
 test/CodeGen/Mips/llvm-ir/ashr.ll             |  38 ++-
 test/CodeGen/Mips/llvm-ir/call.ll             |   4 +
 test/CodeGen/Mips/llvm-ir/indirectbr.ll       |   4 +
 test/CodeGen/Mips/llvm-ir/lshr.ll             |  36 +-
 test/CodeGen/Mips/llvm-ir/mul.ll              |  58 ++--
 test/CodeGen/Mips/llvm-ir/or.ll               |   8 +
 test/CodeGen/Mips/llvm-ir/ret.ll              |   4 +
 test/CodeGen/Mips/llvm-ir/sdiv.ll             |  28 +-
 test/CodeGen/Mips/llvm-ir/select.ll           |  24 +-
 test/CodeGen/Mips/llvm-ir/shl.ll              |  36 +-
 test/CodeGen/Mips/llvm-ir/srem.ll             |  30 +-
 test/CodeGen/Mips/llvm-ir/sub.ll              |   8 +
 test/CodeGen/Mips/llvm-ir/udiv.ll             |   8 +
 test/CodeGen/Mips/llvm-ir/urem.ll             |  38 ++-
 test/CodeGen/Mips/llvm-ir/xor.ll              |   8 +
 .../Mips/mips32r3/valid-mips32r3-le.txt       | 169 ++++++++++
 .../Mips/mips32r3/valid-mips32r3.txt          | 169 ++++++++++
 .../Mips/mips32r3/valid-xfail-mips32r3.txt    |  83 +++++
 .../Mips/mips32r5/valid-mips32r5-le.txt       | 169 ++++++++++
 .../Mips/mips32r5/valid-mips32r5.txt          | 169 ++++++++++
 .../Mips/mips32r5/valid-xfail-mips32r5.txt    |  83 +++++
 .../Mips/mips64r2/valid-xfail-mips64r2.txt    |   2 +-
 .../Mips/mips64r3/valid-mips64r3-el.txt       | 234 +++++++++++++
 .../Mips/mips64r3/valid-mips64r3.txt          | 234 +++++++++++++
 .../Mips/mips64r3/valid-xfail-mips64r3.txt    |  76 +++++
 .../Mips/mips64r5/valid-mips64r5-el.txt       | 234 +++++++++++++
 .../Mips/mips64r5/valid-mips64r5.txt          | 234 +++++++++++++
 .../Mips/mips64r5/valid-xfail-mips64r5.txt    |  76 +++++
 test/MC/Mips/elf_eflags.s                     |   8 +
 test/MC/Mips/mips32r3/abiflags.s              |  37 +++
 test/MC/Mips/mips32r3/invalid-mips64r2.s      |  10 +
 test/MC/Mips/mips32r3/invalid.s               |  10 +
 test/MC/Mips/mips32r3/valid-xfail.s           | 308 +++++++++++++++++
 test/MC/Mips/mips32r3/valid.s                 | 236 +++++++++++++
 test/MC/Mips/mips32r5/abiflags.s              |  37 +++
 test/MC/Mips/mips32r5/invalid-mips64r2.s      |  10 +
 test/MC/Mips/mips32r5/invalid.s               |  10 +
 test/MC/Mips/mips32r5/valid-xfail.s           | 308 +++++++++++++++++
 test/MC/Mips/mips32r5/valid.s                 | 236 +++++++++++++
 test/MC/Mips/mips64r3/abi-bad.s               |   5 +
 test/MC/Mips/mips64r3/abiflags.s              |  36 ++
 test/MC/Mips/mips64r3/invalid.s               |  10 +
 test/MC/Mips/mips64r3/valid-xfail.s           | 310 ++++++++++++++++++
 test/MC/Mips/mips64r3/valid.s                 | 305 +++++++++++++++++
 test/MC/Mips/mips64r5/abi-bad.s               |   5 +
 test/MC/Mips/mips64r5/abiflags.s              |  36 ++
 test/MC/Mips/mips64r5/invalid.s               |  10 +
 test/MC/Mips/mips64r5/valid-xfail.s           | 310 ++++++++++++++++++
 test/MC/Mips/mips64r5/valid.s                 | 305 +++++++++++++++++
 test/MC/Mips/set-arch.s                       |  12 +
 test/MC/Mips/set-mips-directives-bad.s        |  12 +
 test/MC/Mips/set-mips-directives.s            |  24 ++
 62 files changed, 4892 insertions(+), 115 deletions(-)
 create mode 100644 test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-le.txt
 create mode 100644 test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
 create mode 100644 test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt
 create mode 100644 test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-le.txt
 create mode 100644 test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
 create mode 100644 test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt
 create mode 100644 test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
 create mode 100644 test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
 create mode 100644 test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt
 create mode 100644 test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
 create mode 100644 test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
 create mode 100644 test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt
 create mode 100644 test/MC/Mips/mips32r3/abiflags.s
 create mode 100644 test/MC/Mips/mips32r3/invalid-mips64r2.s
 create mode 100644 test/MC/Mips/mips32r3/invalid.s
 create mode 100644 test/MC/Mips/mips32r3/valid-xfail.s
 create mode 100644 test/MC/Mips/mips32r3/valid.s
 create mode 100644 test/MC/Mips/mips32r5/abiflags.s
 create mode 100644 test/MC/Mips/mips32r5/invalid-mips64r2.s
 create mode 100644 test/MC/Mips/mips32r5/invalid.s
 create mode 100644 test/MC/Mips/mips32r5/valid-xfail.s
 create mode 100644 test/MC/Mips/mips32r5/valid.s
 create mode 100644 test/MC/Mips/mips64r3/abi-bad.s
 create mode 100644 test/MC/Mips/mips64r3/abiflags.s
 create mode 100644 test/MC/Mips/mips64r3/invalid.s
 create mode 100644 test/MC/Mips/mips64r3/valid-xfail.s
 create mode 100644 test/MC/Mips/mips64r3/valid.s
 create mode 100644 test/MC/Mips/mips64r5/abi-bad.s
 create mode 100644 test/MC/Mips/mips64r5/abiflags.s
 create mode 100644 test/MC/Mips/mips64r5/invalid.s
 create mode 100644 test/MC/Mips/mips64r5/valid-xfail.s
 create mode 100644 test/MC/Mips/mips64r5/valid.s

diff --git a/include/llvm/Support/ELF.h b/include/llvm/Support/ELF.h
index 3e41a6be4a1..fc6f314433a 100644
--- a/include/llvm/Support/ELF.h
+++ b/include/llvm/Support/ELF.h
@@ -454,8 +454,8 @@ enum : unsigned {
   EF_MIPS_ARCH_5    = 0x40000000, // MIPS5 instruction set
   EF_MIPS_ARCH_32   = 0x50000000, // MIPS32 instruction set per linux not elf.h
   EF_MIPS_ARCH_64   = 0x60000000, // MIPS64 instruction set per linux not elf.h
-  EF_MIPS_ARCH_32R2 = 0x70000000, // mips32r2
-  EF_MIPS_ARCH_64R2 = 0x80000000, // mips64r2
+  EF_MIPS_ARCH_32R2 = 0x70000000, // mips32r2, mips32r3, mips32r5
+  EF_MIPS_ARCH_64R2 = 0x80000000, // mips64r2, mips64r3, mips64r5
   EF_MIPS_ARCH_32R6 = 0x90000000, // mips32r6
   EF_MIPS_ARCH_64R6 = 0xa0000000, // mips64r6
   EF_MIPS_ARCH      = 0xf0000000  // Mask for applying EF_MIPS_ARCH_ variant
diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 7d02c542de4..1040bf7ffe6 100644
--- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -76,9 +76,10 @@ public:
       Mips::FeatureMips3_32 | Mips::FeatureMips3_32r2 | Mips::FeatureMips4 |
       Mips::FeatureMips4_32 | Mips::FeatureMips4_32r2 | Mips::FeatureMips5 |
       Mips::FeatureMips5_32r2 | Mips::FeatureMips32 | Mips::FeatureMips32r2 |
-      Mips::FeatureMips32r6 | Mips::FeatureMips64 | Mips::FeatureMips64r2 |
-      Mips::FeatureMips64r6 | Mips::FeatureCnMips | Mips::FeatureFP64Bit |
-      Mips::FeatureGP64Bit | Mips::FeatureNaN2008;
+      Mips::FeatureMips32r3 | Mips::FeatureMips32r5 | Mips::FeatureMips32r6 |
+      Mips::FeatureMips64 | Mips::FeatureMips64r2 | Mips::FeatureMips64r3 |
+      Mips::FeatureMips64r5 | Mips::FeatureMips64r6 | Mips::FeatureCnMips |
+      Mips::FeatureFP64Bit | Mips::FeatureGP64Bit | Mips::FeatureNaN2008;
 
 private:
   unsigned ATReg;
@@ -386,6 +387,18 @@ public:
   bool hasMips64r2() const {
     return (STI.getFeatureBits() & Mips::FeatureMips64r2);
   }
+  bool hasMips32r3() const {
+    return (STI.getFeatureBits() & Mips::FeatureMips32r3);
+  }
+  bool hasMips64r3() const {
+    return (STI.getFeatureBits() & Mips::FeatureMips64r3);
+  }
+  bool hasMips32r5() const {
+    return (STI.getFeatureBits() & Mips::FeatureMips32r5);
+  }
+  bool hasMips64r5() const {
+    return (STI.getFeatureBits() & Mips::FeatureMips64r5);
+  }
   bool hasMips32r6() const {
     return (STI.getFeatureBits() & Mips::FeatureMips32r6);
   }
@@ -3605,9 +3618,13 @@ bool MipsAsmParser::parseSetArchDirective() {
           .Case("mips5", "mips5")
           .Case("mips32", "mips32")
           .Case("mips32r2", "mips32r2")
+          .Case("mips32r3", "mips32r3")
+          .Case("mips32r5", "mips32r5")
           .Case("mips32r6", "mips32r6")
           .Case("mips64", "mips64")
           .Case("mips64r2", "mips64r2")
+          .Case("mips64r3", "mips64r3")
+          .Case("mips64r5", "mips64r5")
           .Case("mips64r6", "mips64r6")
           .Case("cnmips", "cnmips")
           .Case("r4000", "mips3") // This is an implementation of Mips3.
@@ -3665,6 +3682,14 @@ bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
     selectArch("mips32r2");
     getTargetStreamer().emitDirectiveSetMips32R2();
     break;
+  case Mips::FeatureMips32r3:
+    selectArch("mips32r3");
+    getTargetStreamer().emitDirectiveSetMips32R3();
+    break;
+  case Mips::FeatureMips32r5:
+    selectArch("mips32r5");
+    getTargetStreamer().emitDirectiveSetMips32R5();
+    break;
   case Mips::FeatureMips32r6:
     selectArch("mips32r6");
     getTargetStreamer().emitDirectiveSetMips32R6();
@@ -3677,6 +3702,14 @@ bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
     selectArch("mips64r2");
     getTargetStreamer().emitDirectiveSetMips64R2();
     break;
+  case Mips::FeatureMips64r3:
+    selectArch("mips64r3");
+    getTargetStreamer().emitDirectiveSetMips64R3();
+    break;
+  case Mips::FeatureMips64r5:
+    selectArch("mips64r5");
+    getTargetStreamer().emitDirectiveSetMips64R5();
+    break;
   case Mips::FeatureMips64r6:
     selectArch("mips64r6");
     getTargetStreamer().emitDirectiveSetMips64R6();
@@ -3870,12 +3903,20 @@ bool MipsAsmParser::parseDirectiveSet() {
     return parseSetFeature(Mips::FeatureMips32);
   } else if (Tok.getString() == "mips32r2") {
     return parseSetFeature(Mips::FeatureMips32r2);
+  } else if (Tok.getString() == "mips32r3") {
+    return parseSetFeature(Mips::FeatureMips32r3);
+  } else if (Tok.getString() == "mips32r5") {
+    return parseSetFeature(Mips::FeatureMips32r5);
   } else if (Tok.getString() == "mips32r6") {
     return parseSetFeature(Mips::FeatureMips32r6);
   } else if (Tok.getString() == "mips64") {
     return parseSetFeature(Mips::FeatureMips64);
   } else if (Tok.getString() == "mips64r2") {
     return parseSetFeature(Mips::FeatureMips64r2);
+  } else if (Tok.getString() == "mips64r3") {
+    return parseSetFeature(Mips::FeatureMips64r3);
+  } else if (Tok.getString() == "mips64r5") {
+    return parseSetFeature(Mips::FeatureMips64r5);
   } else if (Tok.getString() == "mips64r6") {
     return parseSetFeature(Mips::FeatureMips64r6);
   } else if (Tok.getString() == "dsp") {
diff --git a/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h b/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h
index 8bcfb0fab9e..473f4f244d0 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h
+++ b/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h
@@ -145,6 +145,10 @@ public:
       ISALevel = 64;
       if (P.hasMips64r6())
         ISARevision = 6;
+      else if (P.hasMips64r5())
+        ISARevision = 5;
+      else if (P.hasMips64r3())
+        ISARevision = 3;
       else if (P.hasMips64r2())
         ISARevision = 2;
       else
@@ -153,6 +157,10 @@ public:
       ISALevel = 32;
       if (P.hasMips32r6())
         ISARevision = 6;
+      else if (P.hasMips32r5())
+        ISARevision = 5;
+      else if (P.hasMips32r3())
+        ISARevision = 3;
       else if (P.hasMips32r2())
         ISARevision = 2;
       else
diff --git a/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
index 6e2849ff862..faf974198ca 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
@@ -75,6 +75,8 @@ MipsABIInfo MipsABIInfo::computeTargetABI(Triple TT, StringRef CPU,
       .Case("mips2", MipsABIInfo::O32())
       .Case("mips32", MipsABIInfo::O32())
       .Case("mips32r2", MipsABIInfo::O32())
+      .Case("mips32r3", MipsABIInfo::O32())
+      .Case("mips32r5", MipsABIInfo::O32())
       .Case("mips32r6", MipsABIInfo::O32())
       .Case("mips16", MipsABIInfo::O32())
       .Case("mips3", MipsABIInfo::N64())
@@ -82,6 +84,8 @@ MipsABIInfo MipsABIInfo::computeTargetABI(Triple TT, StringRef CPU,
       .Case("mips5", MipsABIInfo::N64())
       .Case("mips64", MipsABIInfo::N64())
       .Case("mips64r2", MipsABIInfo::N64())
+      .Case("mips64r3", MipsABIInfo::N64())
+      .Case("mips64r5", MipsABIInfo::N64())
       .Case("mips64r6", MipsABIInfo::N64())
       .Case("octeon", MipsABIInfo::N64())
       .Default(MipsABIInfo::Unknown());
diff --git a/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
index a329234fb21..64d7cab4d7c 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
@@ -70,9 +70,13 @@ void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
+void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
+void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
+void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
+void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetPop() {}
 void MipsTargetStreamer::emitDirectiveSetPush() {}
@@ -231,6 +235,16 @@ void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
   MipsTargetStreamer::emitDirectiveSetMips32R2();
 }
 
+void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
+  OS << "\t.set\tmips32r3\n";
+  MipsTargetStreamer::emitDirectiveSetMips32R3();
+}
+
+void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
+  OS << "\t.set\tmips32r5\n";
+  MipsTargetStreamer::emitDirectiveSetMips32R5();
+}
+
 void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
   OS << "\t.set\tmips32r6\n";
   MipsTargetStreamer::emitDirectiveSetMips32R6();
@@ -246,6 +260,16 @@ void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
   MipsTargetStreamer::emitDirectiveSetMips64R2();
 }
 
+void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
+  OS << "\t.set\tmips64r3\n";
+  MipsTargetStreamer::emitDirectiveSetMips64R3();
+}
+
+void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
+  OS << "\t.set\tmips64r5\n";
+  MipsTargetStreamer::emitDirectiveSetMips64R5();
+}
+
 void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
   OS << "\t.set\tmips64r6\n";
   MipsTargetStreamer::emitDirectiveSetMips64R6();
@@ -366,7 +390,9 @@ MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
   // Architecture
   if (Features & Mips::FeatureMips64r6)
     EFlags |= ELF::EF_MIPS_ARCH_64R6;
-  else if (Features & Mips::FeatureMips64r2)
+  else if (Features & Mips::FeatureMips64r2 ||
+           Features & Mips::FeatureMips64r3 ||
+           Features & Mips::FeatureMips64r5)
     EFlags |= ELF::EF_MIPS_ARCH_64R2;
   else if (Features & Mips::FeatureMips64)
     EFlags |= ELF::EF_MIPS_ARCH_64;
@@ -378,7 +404,9 @@ MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
     EFlags |= ELF::EF_MIPS_ARCH_3;
   else if (Features & Mips::FeatureMips32r6)
     EFlags |= ELF::EF_MIPS_ARCH_32R6;
-  else if (Features & Mips::FeatureMips32r2)
+  else if (Features & Mips::FeatureMips32r2 ||
+           Features & Mips::FeatureMips32r3 ||
+           Features & Mips::FeatureMips32r5)
     EFlags |= ELF::EF_MIPS_ARCH_32R2;
   else if (Features & Mips::FeatureMips32)
     EFlags |= ELF::EF_MIPS_ARCH_32;
diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td
index 1db59c40133..01c548eb80e 100644
--- a/lib/Target/Mips/Mips.td
+++ b/lib/Target/Mips/Mips.td
@@ -114,10 +114,16 @@ def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
                                 "Mips32r2", "Mips32r2 ISA Support",
                                 [FeatureMips3_32r2, FeatureMips4_32r2,
                                  FeatureMips5_32r2, FeatureMips32]>;
+def FeatureMips32r3    : SubtargetFeature<"mips32r3", "MipsArchVersion",
+                                "Mips32r3", "Mips32r3 ISA Support",
+                                [FeatureMips32r2]>;
+def FeatureMips32r5    : SubtargetFeature<"mips32r5", "MipsArchVersion",
+                                "Mips32r5", "Mips32r5 ISA Support",
+                                [FeatureMips32r3]>;
 def FeatureMips32r6    : SubtargetFeature<"mips32r6", "MipsArchVersion",
                                 "Mips32r6",
                                 "Mips32r6 ISA Support [experimental]",
-                                [FeatureMips32r2, FeatureFP64Bit,
+                                [FeatureMips32r5, FeatureFP64Bit,
                                  FeatureNaN2008]>;
 def FeatureMips64      : SubtargetFeature<"mips64", "MipsArchVersion",
                                 "Mips64", "Mips64 ISA Support",
@@ -125,10 +131,16 @@ def FeatureMips64      : SubtargetFeature<"mips64", "MipsArchVersion",
 def FeatureMips64r2    : SubtargetFeature<"mips64r2", "MipsArchVersion",
                                 "Mips64r2", "Mips64r2 ISA Support",
                                 [FeatureMips64, FeatureMips32r2]>;
+def FeatureMips64r3    : SubtargetFeature<"mips64r3", "MipsArchVersion",
+                                "Mips64r3", "Mips64r3 ISA Support",
+                                [FeatureMips64r2, FeatureMips32r3]>;
+def FeatureMips64r5    : SubtargetFeature<"mips64r5", "MipsArchVersion",
+                                "Mips64r5", "Mips64r5 ISA Support",
+                                [FeatureMips64r3, FeatureMips32r5]>;
 def FeatureMips64r6    : SubtargetFeature<"mips64r6", "MipsArchVersion",
                                 "Mips64r6",
                                 "Mips64r6 ISA Support [experimental]",
-                                [FeatureMips32r6, FeatureMips64r2,
+                                [FeatureMips32r6, FeatureMips64r5,
                                  FeatureNaN2008]>;
 
 def FeatureMips16  : SubtargetFeature<"mips16", "InMips16Mode", "true",
@@ -158,6 +170,8 @@ def : Proc<"mips1", [FeatureMips1]>;
 def : Proc<"mips2", [FeatureMips2]>;
 def : Proc<"mips32", [FeatureMips32]>;
 def : Proc<"mips32r2", [FeatureMips32r2]>;
+def : Proc<"mips32r3", [FeatureMips32r3]>;
+def : Proc<"mips32r5", [FeatureMips32r5]>;
 def : Proc<"mips32r6", [FeatureMips32r6]>;
 
 def : Proc<"mips3", [FeatureMips3]>;
@@ -165,6 +179,8 @@ def : Proc<"mips4", [FeatureMips4]>;
 def : Proc<"mips5", [FeatureMips5]>;
 def : Proc<"mips64", [FeatureMips64]>;
 def : Proc<"mips64r2", [FeatureMips64r2]>;
+def : Proc<"mips64r3", [FeatureMips64r3]>;
+def : Proc<"mips64r5", [FeatureMips64r5]>;
 def : Proc<"mips64r6", [FeatureMips64r6]>;
 def : Proc<"mips16", [FeatureMips16]>;
 def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h
index a47a2446638..faded8a3d6c 100644
--- a/lib/Target/Mips/MipsSubtarget.h
+++ b/lib/Target/Mips/MipsSubtarget.h
@@ -38,8 +38,8 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
 
   enum MipsArchEnum {
     MipsDefault,
-    Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips32Max, Mips3, Mips4, Mips5,
-    Mips64, Mips64r2, Mips64r6
+    Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
+    Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
   };
 
   // Mips architecture version
@@ -181,12 +181,22 @@ public:
     return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
            hasMips64r2();
   }
+  bool hasMips32r3() const {
+    return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
+           hasMips64r2();
+  }
+  bool hasMips32r5() const {
+    return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
+           hasMips64r2();
+  }
   bool hasMips32r6() const {
     return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
            hasMips64r6();
   }
   bool hasMips64() const { return MipsArchVersion >= Mips64; }
   bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
+  bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
+  bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
   bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
 
   bool hasCnMips() const { return HasCnMips; }
diff --git a/lib/Target/Mips/MipsTargetStreamer.h b/lib/Target/Mips/MipsTargetStreamer.h
index f3e25cf1055..b3b829623fa 100644
--- a/lib/Target/Mips/MipsTargetStreamer.h
+++ b/lib/Target/Mips/MipsTargetStreamer.h
@@ -59,9 +59,13 @@ public:
   virtual void emitDirectiveSetMips5();
   virtual void emitDirectiveSetMips32();
   virtual void emitDirectiveSetMips32R2();
+  virtual void emitDirectiveSetMips32R3();
+  virtual void emitDirectiveSetMips32R5();
   virtual void emitDirectiveSetMips32R6();
   virtual void emitDirectiveSetMips64();
   virtual void emitDirectiveSetMips64R2();
+  virtual void emitDirectiveSetMips64R3();
+  virtual void emitDirectiveSetMips64R5();
   virtual void emitDirectiveSetMips64R6();
   virtual void emitDirectiveSetDsp();
   virtual void emitDirectiveSetNoDsp();
@@ -170,9 +174,13 @@ public:
   void emitDirectiveSetMips5() override;
   void emitDirectiveSetMips32() override;
   void emitDirectiveSetMips32R2() override;
+  void emitDirectiveSetMips32R3() override;
+  void emitDirectiveSetMips32R5() override;
   void emitDirectiveSetMips32R6() override;
   void emitDirectiveSetMips64() override;
   void emitDirectiveSetMips64R2() override;
+  void emitDirectiveSetMips64R3() override;
+  void emitDirectiveSetMips64R5() override;
   void emitDirectiveSetMips64R6() override;
   void emitDirectiveSetDsp() override;
   void emitDirectiveSetNoDsp() override;
diff --git a/test/CodeGen/Mips/llvm-ir/add.ll b/test/CodeGen/Mips/llvm-ir/add.ll
index 83774eda634..6cccc7df19f 100644
--- a/test/CodeGen/Mips/llvm-ir/add.ll
+++ b/test/CodeGen/Mips/llvm-ir/add.ll
@@ -4,6 +4,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 
diff --git a/test/CodeGen/Mips/llvm-ir/and.ll b/test/CodeGen/Mips/llvm-ir/and.ll
index eec98831bd6..8ebcfe4a3f6 100644
--- a/test/CodeGen/Mips/llvm-ir/and.ll
+++ b/test/CodeGen/Mips/llvm-ir/and.ll
@@ -4,6 +4,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 
diff --git a/test/CodeGen/Mips/llvm-ir/ashr.ll b/test/CodeGen/Mips/llvm-ir/ashr.ll
index 483c6011d89..7e1587c9f4b 100644
--- a/test/CodeGen/Mips/llvm-ir/ashr.ll
+++ b/test/CodeGen/Mips/llvm-ir/ashr.ll
@@ -3,10 +3,16 @@
 ; RUN:    -check-prefix=M2
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R1-R2
+; RUN:    -check-prefix=32R1-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R1-R2
+; RUN:    -check-prefix=32R1-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32 \
+; RUN:    -check-prefix=32R1-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32 \
+; RUN:    -check-prefix=32R1-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 \
 ; RUN:    -check-prefix=32R6
@@ -22,6 +28,12 @@
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64 \
+; RUN:    -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64 \
+; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=64R6
@@ -91,17 +103,17 @@ entry:
   ; M2:         jr        $ra
   ; M2:         nop
 
-  ; 32R1-R2:    srlv      $[[T0:[0-9]+]], $5, $7
-  ; 32R1-R2:    not       $[[T1:[0-9]+]], $7
-  ; 32R1-R2:    sll       $[[T2:[0-9]+]], $4, 1
-  ; 32R1-R2:    sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
-  ; 32R1-R2:    or        $3, $[[T3]], $[[T0]]
-  ; 32R1-R2:    srav      $[[T4:[0-9]+]], $4, $7
-  ; 32R1-R2:    andi      $[[T5:[0-9]+]], $7, 32
-  ; 32R1-R2:    movn      $3, $[[T4]], $[[T5]]
-  ; 32R1-R2:    sra       $4, $4, 31
-  ; 32R1-R2:    jr        $ra
-  ; 32R1-R2:    movn      $2, $4, $[[T5]]
+  ; 32R1-R5:    srlv      $[[T0:[0-9]+]], $5, $7
+  ; 32R1-R5:    not       $[[T1:[0-9]+]], $7
+  ; 32R1-R5:    sll       $[[T2:[0-9]+]], $4, 1
+  ; 32R1-R5:    sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; 32R1-R5:    or        $3, $[[T3]], $[[T0]]
+  ; 32R1-R5:    srav      $[[T4:[0-9]+]], $4, $7
+  ; 32R1-R5:    andi      $[[T5:[0-9]+]], $7, 32
+  ; 32R1-R5:    movn      $3, $[[T4]], $[[T5]]
+  ; 32R1-R5:    sra       $4, $4, 31
+  ; 32R1-R5:    jr        $ra
+  ; 32R1-R5:    movn      $2, $4, $[[T5]]
 
   ; 32R6:       srav      $[[T0:[0-9]+]], $4, $7
   ; 32R6:       andi      $[[T1:[0-9]+]], $7, 32
diff --git a/test/CodeGen/Mips/llvm-ir/call.ll b/test/CodeGen/Mips/llvm-ir/call.ll
index 4cbf43cae28..112ab8ee8c7 100644
--- a/test/CodeGen/Mips/llvm-ir/call.ll
+++ b/test/CodeGen/Mips/llvm-ir/call.ll
@@ -3,10 +3,14 @@
 ; FIXME: We should remove the need for -enable-mips-tail-calls
 ; RUN: llc -march=mips   -mcpu=mips32   -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
 ; RUN: llc -march=mips   -mcpu=mips32r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
+; RUN: llc -march=mips   -mcpu=mips32r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
+; RUN: llc -march=mips   -mcpu=mips32r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
 ; RUN: llc -march=mips   -mcpu=mips32r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
 ; RUN: llc -march=mips64 -mcpu=mips4    -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
 ; RUN: llc -march=mips64 -mcpu=mips64   -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
 ; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
+; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
+; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
 ; RUN: llc -march=mips64 -mcpu=mips64r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
 
 declare void @extern_void_void()
diff --git a/test/CodeGen/Mips/llvm-ir/indirectbr.ll b/test/CodeGen/Mips/llvm-ir/indirectbr.ll
index d8fd7877455..debfeb35b21 100644
--- a/test/CodeGen/Mips/llvm-ir/indirectbr.ll
+++ b/test/CodeGen/Mips/llvm-ir/indirectbr.ll
@@ -2,10 +2,14 @@
 
 ; RUN: llc -march=mips   -mcpu=mips32   -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
+; RUN: llc -march=mips   -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
+; RUN: llc -march=mips   -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6
 ; RUN: llc -march=mips64 -mcpu=mips4    -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64   -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
+; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
+; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6
 
 define i32 @br(i8 *%addr) {
diff --git a/test/CodeGen/Mips/llvm-ir/lshr.ll b/test/CodeGen/Mips/llvm-ir/lshr.ll
index 9336f0a5349..7344d950cad 100644
--- a/test/CodeGen/Mips/llvm-ir/lshr.ll
+++ b/test/CodeGen/Mips/llvm-ir/lshr.ll
@@ -3,10 +3,16 @@
 ; RUN:    -check-prefix=M2
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R1-R2
+; RUN:    -check-prefix=32R1-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R1-R2
+; RUN:    -check-prefix=32R1-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32 \
+; RUN:    -check-prefix=32R1-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32 \
+; RUN:    -check-prefix=32R1-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 \
 ; RUN:    -check-prefix=32R6
@@ -22,6 +28,12 @@
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64 \
+; RUN:    -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64 \
+; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=64R6
@@ -89,16 +101,16 @@ entry:
   ; M2:         jr        $ra
   ; M2:         nop
 
-  ; 32R1-R2:    srlv      $[[T0:[0-9]+]], $5, $7
-  ; 32R1-R2:    not       $[[T1:[0-9]+]], $7
-  ; 32R1-R2:    sll       $[[T2:[0-9]+]], $4, 1
-  ; 32R1-R2:    sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
-  ; 32R1-R2:    or        $3, $[[T3]], $[[T0]]
-  ; 32R1-R2:    srlv      $[[T4:[0-9]+]], $4, $7
-  ; 32R1-R2:    andi      $[[T5:[0-9]+]], $7, 32
-  ; 32R1-R2:    movn      $3, $[[T4]], $[[T5]]
-  ; 32R1-R2:    jr        $ra
-  ; 32R1-R2:    movn      $2, $zero, $[[T5]]
+  ; 32R1-R5:    srlv      $[[T0:[0-9]+]], $5, $7
+  ; 32R1-R5:    not       $[[T1:[0-9]+]], $7
+  ; 32R1-R5:    sll       $[[T2:[0-9]+]], $4, 1
+  ; 32R1-R5:    sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; 32R1-R5:    or        $3, $[[T3]], $[[T0]]
+  ; 32R1-R5:    srlv      $[[T4:[0-9]+]], $4, $7
+  ; 32R1-R5:    andi      $[[T5:[0-9]+]], $7, 32
+  ; 32R1-R5:    movn      $3, $[[T4]], $[[T5]]
+  ; 32R1-R5:    jr        $ra
+  ; 32R1-R5:    movn      $2, $zero, $[[T5]]
 
   ; 32R6:       srlv      $[[T0:[0-9]+]], $5, $7
   ; 32R6:       not       $[[T1:[0-9]+]], $7
diff --git a/test/CodeGen/Mips/llvm-ir/mul.ll b/test/CodeGen/Mips/llvm-ir/mul.ll
index 5f7f338c778..a7582805dd7 100644
--- a/test/CodeGen/Mips/llvm-ir/mul.ll
+++ b/test/CodeGen/Mips/llvm-ir/mul.ll
@@ -1,17 +1,25 @@
 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=M2 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL \
-; RUN:    -check-prefix=32R1-R2 -check-prefix=GP32
+; RUN:    -check-prefix=32R1-R5 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL \
-; RUN:    -check-prefix=32R1-R2 -check-prefix=32R2 -check-prefix=GP32
+; RUN:    -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=32R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=M4 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL \
-; RUN:    -check-prefix=64R1-R2 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL \
-; RUN:    -check-prefix=64R1-R2 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=64R6
 
@@ -24,9 +32,9 @@ entry:
   ; M2:         sll     $[[T0]], $[[T0]], 31
   ; M2:         sra     $2, $[[T0]], 31
 
-  ; 32R1-R2:    mul     $[[T0:[0-9]+]], $4, $5
-  ; 32R1-R2:    sll     $[[T0]], $[[T0]], 31
-  ; 32R1-R2:    sra     $2, $[[T0]], 31
+  ; 32R1-R5:    mul     $[[T0:[0-9]+]], $4, $5
+  ; 32R1-R5:    sll     $[[T0]], $[[T0]], 31
+  ; 32R1-R5:    sra     $2, $[[T0]], 31
 
   ; 32R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 32R6:       sll     $[[T0]], $[[T0]], 31
@@ -37,9 +45,9 @@ entry:
   ; M4:         sll     $[[T0]], $[[T0]], 31
   ; M4:         sra     $2, $[[T0]], 31
 
-  ; 64R1-R2:    mul     $[[T0:[0-9]+]], $4, $5
-  ; 64R1-R2:    sll     $[[T0]], $[[T0]], 31
-  ; 64R1-R2:    sra     $2, $[[T0]], 31
+  ; 64R1-R5:    mul     $[[T0:[0-9]+]], $4, $5
+  ; 64R1-R5:    sll     $[[T0]], $[[T0]], 31
+  ; 64R1-R5:    sra     $2, $[[T0]], 31
 
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R6:       sll     $[[T0]], $[[T0]], 31
@@ -62,8 +70,8 @@ entry:
   ; 32R1:       sll     $[[T0]], $[[T0]], 24
   ; 32R1:       sra     $2, $[[T0]], 24
 
-  ; 32R2:       mul     $[[T0:[0-9]+]], $4, $5
-  ; 32R2:       seb     $2, $[[T0]]
+  ; 32R2-R5:    mul     $[[T0:[0-9]+]], $4, $5
+  ; 32R2-R5:    seb     $2, $[[T0]]
 
   ; 32R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 32R6:       seb     $2, $[[T0]]
@@ -99,8 +107,8 @@ entry:
   ; 32R1:       sll     $[[T0]], $[[T0]], 16
   ; 32R1:       sra     $2, $[[T0]], 16
 
-  ; 32R2:       mul     $[[T0:[0-9]+]], $4, $5
-  ; 32R2:       seh     $2, $[[T0]]
+  ; 32R2-R5:    mul     $[[T0:[0-9]+]], $4, $5
+  ; 32R2-R5:    seh     $2, $[[T0]]
 
   ; 32R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 32R6:       seh     $2, $[[T0]]
@@ -130,10 +138,10 @@ entry:
   ; M2:         mult    $4, $5
   ; M2:         mflo    $2
 
-  ; 32R1-R2:    mul     $2, $4, $5
+  ; 32R1-R5:    mul     $2, $4, $5
   ; 32R6:       mul     $2, $4, $5
 
-  ; 64R1-R2:    mul     $2, $4, $5
+  ; 64R1-R5:    mul     $2, $4, $5
   ; 64R6:       mul     $2, $4, $5
   %r = mul i32 %a, %b
   ret i32 %r
@@ -153,13 +161,13 @@ entry:
   ; M2:         addu    $[[T2:[0-9]+]], $4, $[[T1]]
   ; M2:         addu    $2, $[[T2]], $[[T0]]
 
-  ; 32R1-R2:    multu   $5, $7
-  ; 32R1-R2:    mflo    $3
-  ; 32R1-R2:    mfhi    $[[T0:[0-9]+]]
-  ; 32R1-R2:    mul     $[[T1:[0-9]+]], $4, $7
-  ; 32R1-R2:    mul     $[[T2:[0-9]+]], $5, $6
-  ; 32R1-R2:    addu    $[[T0]], $[[T0]], $[[T2:[0-9]+]]
-  ; 32R1-R2:    addu    $2, $[[T0]], $[[T1]]
+  ; 32R1-R5:    multu   $5, $7
+  ; 32R1-R5:    mflo    $3
+  ; 32R1-R5:    mfhi    $[[T0:[0-9]+]]
+  ; 32R1-R5:    mul     $[[T1:[0-9]+]], $4, $7
+  ; 32R1-R5:    mul     $[[T2:[0-9]+]], $5, $6
+  ; 32R1-R5:    addu    $[[T0]], $[[T0]], $[[T2:[0-9]+]]
+  ; 32R1-R5:    addu    $2, $[[T0]], $[[T1]]
 
   ; 32R6:       mul     $[[T0:[0-9]+]], $5, $6
   ; 32R6:       muhu    $[[T1:[0-9]+]], $5, $7
@@ -171,8 +179,8 @@ entry:
   ; M4:         dmult   $4, $5
   ; M4:         mflo    $2
 
-  ; 64R1-R2:    dmult   $4, $5
-  ; 64R1-R2:    mflo    $2
+  ; 64R1-R5:    dmult   $4, $5
+  ; 64R1-R5:    mflo    $2
 
   ; 64R6:       dmul    $2, $4, $5
 
diff --git a/test/CodeGen/Mips/llvm-ir/or.ll b/test/CodeGen/Mips/llvm-ir/or.ll
index 910f769ab5a..6215e403632 100644
--- a/test/CodeGen/Mips/llvm-ir/or.ll
+++ b/test/CodeGen/Mips/llvm-ir/or.ll
@@ -4,6 +4,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 
diff --git a/test/CodeGen/Mips/llvm-ir/ret.ll b/test/CodeGen/Mips/llvm-ir/ret.ll
index 8f5b1159760..0561c24219c 100644
--- a/test/CodeGen/Mips/llvm-ir/ret.ll
+++ b/test/CodeGen/Mips/llvm-ir/ret.ll
@@ -9,10 +9,14 @@
 
 ; RUN: llc -march=mips   -mcpu=mips32   -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-MTHC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips   -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips   -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips   -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6
 ; RUN: llc -march=mips64 -mcpu=mips4    -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64   -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=R6
 
 define void @ret_void() {
diff --git a/test/CodeGen/Mips/llvm-ir/sdiv.ll b/test/CodeGen/Mips/llvm-ir/sdiv.ll
index 54b7f70b1da..929ee88bb7f 100644
--- a/test/CodeGen/Mips/llvm-ir/sdiv.ll
+++ b/test/CodeGen/Mips/llvm-ir/sdiv.ll
@@ -3,7 +3,11 @@
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=R2 -check-prefix=GP32
+; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -13,7 +17,11 @@
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=R2 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=R6 -check-prefix=64R6
 
@@ -49,11 +57,11 @@ entry:
   ; NOT-R2-R6:    sll     $[[T1:[0-9]+]], $[[T0]], 24
   ; NOT-R2-R6:    sra     $2, $[[T1]], 24
 
-  ; R2:           div     $zero, $4, $5
-  ; R2:           teq     $5, $zero, 7
-  ; R2:           mflo    $[[T0:[0-9]+]]
+  ; R2-R5:        div     $zero, $4, $5
+  ; R2-R5:        teq     $5, $zero, 7
+  ; R2-R5:        mflo    $[[T0:[0-9]+]]
   ; FIXME: This instruction is redundant.
-  ; R2:           seb     $2, $[[T0]]
+  ; R2-R5:        seb     $2, $[[T0]]
 
   ; R6:           div     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
@@ -75,11 +83,11 @@ entry:
   ; NOT-R2-R6:    sll     $[[T1:[0-9]+]], $[[T0]], 16
   ; NOT-R2-R6:    sra     $2, $[[T1]], 16
 
-  ; R2:           div     $zero, $4, $5
-  ; R2:           teq     $5, $zero, 7
-  ; R2:           mflo    $[[T0:[0-9]+]]
+  ; R2-R5:        div     $zero, $4, $5
+  ; R2-R5:        teq     $5, $zero, 7
+  ; R2-R5:        mflo    $[[T0:[0-9]+]]
   ; FIXME: This is instruction is redundant since div is signed.
-  ; R2:           seh     $2, $[[T0]]
+  ; R2-R5:        seh     $2, $[[T0]]
 
   ; R6:           div     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
diff --git a/test/CodeGen/Mips/llvm-ir/select.ll b/test/CodeGen/Mips/llvm-ir/select.ll
index 736bc579088..f17670adca3 100644
--- a/test/CodeGen/Mips/llvm-ir/select.ll
+++ b/test/CodeGen/Mips/llvm-ir/select.ll
@@ -5,7 +5,13 @@
 ; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV \
-; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2
+; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=CMOV \
+; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=CMOV \
+; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -16,6 +22,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
 
@@ -232,12 +242,12 @@ entry:
   ; M2:         jr      $ra
   ; M2:         mtc1    $6, $f1
 
-  ; CMOV-32:    mtc1    $7, $[[F0:f[0-9]+]]
-  ; CMOV-32R1:  mtc1    $6, $f{{[0-9]+}}
-  ; CMOV-32R2   mthc1   $6, $[[F0]]
-  ; CMOV-32:    andi    $[[T0:[0-9]+]], $4, 1
-  ; CMOV-32:    ldc1    $f0, 16($sp)
-  ; CMOV-32:    movn.d  $f0, $[[F0]], $[[T0]]
+  ; CMOV-32:      mtc1    $7, $[[F0:f[0-9]+]]
+  ; CMOV-32R1:    mtc1    $6, $f{{[0-9]+}}
+  ; CMOV-32R2-R5: mthc1   $6, $[[F0]]
+  ; CMOV-32:      andi    $[[T0:[0-9]+]], $4, 1
+  ; CMOV-32:      ldc1    $f0, 16($sp)
+  ; CMOV-32:      movn.d  $f0, $[[F0]], $[[T0]]
 
   ; SEL-32:     mtc1    $7, $[[F0:f[0-9]+]]
   ; SEL-32:     mthc1   $6, $[[F0]]
diff --git a/test/CodeGen/Mips/llvm-ir/shl.ll b/test/CodeGen/Mips/llvm-ir/shl.ll
index 072b44aa2a5..664032005e6 100644
--- a/test/CodeGen/Mips/llvm-ir/shl.ll
+++ b/test/CodeGen/Mips/llvm-ir/shl.ll
@@ -3,10 +3,16 @@
 ; RUN:    -check-prefix=M2 -check-prefix=NOT-R2-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \
-; RUN:    -check-prefix=32R1-R2
+; RUN:    -check-prefix=32R1-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R1-R2 -check-prefix=R2-R6
+; RUN:    -check-prefix=32R1-R5 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32 \
+; RUN:    -check-prefix=32R1-R5 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32 \
+; RUN:    -check-prefix=32R1-R5 -check-prefix=R2-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32 \
 ; RUN:    -check-prefix=32R6 -check-prefix=R2-R6
@@ -22,6 +28,12 @@
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64 \
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64 \
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=64R6 -check-prefix=R2-R6
@@ -101,16 +113,16 @@ entry:
   ; M2:         jr        $ra
   ; M2:         nop
 
-  ; 32R1-R2:    sllv      $[[T0:[0-9]+]], $4, $7
-  ; 32R1-R2:    not       $[[T1:[0-9]+]], $7
-  ; 32R1-R2:    srl       $[[T2:[0-9]+]], $5, 1
-  ; 32R1-R2:    srlv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
-  ; 32R1-R2:    or        $2, $[[T0]], $[[T3]]
-  ; 32R1-R2:    sllv      $[[T4:[0-9]+]], $5, $7
-  ; 32R1-R2:    andi      $[[T5:[0-9]+]], $7, 32
-  ; 32R1-R2:    movn      $2, $[[T4]], $[[T5]]
-  ; 32R1-R2:    jr        $ra
-  ; 32R1-R2:    movn      $3, $zero, $[[T5]]
+  ; 32R1-R5:    sllv      $[[T0:[0-9]+]], $4, $7
+  ; 32R1-R5:    not       $[[T1:[0-9]+]], $7
+  ; 32R1-R5:    srl       $[[T2:[0-9]+]], $5, 1
+  ; 32R1-R5:    srlv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; 32R1-R5:    or        $2, $[[T0]], $[[T3]]
+  ; 32R1-R5:    sllv      $[[T4:[0-9]+]], $5, $7
+  ; 32R1-R5:    andi      $[[T5:[0-9]+]], $7, 32
+  ; 32R1-R5:    movn      $2, $[[T4]], $[[T5]]
+  ; 32R1-R5:    jr        $ra
+  ; 32R1-R5:    movn      $3, $zero, $[[T5]]
 
   ; 32R6:       sllv      $[[T0:[0-9]+]], $4, $7
   ; 32R6:       not       $[[T1:[0-9]+]], $7
diff --git a/test/CodeGen/Mips/llvm-ir/srem.ll b/test/CodeGen/Mips/llvm-ir/srem.ll
index 1e949d24678..ceb53ee7033 100644
--- a/test/CodeGen/Mips/llvm-ir/srem.ll
+++ b/test/CodeGen/Mips/llvm-ir/srem.ll
@@ -3,7 +3,11 @@
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
 ; RUN:  -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \
-; RUN:  -check-prefix=R2 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:   -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -13,7 +17,13 @@
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
 ; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN:  -check-prefix=R2 -check-prefix=R2-R6 \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
+; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
+; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
 ; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:  -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6
@@ -47,10 +57,10 @@ entry:
   ; NOT-R2-R6:    sll     $[[T1:[0-9]+]], $[[T0]], 24
   ; NOT-R2-R6:    sra     $2, $[[T1]], 24
 
-  ; R2:           div     $zero, $4, $5
-  ; R2:           teq     $5, $zero, 7
-  ; R2:           mfhi    $[[T0:[0-9]+]]
-  ; R2:           seb     $2, $[[T0]]
+  ; R2-R5:        div     $zero, $4, $5
+  ; R2-R5:        teq     $5, $zero, 7
+  ; R2-R5:        mfhi    $[[T0:[0-9]+]]
+  ; R2-R5:        seb     $2, $[[T0]]
 
   ; R6:           mod     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
@@ -70,10 +80,10 @@ entry:
   ; NOT-R2-R6:    sll     $[[T1:[0-9]+]], $[[T0]], 16
   ; NOT-R2-R6:    sra     $2, $[[T1]], 16
 
-  ; R2:           div     $zero, $4, $5
-  ; R2:           teq     $5, $zero, 7
-  ; R2:           mfhi    $[[T0:[0-9]+]]
-  ; R2:           seh     $2, $[[T1]]
+  ; R2-R5:        div     $zero, $4, $5
+  ; R2-R5:        teq     $5, $zero, 7
+  ; R2-R5:        mfhi    $[[T0:[0-9]+]]
+  ; R2-R5:        seh     $2, $[[T1]]
 
   ; R6:           mod     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
diff --git a/test/CodeGen/Mips/llvm-ir/sub.ll b/test/CodeGen/Mips/llvm-ir/sub.ll
index 6d592be3821..164975844d7 100644
--- a/test/CodeGen/Mips/llvm-ir/sub.ll
+++ b/test/CodeGen/Mips/llvm-ir/sub.ll
@@ -4,6 +4,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 
diff --git a/test/CodeGen/Mips/llvm-ir/udiv.ll b/test/CodeGen/Mips/llvm-ir/udiv.ll
index 1f7aa0d5f4c..a7cafe52d1a 100644
--- a/test/CodeGen/Mips/llvm-ir/udiv.ll
+++ b/test/CodeGen/Mips/llvm-ir/udiv.ll
@@ -4,6 +4,10 @@
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=NOT-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=NOT-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=R6 -check-prefix=64R6
 
diff --git a/test/CodeGen/Mips/llvm-ir/urem.ll b/test/CodeGen/Mips/llvm-ir/urem.ll
index 73235341a42..d5a231c8dfc 100644
--- a/test/CodeGen/Mips/llvm-ir/urem.ll
+++ b/test/CodeGen/Mips/llvm-ir/urem.ll
@@ -3,7 +3,11 @@
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
 ; RUN:  -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \
-; RUN:  -check-prefix=R2 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:   -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -13,7 +17,13 @@
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
 ; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN:  -check-prefix=R2 -check-prefix=R2-R6 \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
+; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
+; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
 ; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:  -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6
@@ -53,12 +63,12 @@ entry:
   ; NOT-R2-R6:    sll     $[[T3:[0-9]+]], $[[T2]], 24
   ; NOT-R2-R6:    sra     $2, $[[T3]], 24
 
-  ; R2:           andi    $[[T0:[0-9]+]], $5, 255
-  ; R2:           andi    $[[T1:[0-9]+]], $4, 255
-  ; R2:           divu    $zero, $[[T1]], $[[T0]]
-  ; R2:           teq     $[[T0]], $zero, 7
-  ; R2:           mfhi    $[[T2:[0-9]+]]
-  ; R2:           seb     $2, $[[T2]]
+  ; R2-R5:        andi    $[[T0:[0-9]+]], $5, 255
+  ; R2-R5:        andi    $[[T1:[0-9]+]], $4, 255
+  ; R2-R5:        divu    $zero, $[[T1]], $[[T0]]
+  ; R2-R5:        teq     $[[T0]], $zero, 7
+  ; R2-R5:        mfhi    $[[T2:[0-9]+]]
+  ; R2-R5:        seb     $2, $[[T2]]
 
   ; R6:           andi    $[[T0:[0-9]+]], $5, 255
   ; R6:           andi    $[[T1:[0-9]+]], $4, 255
@@ -82,12 +92,12 @@ entry:
   ; NOT-R2-R6:    sll     $[[T3:[0-9]+]], $[[T2]], 16
   ; NOT-R2-R6:    sra     $2, $[[T3]], 16
 
-  ; R2:           andi    $[[T0:[0-9]+]], $5, 65535
-  ; R2:           andi    $[[T1:[0-9]+]], $4, 65535
-  ; R2:           divu    $zero, $[[T1]], $[[T0]]
-  ; R2:           teq     $[[T0]], $zero, 7
-  ; R2:           mfhi    $[[T3:[0-9]+]]
-  ; R2:           seh     $2, $[[T2]]
+  ; R2-R5:        andi    $[[T0:[0-9]+]], $5, 65535
+  ; R2-R5:        andi    $[[T1:[0-9]+]], $4, 65535
+  ; R2-R5:        divu    $zero, $[[T1]], $[[T0]]
+  ; R2-R5:        teq     $[[T0]], $zero, 7
+  ; R2-R5:        mfhi    $[[T3:[0-9]+]]
+  ; R2-R5:        seh     $2, $[[T2]]
 
   ; R6:           andi    $[[T0:[0-9]+]], $5, 65535
   ; R6:           andi    $[[T1:[0-9]+]], $4, 65535
diff --git a/test/CodeGen/Mips/llvm-ir/xor.ll b/test/CodeGen/Mips/llvm-ir/xor.ll
index 83107e32432..89af99981a3 100644
--- a/test/CodeGen/Mips/llvm-ir/xor.ll
+++ b/test/CodeGen/Mips/llvm-ir/xor.ll
@@ -4,6 +4,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 
diff --git a/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-le.txt b/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-le.txt
new file mode 100644
index 00000000000..1909e2a2127
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-le.txt
@@ -0,0 +1,169 @@
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r3 | FileCheck %s
+0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
+0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
+0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
+0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
+0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
+0x67 0x45 0xc9 0x20 # CHECK: addi $9, $6, 17767
+0x67 0xc5 0xc9 0x24 # CHECK: addiu $9, $6, -15001
+0x21 0x48 0xc7 0x00 # CHECK: addu $9, $6, $7
+0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
+0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
+0x4c 0x01 0x00 0x10 # CHECK: b 1332
+0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
+0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
+0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
+0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
+0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
+0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
+0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
+0x4c 0x01 0xc0 0x1c # CHECK: bgtz $6, 1332
+0x4c 0x01 0xc0 0x18 # CHECK: blez $6, 1332
+0x4c 0x01 0x26 0x15 # CHECK: bne $9, $6, 1332
+0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
+0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
+0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
+0x30 0x30 0x07 0x46 # CHECK: c.f.s $f6, $f7
+0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
+0x3e 0x30 0x07 0x46 # CHECK: c.le.s $f6, $f7
+0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
+0x3c 0x30 0x07 0x46 # CHECK: c.lt.s $f6, $f7
+0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
+0x3d 0x30 0x07 0x46 # CHECK: c.nge.s $f6, $f7
+0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
+0x3b 0x30 0x07 0x46 # CHECK: c.ngl.s $f6, $f7
+0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
+0x39 0x30 0x07 0x46 # CHECK: c.ngle.s $f6, $f7
+0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
+0x3f 0x30 0x07 0x46 # CHECK: c.ngt.s $f6, $f7
+0x36 0x60 0x2e 0x46 # CHECK: c.ole.d $f12, $f14
+0x36 0x30 0x07 0x46 # CHECK: c.ole.s $f6, $f7
+0x34 0x60 0x2e 0x46 # CHECK: c.olt.d $f12, $f14
+0x34 0x30 0x07 0x46 # CHECK: c.olt.s $f6, $f7
+0x3a 0x60 0x2e 0x46 # CHECK: c.seq.d $f12, $f14
+0x3a 0x30 0x07 0x46 # CHECK: c.seq.s $f6, $f7
+0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
+0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
+0x33 0x60 0x2e 0x46 # CHECK: c.ueq.d $f12, $f14
+0x33 0xe0 0x12 0x46 # CHECK: c.ueq.s $f28, $f18
+0x37 0x60 0x2e 0x46 # CHECK: c.ule.d $f12, $f14
+0x37 0x30 0x07 0x46 # CHECK: c.ule.s $f6, $f7
+0x35 0x60 0x2e 0x46 # CHECK: c.ult.d $f12, $f14
+0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7
+0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14
+0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7
+0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14
+0x8e 0x39 0x00 0x46 # CHECK: ceil.w.s $f6, $f7
+0x00 0x38 0x46 0x44 # CHECK: cfc1 $6, $7
+0x21 0x30 0xe6 0x70 # CHECK: clo $6, $7
+0x20 0x30 0xe6 0x70 # CHECK: clz $6, $7
+0x00 0x38 0xc6 0x44 # CHECK: ctc1 $6, $7
+0xa1 0x39 0x00 0x46 # CHECK: cvt.d.s $f6, $f7
+0x21 0x73 0x80 0x46 # CHECK: cvt.d.w $f12, $f14
+0x25 0x73 0x20 0x46 # CHECK: cvt.l.d $f12, $f14
+0xa5 0x39 0x00 0x46 # CHECK: cvt.l.s $f6, $f7
+0x20 0x73 0x20 0x46 # CHECK: cvt.s.d $f12, $f14
+0xa0 0x39 0x80 0x46 # CHECK: cvt.s.w $f6, $f7
+0x24 0x73 0x20 0x46 # CHECK: cvt.w.d $f12, $f14
+0xa4 0x39 0x00 0x46 # CHECK: cvt.w.s $f6, $f7
+0x00 0x60 0x7e 0x41 # CHECK: di $fp
+0x00 0x60 0x60 0x41 # CHECK: di
+0x20 0x60 0x6e 0x41 # CHECK: ei $14
+0x20 0x60 0x60 0x41 # CHECK: ei
+0x0f 0x73 0x20 0x46 # CHECK: floor.w.d $f12, $f14
+0x8f 0x39 0x00 0x46 # CHECK: floor.w.s $f6, $f7
+0x84 0x61 0x33 0x7d # CHECK: ins $19, $9, 6, 7
+0x4c 0x01 0x00 0x08 # CHECK: j 1328
+0x4c 0x01 0x00 0x0c # CHECK: jal 1328
+0x4c 0x01 0x00 0x74 # CHECK: jalx 1328
+0x09 0xf8 0xe0 0x00 # CHECK: jalr $7
+0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
+0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
+0x08 0x00 0xe0 0x00 # CHECK: jr $7
+0xc6 0x23 0xa4 0x80 # CHECK: lb $4, 9158($5)
+0x06 0x00 0xa4 0x90 # CHECK: lbu $4, 6($5)
+0xc6 0x23 0xe9 0xd4 # CHECK: ldc1 $f9, 9158($7)
+0x01 0x02 0xf7 0x4d # CHECK: ldxc1 $f8, $23($15)
+0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
+0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
+0xc6 0x23 0xe9 0xc0 # CHECK: ll $9, 9158($7)
+0x67 0x45 0x06 0x3c # CHECK: lui $6, 17767
+0x05 0x00 0xa6 0x4c # CHECK: luxc1 $f0, $6($5)
+0x18 0x00 0xa4 0x8c # CHECK: lw $4, 24($5)
+0xc6 0x23 0xe9 0xc4 # CHECK: lwc1 $f9, 9158($7)
+0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
+0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
+0x00 0x05 0xcc 0x4d # CHECK: lwxc1 $f20, $12($14)
+0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
+0xa1 0xd4 0x94 0x4e # CHECK: madd.d $f18, $f20, $f26, $f20
+0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
+0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
+0x10 0x28 0x00 0x00 # CHECK: mfhi $5
+0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
+0x12 0x28 0x00 0x00 # CHECK: mflo $5
+0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
+0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
+0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
+0xa9 0xf2 0x52 0x4c # CHECK: msub.d $f10, $f2, $f30, $f18
+0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
+0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
+0x11 0x00 0xe0 0x00 # CHECK: mthi $7
+0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
+0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
+0x02 0x62 0x2e 0x46 # CHECK: mul.d $f8, $f12, $f14
+0x42 0x32 0x07 0x46 # CHECK: mul.s $f9, $f6, $f7
+0x02 0x48 0xc7 0x70 # CHECK: mul $9, $6, $7
+0x18 0x00 0x65 0x00 # CHECK: mult $3, $5
+0x19 0x00 0x65 0x00 # CHECK: multu $3, $5
+0x07 0x73 0x20 0x46 # CHECK: neg.d $f12, $f14
+0x87 0x39 0x00 0x46 # CHECK: neg.s $f6, $f7
+0xb1 0x74 0x54 0x4d # CHECK: nmadd.d $f18, $f10, $f14, $f20
+0x30 0xc8 0xac 0x4c # CHECK: nmadd.s $f0, $f5, $f25, $f12
+0x00 0x00 0x00 0x00 # CHECK: nop
+0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7
+0xb9 0x87 0x1e 0x4d # CHECK: nmsub.d $f30, $f8, $f16, $f30
+0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
+0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
+0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
+0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
+0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
+0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
+0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
+0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
+0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
+0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7)
+0x09 0x40 0x24 0x4f # CHECK: sdxc1 $f8, $4($25)
+0x20 0x34 0x07 0x7c # CHECK: seb $6, $7
+0x20 0x36 0x07 0x7c # CHECK: seh $6, $7
+0xc6 0x23 0xa4 0xa4 # CHECK: sh $4, 9158($5)
+0xc0 0x21 0x03 0x00 # CHECK: sll $4, $3, 7
+0x04 0x10 0xa3 0x00 # CHECK: sllv $2, $3, $5
+0x2a 0x18 0x65 0x00 # CHECK: slt $3, $3, $5
+0x67 0x00 0x63 0x28 # CHECK: slti $3, $3, 103
+0x67 0x00 0x63 0x2c # CHECK: sltiu $3, $3, 103
+0x2b 0x18 0x65 0x00 # CHECK: sltu $3, $3, $5
+0x04 0x73 0x20 0x46 # CHECK: sqrt.d $f12, $f14
+0x84 0x39 0x00 0x46 # CHECK: sqrt.s $f6, $f7
+0xc3 0x21 0x03 0x00 # CHECK: sra $4, $3, 7
+0x07 0x10 0xa3 0x00 # CHECK: srav $2, $3, $5
+0xc2 0x21 0x03 0x00 # CHECK: srl $4, $3, 7
+0x06 0x10 0xa3 0x00 # CHECK: srlv $2, $3, $5
+0x01 0x62 0x2e 0x46 # CHECK: sub.d $f8, $f12, $f14
+0x41 0x32 0x07 0x46 # CHECK: sub.s $f9, $f6, $f7
+0x22 0x48 0xc7 0x00 # CHECK: sub $9, $6, $7
+0x23 0x20 0x65 0x00 # CHECK: subu $4, $3, $5
+0x0d 0x20 0xb8 0x4c # CHECK: suxc1 $f4, $24($5)
+0x18 0x00 0xa4 0xac # CHECK: sw $4, 24($5)
+0xc6 0x23 0xe9 0xe4 # CHECK: swc1 $f9, 9158($7)
+0x10 0x00 0xa4 0xa8 # CHECK: swl $4, 16($5)
+0x10 0x00 0xe6 0xb8 # CHECK: swr $6, 16($7)
+0x08 0xd0 0xd2 0x4e # CHECK: swxc1 $f26, $18($22)
+0xcf 0x01 0x00 0x00 # CHECK: sync 7
+0x0d 0x73 0x20 0x46 # CHECK: trunc.w.d $f12, $f14
+0x8d 0x39 0x00 0x46 # CHECK: trunc.w.s $f6, $f7
+0xa0 0x30 0x07 0x7c # CHECK: wsbh $6, $7
+0x26 0x18 0x65 0x00 # CHECK: xor $3, $3, $5
+0x67 0x45 0xc9 0x38 # CHECK: xori $9, $6, 17767
diff --git a/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt b/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
new file mode 100644
index 00000000000..a273c24f9c9
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
@@ -0,0 +1,169 @@
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r3 | FileCheck %s
+0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
+0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7
+0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7
+0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14
+0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7
+0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767
+0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001
+0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7
+0x00 0xc7 0x48 0x24 # CHECK: and $9, $6, $7
+0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767
+0x10 0x00 0x01 0x4c # CHECK: b 1332
+0x45 0x00 0x01 0x4c # CHECK: bc1f 1332
+0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332
+0x45 0x01 0x01 0x4c # CHECK: bc1t 1332
+0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332
+0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332
+0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
+0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
+0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332
+0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332
+0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332
+0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14
+0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7
+0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14
+0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7
+0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14
+0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7
+0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14
+0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7
+0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14
+0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7
+0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14
+0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7
+0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14
+0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7
+0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14
+0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7
+0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14
+0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7
+0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14
+0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7
+0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14
+0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7
+0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14
+0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7
+0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14
+0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18
+0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14
+0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7
+0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14
+0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7
+0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14
+0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7
+0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14
+0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7
+0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7
+0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7
+0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7
+0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7
+0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7
+0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
+0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14
+0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7
+0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14
+0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7
+0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14
+0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7
+0x41 0x7e 0x60 0x00 # CHECK: di $fp
+0x41 0x60 0x60 0x00 # CHECK: di
+0x41 0x6e 0x60 0x20 # CHECK: ei $14
+0x41 0x60 0x60 0x20 # CHECK: ei
+0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14
+0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7
+0x7d 0x33 0x61 0x84 # CHECK: ins $19, $9, 6, 7
+0x08 0x00 0x01 0x4c # CHECK: j 1328
+0x0c 0x00 0x01 0x4c # CHECK: jal 1328
+0x74 0x00 0x01 0x4c # CHECK: jalx 1328
+0x00 0xe0 0xf8 0x09 # CHECK: jalr $7
+0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
+0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
+0x00 0xe0 0x00 0x08 # CHECK: jr $7
+0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5)
+0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5)
+0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7)
+0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15)
+0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5)
+0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5)
+0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7)
+0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767
+0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
+0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5)
+0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7)
+0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4)
+0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
+0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
+0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
+0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
+0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
+0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
+0x00 0x00 0x28 0x10 # CHECK: mfhi $5
+0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
+0x00 0x00 0x28 0x12 # CHECK: mflo $5
+0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
+0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
+0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
+0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
+0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
+0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
+0x00 0xe0 0x00 0x11 # CHECK: mthi $7
+0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
+0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
+0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
+0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
+0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7
+0x00 0x65 0x00 0x18 # CHECK: mult $3, $5
+0x00 0x65 0x00 0x19 # CHECK: multu $3, $5
+0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14
+0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7
+0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
+0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
+0x00 0x00 0x00 0x00 # CHECK: nop
+0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7
+0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
+0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
+0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5
+0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767
+0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7
+0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7
+0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14
+0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7
+0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5)
+0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5)
+0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7)
+0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7)
+0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25)
+0x7c 0x07 0x34 0x20 # CHECK: seb $6, $7
+0x7c 0x07 0x36 0x20 # CHECK: seh $6, $7
+0xa4 0xa4 0x23 0xc6 # CHECK: sh $4, 9158($5)
+0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7
+0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5
+0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5
+0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103
+0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
+0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
+0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14
+0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7
+0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7
+0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5
+0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7
+0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5
+0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14
+0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7
+0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7
+0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5
+0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5)
+0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5)
+0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7)
+0xa8 0xa4 0x00 0x10 # CHECK: swl $4, 16($5)
+0xb8 0xe6 0x00 0x10 # CHECK: swr $6, 16($7)
+0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22)
+0x00 0x00 0x01 0xcf # CHECK: sync 7
+0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14
+0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7
+0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7
+0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5
+0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767
diff --git a/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt b/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt
new file mode 100644
index 00000000000..7623bba364f
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt
@@ -0,0 +1,83 @@
+# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips32r3 | FileCheck %s
+# XFAIL: *
+0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
+0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
+0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
+0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
+0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
+0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
+0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3
+0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
+0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
+0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
+0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
+0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
+0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
+0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
+0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
+0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
+0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
+0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
+0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
+0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
+0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
+0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
+0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
+0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
+0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
+0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
+0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
+0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
+0x46 0xc0 0x45 0x85 # CHECK: abs.ps $f22, $f8
+0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
+0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10
+0x46 0xcc 0x66 0x30 # CHECK: c.f.ps $fcc6, $f12, $f12
+0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20
+0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
+0x46 0xda 0x10 0x3d # CHECK: c.nge.ps $f2, $f26
+0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
+0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20
+0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
+0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8
+0x46 0xd0 0x32 0x34 # CHECK: c.olt.ps $fcc2, $f6, $f16
+0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14
+0x46 0xc6 0x26 0x38 # CHECK: c.sf.ps $fcc6, $f4, $f6
+0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28
+0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2
+0x46 0xc0 0x76 0x35 # CHECK: c.ult.ps $fcc6, $f14, $f0
+0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
+0x46 0x20 0x20 0x8a # CHECK: ceil.l.d $f2, $f4
+0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
+0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
+0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
+0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
+0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
+0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
+0x46 0x20 0x36 0x8b # CHECK: floor.l.d $f26, $f6
+0x46 0x00 0x23 0x0b # CHECK: floor.l.s $f12, $f4
+0x4c 0x42 0x75 0xa6 # CHECK: madd.ps $f22, $f2, $f14, $f2
+0x46 0xc0 0x85 0x86 # CHECK: mov.ps $f22, $f16
+0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6
+0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
+0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
+0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
+0x4d 0xd0 0xe3 0x2e # CHECK: msub.ps $f12, $f14, $f28, $f16
+0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
+0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
+0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
+0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
+0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
+0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
+0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
+0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
+0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
+0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
+0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
+0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
+0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
+0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5
diff --git a/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-le.txt b/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-le.txt
new file mode 100644
index 00000000000..62977dc3266
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-le.txt
@@ -0,0 +1,169 @@
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r5 | FileCheck %s
+0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
+0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
+0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
+0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
+0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
+0x67 0x45 0xc9 0x20 # CHECK: addi $9, $6, 17767
+0x67 0xc5 0xc9 0x24 # CHECK: addiu $9, $6, -15001
+0x21 0x48 0xc7 0x00 # CHECK: addu $9, $6, $7
+0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
+0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
+0x4c 0x01 0x00 0x10 # CHECK: b 1332
+0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
+0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
+0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
+0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
+0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
+0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
+0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
+0x4c 0x01 0xc0 0x1c # CHECK: bgtz $6, 1332
+0x4c 0x01 0xc0 0x18 # CHECK: blez $6, 1332
+0x4c 0x01 0x26 0x15 # CHECK: bne $9, $6, 1332
+0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
+0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
+0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
+0x30 0x30 0x07 0x46 # CHECK: c.f.s $f6, $f7
+0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
+0x3e 0x30 0x07 0x46 # CHECK: c.le.s $f6, $f7
+0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
+0x3c 0x30 0x07 0x46 # CHECK: c.lt.s $f6, $f7
+0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
+0x3d 0x30 0x07 0x46 # CHECK: c.nge.s $f6, $f7
+0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
+0x3b 0x30 0x07 0x46 # CHECK: c.ngl.s $f6, $f7
+0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
+0x39 0x30 0x07 0x46 # CHECK: c.ngle.s $f6, $f7
+0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
+0x3f 0x30 0x07 0x46 # CHECK: c.ngt.s $f6, $f7
+0x36 0x60 0x2e 0x46 # CHECK: c.ole.d $f12, $f14
+0x36 0x30 0x07 0x46 # CHECK: c.ole.s $f6, $f7
+0x34 0x60 0x2e 0x46 # CHECK: c.olt.d $f12, $f14
+0x34 0x30 0x07 0x46 # CHECK: c.olt.s $f6, $f7
+0x3a 0x60 0x2e 0x46 # CHECK: c.seq.d $f12, $f14
+0x3a 0x30 0x07 0x46 # CHECK: c.seq.s $f6, $f7
+0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
+0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
+0x33 0x60 0x2e 0x46 # CHECK: c.ueq.d $f12, $f14
+0x33 0xe0 0x12 0x46 # CHECK: c.ueq.s $f28, $f18
+0x37 0x60 0x2e 0x46 # CHECK: c.ule.d $f12, $f14
+0x37 0x30 0x07 0x46 # CHECK: c.ule.s $f6, $f7
+0x35 0x60 0x2e 0x46 # CHECK: c.ult.d $f12, $f14
+0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7
+0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14
+0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7
+0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14
+0x8e 0x39 0x00 0x46 # CHECK: ceil.w.s $f6, $f7
+0x00 0x38 0x46 0x44 # CHECK: cfc1 $6, $7
+0x21 0x30 0xe6 0x70 # CHECK: clo $6, $7
+0x20 0x30 0xe6 0x70 # CHECK: clz $6, $7
+0x00 0x38 0xc6 0x44 # CHECK: ctc1 $6, $7
+0xa1 0x39 0x00 0x46 # CHECK: cvt.d.s $f6, $f7
+0x21 0x73 0x80 0x46 # CHECK: cvt.d.w $f12, $f14
+0x25 0x73 0x20 0x46 # CHECK: cvt.l.d $f12, $f14
+0xa5 0x39 0x00 0x46 # CHECK: cvt.l.s $f6, $f7
+0x20 0x73 0x20 0x46 # CHECK: cvt.s.d $f12, $f14
+0xa0 0x39 0x80 0x46 # CHECK: cvt.s.w $f6, $f7
+0x24 0x73 0x20 0x46 # CHECK: cvt.w.d $f12, $f14
+0xa4 0x39 0x00 0x46 # CHECK: cvt.w.s $f6, $f7
+0x00 0x60 0x7e 0x41 # CHECK: di $fp
+0x00 0x60 0x60 0x41 # CHECK: di
+0x20 0x60 0x6e 0x41 # CHECK: ei $14
+0x20 0x60 0x60 0x41 # CHECK: ei
+0x0f 0x73 0x20 0x46 # CHECK: floor.w.d $f12, $f14
+0x8f 0x39 0x00 0x46 # CHECK: floor.w.s $f6, $f7
+0x84 0x61 0x33 0x7d # CHECK: ins $19, $9, 6, 7
+0x4c 0x01 0x00 0x08 # CHECK: j 1328
+0x4c 0x01 0x00 0x0c # CHECK: jal 1328
+0x4c 0x01 0x00 0x74 # CHECK: jalx 1328
+0x09 0xf8 0xe0 0x00 # CHECK: jalr $7
+0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
+0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
+0x08 0x00 0xe0 0x00 # CHECK: jr $7
+0xc6 0x23 0xa4 0x80 # CHECK: lb $4, 9158($5)
+0x06 0x00 0xa4 0x90 # CHECK: lbu $4, 6($5)
+0xc6 0x23 0xe9 0xd4 # CHECK: ldc1 $f9, 9158($7)
+0x01 0x02 0xf7 0x4d # CHECK: ldxc1 $f8, $23($15)
+0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
+0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
+0xc6 0x23 0xe9 0xc0 # CHECK: ll $9, 9158($7)
+0x67 0x45 0x06 0x3c # CHECK: lui $6, 17767
+0x05 0x00 0xa6 0x4c # CHECK: luxc1 $f0, $6($5)
+0x18 0x00 0xa4 0x8c # CHECK: lw $4, 24($5)
+0xc6 0x23 0xe9 0xc4 # CHECK: lwc1 $f9, 9158($7)
+0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
+0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
+0x00 0x05 0xcc 0x4d # CHECK: lwxc1 $f20, $12($14)
+0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
+0xa1 0xd4 0x94 0x4e # CHECK: madd.d $f18, $f20, $f26, $f20
+0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
+0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
+0x10 0x28 0x00 0x00 # CHECK: mfhi $5
+0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
+0x12 0x28 0x00 0x00 # CHECK: mflo $5
+0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
+0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
+0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
+0xa9 0xf2 0x52 0x4c # CHECK: msub.d $f10, $f2, $f30, $f18
+0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
+0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
+0x11 0x00 0xe0 0x00 # CHECK: mthi $7
+0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
+0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
+0x02 0x62 0x2e 0x46 # CHECK: mul.d $f8, $f12, $f14
+0x42 0x32 0x07 0x46 # CHECK: mul.s $f9, $f6, $f7
+0x02 0x48 0xc7 0x70 # CHECK: mul $9, $6, $7
+0x18 0x00 0x65 0x00 # CHECK: mult $3, $5
+0x19 0x00 0x65 0x00 # CHECK: multu $3, $5
+0x07 0x73 0x20 0x46 # CHECK: neg.d $f12, $f14
+0x87 0x39 0x00 0x46 # CHECK: neg.s $f6, $f7
+0xb1 0x74 0x54 0x4d # CHECK: nmadd.d $f18, $f10, $f14, $f20
+0x30 0xc8 0xac 0x4c # CHECK: nmadd.s $f0, $f5, $f25, $f12
+0x00 0x00 0x00 0x00 # CHECK: nop
+0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7
+0xb9 0x87 0x1e 0x4d # CHECK: nmsub.d $f30, $f8, $f16, $f30
+0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
+0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
+0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
+0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
+0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
+0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
+0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
+0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
+0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
+0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7)
+0x09 0x40 0x24 0x4f # CHECK: sdxc1 $f8, $4($25)
+0x20 0x34 0x07 0x7c # CHECK: seb $6, $7
+0x20 0x36 0x07 0x7c # CHECK: seh $6, $7
+0xc6 0x23 0xa4 0xa4 # CHECK: sh $4, 9158($5)
+0xc0 0x21 0x03 0x00 # CHECK: sll $4, $3, 7
+0x04 0x10 0xa3 0x00 # CHECK: sllv $2, $3, $5
+0x2a 0x18 0x65 0x00 # CHECK: slt $3, $3, $5
+0x67 0x00 0x63 0x28 # CHECK: slti $3, $3, 103
+0x67 0x00 0x63 0x2c # CHECK: sltiu $3, $3, 103
+0x2b 0x18 0x65 0x00 # CHECK: sltu $3, $3, $5
+0x04 0x73 0x20 0x46 # CHECK: sqrt.d $f12, $f14
+0x84 0x39 0x00 0x46 # CHECK: sqrt.s $f6, $f7
+0xc3 0x21 0x03 0x00 # CHECK: sra $4, $3, 7
+0x07 0x10 0xa3 0x00 # CHECK: srav $2, $3, $5
+0xc2 0x21 0x03 0x00 # CHECK: srl $4, $3, 7
+0x06 0x10 0xa3 0x00 # CHECK: srlv $2, $3, $5
+0x01 0x62 0x2e 0x46 # CHECK: sub.d $f8, $f12, $f14
+0x41 0x32 0x07 0x46 # CHECK: sub.s $f9, $f6, $f7
+0x22 0x48 0xc7 0x00 # CHECK: sub $9, $6, $7
+0x23 0x20 0x65 0x00 # CHECK: subu $4, $3, $5
+0x0d 0x20 0xb8 0x4c # CHECK: suxc1 $f4, $24($5)
+0x18 0x00 0xa4 0xac # CHECK: sw $4, 24($5)
+0xc6 0x23 0xe9 0xe4 # CHECK: swc1 $f9, 9158($7)
+0x10 0x00 0xa4 0xa8 # CHECK: swl $4, 16($5)
+0x10 0x00 0xe6 0xb8 # CHECK: swr $6, 16($7)
+0x08 0xd0 0xd2 0x4e # CHECK: swxc1 $f26, $18($22)
+0xcf 0x01 0x00 0x00 # CHECK: sync 7
+0x0d 0x73 0x20 0x46 # CHECK: trunc.w.d $f12, $f14
+0x8d 0x39 0x00 0x46 # CHECK: trunc.w.s $f6, $f7
+0xa0 0x30 0x07 0x7c # CHECK: wsbh $6, $7
+0x26 0x18 0x65 0x00 # CHECK: xor $3, $3, $5
+0x67 0x45 0xc9 0x38 # CHECK: xori $9, $6, 17767
diff --git a/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt b/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
new file mode 100644
index 00000000000..39c46440946
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
@@ -0,0 +1,169 @@
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r5 | FileCheck %s
+0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
+0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7
+0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7
+0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14
+0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7
+0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767
+0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001
+0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7
+0x00 0xc7 0x48 0x24 # CHECK: and $9, $6, $7
+0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767
+0x10 0x00 0x01 0x4c # CHECK: b 1332
+0x45 0x00 0x01 0x4c # CHECK: bc1f 1332
+0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332
+0x45 0x01 0x01 0x4c # CHECK: bc1t 1332
+0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332
+0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332
+0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
+0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
+0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332
+0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332
+0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332
+0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14
+0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7
+0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14
+0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7
+0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14
+0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7
+0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14
+0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7
+0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14
+0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7
+0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14
+0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7
+0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14
+0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7
+0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14
+0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7
+0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14
+0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7
+0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14
+0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7
+0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14
+0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7
+0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14
+0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7
+0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14
+0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18
+0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14
+0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7
+0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14
+0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7
+0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14
+0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7
+0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14
+0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7
+0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7
+0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7
+0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7
+0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7
+0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7
+0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
+0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14
+0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7
+0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14
+0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7
+0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14
+0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7
+0x41 0x7e 0x60 0x00 # CHECK: di $fp
+0x41 0x60 0x60 0x00 # CHECK: di
+0x41 0x6e 0x60 0x20 # CHECK: ei $14
+0x41 0x60 0x60 0x20 # CHECK: ei
+0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14
+0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7
+0x7d 0x33 0x61 0x84 # CHECK: ins $19, $9, 6, 7
+0x08 0x00 0x01 0x4c # CHECK: j 1328
+0x0c 0x00 0x01 0x4c # CHECK: jal 1328
+0x74 0x00 0x01 0x4c # CHECK: jalx 1328
+0x00 0xe0 0xf8 0x09 # CHECK: jalr $7
+0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
+0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
+0x00 0xe0 0x00 0x08 # CHECK: jr $7
+0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5)
+0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5)
+0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7)
+0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15)
+0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5)
+0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5)
+0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7)
+0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767
+0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
+0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5)
+0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7)
+0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4)
+0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
+0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
+0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
+0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
+0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
+0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
+0x00 0x00 0x28 0x10 # CHECK: mfhi $5
+0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
+0x00 0x00 0x28 0x12 # CHECK: mflo $5
+0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
+0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
+0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
+0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
+0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
+0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
+0x00 0xe0 0x00 0x11 # CHECK: mthi $7
+0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
+0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
+0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
+0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
+0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7
+0x00 0x65 0x00 0x18 # CHECK: mult $3, $5
+0x00 0x65 0x00 0x19 # CHECK: multu $3, $5
+0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14
+0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7
+0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
+0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
+0x00 0x00 0x00 0x00 # CHECK: nop
+0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7
+0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
+0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
+0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5
+0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767
+0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7
+0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7
+0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14
+0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7
+0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5)
+0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5)
+0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7)
+0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7)
+0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25)
+0x7c 0x07 0x34 0x20 # CHECK: seb $6, $7
+0x7c 0x07 0x36 0x20 # CHECK: seh $6, $7
+0xa4 0xa4 0x23 0xc6 # CHECK: sh $4, 9158($5)
+0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7
+0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5
+0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5
+0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103
+0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
+0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
+0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14
+0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7
+0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7
+0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5
+0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7
+0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5
+0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14
+0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7
+0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7
+0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5
+0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5)
+0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5)
+0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7)
+0xa8 0xa4 0x00 0x10 # CHECK: swl $4, 16($5)
+0xb8 0xe6 0x00 0x10 # CHECK: swr $6, 16($7)
+0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22)
+0x00 0x00 0x01 0xcf # CHECK: sync 7
+0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14
+0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7
+0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7
+0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5
+0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767
diff --git a/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt b/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt
new file mode 100644
index 00000000000..27f5498ea66
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt
@@ -0,0 +1,83 @@
+# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips32r5 | FileCheck %s
+# XFAIL: *
+0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
+0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
+0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
+0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
+0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
+0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
+0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3
+0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
+0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
+0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
+0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
+0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
+0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
+0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
+0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
+0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
+0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
+0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
+0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
+0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
+0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
+0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
+0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
+0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
+0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
+0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
+0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
+0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
+0x46 0xc0 0x45 0x85 # CHECK: abs.ps $f22, $f8
+0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
+0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10
+0x46 0xcc 0x66 0x30 # CHECK: c.f.ps $fcc6, $f12, $f12
+0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20
+0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
+0x46 0xda 0x10 0x3d # CHECK: c.nge.ps $f2, $f26
+0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
+0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20
+0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
+0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8
+0x46 0xd0 0x32 0x34 # CHECK: c.olt.ps $fcc2, $f6, $f16
+0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14
+0x46 0xc6 0x26 0x38 # CHECK: c.sf.ps $fcc6, $f4, $f6
+0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28
+0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2
+0x46 0xc0 0x76 0x35 # CHECK: c.ult.ps $fcc6, $f14, $f0
+0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
+0x46 0x20 0x20 0x8a # CHECK: ceil.l.d $f2, $f4
+0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
+0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
+0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
+0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
+0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
+0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
+0x46 0x20 0x36 0x8b # CHECK: floor.l.d $f26, $f6
+0x46 0x00 0x23 0x0b # CHECK: floor.l.s $f12, $f4
+0x4c 0x42 0x75 0xa6 # CHECK: madd.ps $f22, $f2, $f14, $f2
+0x46 0xc0 0x85 0x86 # CHECK: mov.ps $f22, $f16
+0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6
+0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
+0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
+0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
+0x4d 0xd0 0xe3 0x2e # CHECK: msub.ps $f12, $f14, $f28, $f16
+0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
+0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
+0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
+0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
+0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
+0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
+0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
+0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
+0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
+0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
+0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
+0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
+0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
+0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5
diff --git a/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt b/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt
index bc69512c013..cbc2eee3fe1 100644
--- a/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt
+++ b/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips32r2 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips64r2 | FileCheck %s
 # XFAIL: *
 0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
diff --git a/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt b/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
new file mode 100644
index 00000000000..52374af2893
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
@@ -0,0 +1,234 @@
+# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mcpu=mips64r3 | FileCheck %s
+# CHECK: .text
+0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
+0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
+0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
+0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
+0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
+0x67 0x45 0xc9 0x20 # CHECK: addi $9, $6, 17767
+0x67 0xc5 0xc9 0x24 # CHECK: addiu $9, $6, -15001
+0x21 0x48 0xc7 0x00 # CHECK: addu $9, $6, $7
+0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
+0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
+0x4c 0x01 0x00 0x10 # CHECK: b 1332
+0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
+0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
+0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
+0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
+0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
+0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
+0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
+0x4c 0x01 0xc0 0x1c # CHECK: bgtz $6, 1332
+0x4c 0x01 0xc0 0x18 # CHECK: blez $6, 1332
+0x4c 0x01 0x26 0x15 # CHECK: bne $9, $6, 1332
+0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
+0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
+0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
+0x30 0x30 0x07 0x46 # CHECK: c.f.s $f6, $f7
+0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
+0x3e 0x30 0x07 0x46 # CHECK: c.le.s $f6, $f7
+0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
+0x3c 0x30 0x07 0x46 # CHECK: c.lt.s $f6, $f7
+0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
+0x3d 0x30 0x07 0x46 # CHECK: c.nge.s $f6, $f7
+0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
+0x3b 0x30 0x07 0x46 # CHECK: c.ngl.s $f6, $f7
+0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
+0x39 0x30 0x07 0x46 # CHECK: c.ngle.s $f6, $f7
+0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
+0x3f 0x30 0x07 0x46 # CHECK: c.ngt.s $f6, $f7
+0x36 0x60 0x2e 0x46 # CHECK: c.ole.d $f12, $f14
+0x36 0x30 0x07 0x46 # CHECK: c.ole.s $f6, $f7
+0x34 0x60 0x2e 0x46 # CHECK: c.olt.d $f12, $f14
+0x34 0x30 0x07 0x46 # CHECK: c.olt.s $f6, $f7
+0x3a 0x60 0x2e 0x46 # CHECK: c.seq.d $f12, $f14
+0x3a 0x30 0x07 0x46 # CHECK: c.seq.s $f6, $f7
+0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
+0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
+0x33 0x60 0x2e 0x46 # CHECK: c.ueq.d $f12, $f14
+0x33 0xe0 0x12 0x46 # CHECK: c.ueq.s $f28, $f18
+0x37 0x60 0x2e 0x46 # CHECK: c.ule.d $f12, $f14
+0x37 0x30 0x07 0x46 # CHECK: c.ule.s $f6, $f7
+0x35 0x60 0x2e 0x46 # CHECK: c.ult.d $f12, $f14
+0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7
+0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14
+0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7
+0x4a 0x18 0x20 0x46 # CHECK: ceil.l.d $f1, $f3
+0x8a 0x6c 0x00 0x46 # CHECK: ceil.l.s $f18, $f13
+0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14
+0x8e 0x39 0x00 0x46 # CHECK: ceil.w.s $f6, $f7
+0x00 0x38 0x46 0x44 # CHECK: cfc1 $6, $7
+0x21 0x30 0xe6 0x70 # CHECK: clo $6, $7
+0x20 0x30 0xe6 0x70 # CHECK: clz $6, $7
+0x00 0x38 0xc6 0x44 # CHECK: ctc1 $6, $7
+0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16
+0xa1 0x39 0x00 0x46 # CHECK: cvt.d.s $f6, $f7
+0x21 0x73 0x80 0x46 # CHECK: cvt.d.w $f12, $f14
+0x25 0x73 0x20 0x46 # CHECK: cvt.l.d $f12, $f14
+0xa5 0x39 0x00 0x46 # CHECK: cvt.l.s $f6, $f7
+0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
+0x20 0x73 0x20 0x46 # CHECK: cvt.s.d $f12, $f14
+0xa0 0x39 0x80 0x46 # CHECK: cvt.s.w $f6, $f7
+0x24 0x73 0x20 0x46 # CHECK: cvt.w.d $f12, $f14
+0xa4 0x39 0x00 0x46 # CHECK: cvt.w.s $f6, $f7
+0x2c 0x98 0x3f 0x00 # CHECK: dadd $19, $1, $ra
+0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
+0xc7 0x93 0xbd 0x63 # CHECK: daddi $sp, $sp, -27705
+0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
+0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
+0xc7 0x93 0xbd 0x63 # CHECK: daddi $sp, $sp, -27705
+0x16 0xee 0xda 0x66 # CHECK: daddiu $26, $22, -4586
+0x2d 0x98 0x3f 0x00 # CHECK: daddu $19, $1, $ra
+0x9f 0x46 0x58 0x64 # CHECK: daddiu $24, $2, 18079
+0x3f 0x69 0x73 0x66 # CHECK: daddiu $19, $19, 26943
+0x25 0x90 0xd2 0x70 # CHECK: dclo $18, $6
+0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
+0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
+0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17
+0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
+0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
+0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9
+0x1d 0x00 0xa6 0x00 # CHECK: dmultu $5, $6
+0xb8 0x04 0x00 0x00 # CHECK: dsll $zero, $zero, 18
+0xb8 0x04 0x14 0x00 # CHECK: dsll $zero, $20, 18
+0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
+0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18
+0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18
+0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
+0xbb 0xe2 0x1c 0x00 # CHECK: dsra $gp, $gp, 10
+0xbb 0xe2 0x12 0x00 # CHECK: dsra $gp, $18, 10
+0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
+0xbf 0xe2 0x1c 0x00 # CHECK: dsra32 $gp, $gp, 10
+0xbf 0xe2 0x12 0x00 # CHECK: dsra32 $gp, $18, 10
+0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
+0xfa 0x9d 0x13 0x00 # CHECK: dsrl $19, $19, 23
+0xfa 0x9d 0x06 0x00 # CHECK: dsrl $19, $6, 23
+0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
+0xfe 0x9d 0x13 0x00 # CHECK: dsrl32 $19, $19, 23
+0xfe 0x9d 0x06 0x00 # CHECK: dsrl32 $19, $6, 23
+0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
+0x2e 0x38 0xc8 0x02 # CHECK: dsub $7, $22, $8
+0xa4 0x18 0x0e 0x7c # CHECK: dsbh $3, $14
+0x64 0x11 0x1d 0x7c # CHECK: dshd $2, $sp
+0x39 0x6c 0x9d 0x62 # CHECK: daddi $sp, $20, 27705
+0x39 0x6c 0xbd 0x63 # CHECK: daddi $sp, $sp, 27705
+0x2f 0x28 0xba 0x00 # CHECK: dsubu $5, $5, $26
+0x5f 0xec 0x6f 0x65 # CHECK: daddiu $15, $11, -5025
+0xea 0x11 0xce 0x65 # CHECK: daddiu $14, $14, 4586
+0x00 0x60 0x7e 0x41 # CHECK: di $fp
+0x00 0x60 0x60 0x41 # CHECK: di
+0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15
+0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15
+0xfe 0x0b 0x21 0x00 # CHECK: drotr32 $1, $1, 15
+0xfe 0x0b 0x2e 0x00 # CHECK: drotr32 $1, $14, 15
+0x56 0x08 0xee 0x01 # CHECK: drotrv $1, $14, $15
+0x20 0x60 0x6e 0x41 # CHECK: ei $14
+0x20 0x60 0x60 0x41 # CHECK: ei
+0x8b 0x3e 0x20 0x46 # CHECK: floor.l.d $f26, $f7
+0x0b 0x2b 0x00 0x46 # CHECK: floor.l.s $f12, $f5
+0x0f 0x73 0x20 0x46 # CHECK: floor.w.d $f12, $f14
+0x8f 0x39 0x00 0x46 # CHECK: floor.w.s $f6, $f7
+0x84 0x61 0x33 0x7d # CHECK: ins $19, $9, 6, 7
+0x4c 0x01 0x00 0x08 # CHECK: j 1328
+0x4c 0x01 0x00 0x0c # CHECK: jal 1328
+0x4c 0x01 0x00 0x74 # CHECK: jalx 1328
+0x09 0xf8 0xe0 0x00 # CHECK: jalr $7
+0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
+0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
+0x08 0x00 0xe0 0x00 # CHECK: jr $7
+0xc6 0x23 0xa4 0x80 # CHECK: lb $4, 9158($5)
+0x06 0x00 0xa4 0x90 # CHECK: lbu $4, 6($5)
+0x1b 0x90 0x3d 0xde # CHECK: ld $sp, -28645($17)
+0xb9 0xef 0x18 0x6b # CHECK: ldl $24, -4167($24)
+0x6a 0x89 0x8e 0x6e # CHECK: ldr $14, -30358($20)
+0xc6 0x23 0xe9 0xd4 # CHECK: ldc1 $f9, 9158($7)
+0x01 0x02 0xf7 0x4d # CHECK: ldxc1 $f8, $23($15)
+0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
+0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
+0xc6 0x23 0xe9 0xc0 # CHECK: ll $9, 9158($7)
+0x70 0xc6 0xe0 0xd3 # CHECK: lld $zero, -14736($ra)
+0x67 0x45 0x06 0x3c # CHECK: lui $6, 17767
+0x05 0x00 0xa6 0x4c # CHECK: luxc1 $f0, $6($5)
+0x18 0x00 0xa4 0x8c # CHECK: lw $4, 24($5)
+0xc6 0x23 0xe9 0xc4 # CHECK: lwc1 $f9, 9158($7)
+0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
+0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
+0x00 0x05 0xcc 0x4d # CHECK: lwxc1 $f20, $12($14)
+0xea 0xa1 0x73 0x9c # CHECK: lwu $19, -24086($3)
+0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
+0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
+0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
+0x10 0x28 0x00 0x00 # CHECK: mfhi $5
+0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
+0x12 0x28 0x00 0x00 # CHECK: mflo $5
+0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
+0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
+0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
+0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
+0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
+0x11 0x00 0xe0 0x00 # CHECK: mthi $7
+0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
+0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
+0x02 0x62 0x2e 0x46 # CHECK: mul.d $f8, $f12, $f14
+0x42 0x32 0x07 0x46 # CHECK: mul.s $f9, $f6, $f7
+0x02 0x48 0xc7 0x70 # CHECK: mul $9, $6, $7
+0x18 0x00 0x65 0x00 # CHECK: mult $3, $5
+0x19 0x00 0x65 0x00 # CHECK: multu $3, $5
+0x07 0x73 0x20 0x46 # CHECK: neg.d $f12, $f14
+0x87 0x39 0x00 0x46 # CHECK: neg.s $f6, $f7
+0x30 0xc8 0xac 0x4c # CHECK: nmadd.s $f0, $f5, $f25, $f12
+0x00 0x00 0x00 0x00 # CHECK: nop
+0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7
+0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
+0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
+0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
+0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
+0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
+0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
+0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
+0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
+0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
+0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
+0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
+0xcd 0xdf 0xaf 0xf3 # CHECK: scd $15, -8243($sp)
+0xcb 0x16 0x4c 0xfd # CHECK: sd $12, 5835($10)
+0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7)
+0x1f 0xae 0xc7 0xb3 # CHECK: sdl $7, -20961($fp)
+0x39 0xb0 0x8b 0xb5 # CHECK: sdr $11, -20423($12)
+0x09 0x40 0x24 0x4f # CHECK: sdxc1 $f8, $4($25)
+0x20 0x34 0x07 0x7c # CHECK: seb $6, $7
+0x20 0x36 0x07 0x7c # CHECK: seh $6, $7
+0xc6 0x23 0xa4 0xa4 # CHECK: sh $4, 9158($5)
+0xc0 0x21 0x03 0x00 # CHECK: sll $4, $3, 7
+0x04 0x10 0xa3 0x00 # CHECK: sllv $2, $3, $5
+0x2a 0x18 0x65 0x00 # CHECK: slt $3, $3, $5
+0x67 0x00 0x63 0x28 # CHECK: slti $3, $3, 103
+0x67 0x00 0x63 0x2c # CHECK: sltiu $3, $3, 103
+0x2b 0x18 0x65 0x00 # CHECK: sltu $3, $3, $5
+0x04 0x73 0x20 0x46 # CHECK: sqrt.d $f12, $f14
+0x84 0x39 0x00 0x46 # CHECK: sqrt.s $f6, $f7
+0xc3 0x21 0x03 0x00 # CHECK: sra $4, $3, 7
+0x07 0x10 0xa3 0x00 # CHECK: srav $2, $3, $5
+0xc2 0x21 0x03 0x00 # CHECK: srl $4, $3, 7
+0x06 0x10 0xa3 0x00 # CHECK: srlv $2, $3, $5
+0x01 0x62 0x2e 0x46 # CHECK: sub.d $f8, $f12, $f14
+0x41 0x32 0x07 0x46 # CHECK: sub.s $f9, $f6, $f7
+0x22 0x48 0xc7 0x00 # CHECK: sub $9, $6, $7
+0x23 0x20 0x65 0x00 # CHECK: subu $4, $3, $5
+0x0d 0x20 0xb8 0x4c # CHECK: suxc1 $f4, $24($5)
+0x18 0x00 0xa4 0xac # CHECK: sw $4, 24($5)
+0xc6 0x23 0xe9 0xe4 # CHECK: swc1 $f9, 9158($7)
+0x10 0x00 0xa4 0xa8 # CHECK: swl $4, 16($5)
+0x10 0x00 0xe6 0xb8 # CHECK: swr $6, 16($7)
+0x08 0xd0 0xd2 0x4e # CHECK: swxc1 $f26, $18($22)
+0xcf 0x01 0x00 0x00 # CHECK: sync 7
+0xc9 0xbd 0x20 0x46 # CHECK: trunc.l.d $f23, $f23
+0x09 0xff 0x00 0x46 # CHECK: trunc.l.s $f28, $f31
+0x0d 0x73 0x20 0x46 # CHECK: trunc.w.d $f12, $f14
+0x8d 0x39 0x00 0x46 # CHECK: trunc.w.s $f6, $f7
+0xa0 0x30 0x07 0x7c # CHECK: wsbh $6, $7
+0x26 0x18 0x65 0x00 # CHECK: xor $3, $3, $5
+0x67 0x45 0xc9 0x38 # CHECK: xori $9, $6, 17767
diff --git a/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt b/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
new file mode 100644
index 00000000000..5a427df4bd7
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
@@ -0,0 +1,234 @@
+# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r3 | FileCheck %s
+# CHECK: .text
+0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
+0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7
+0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7
+0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14
+0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7
+0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767
+0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001
+0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7
+0x00 0xc7 0x48 0x24 # CHECK: and $9, $6, $7
+0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767
+0x10 0x00 0x01 0x4c # CHECK: b 1332
+0x45 0x00 0x01 0x4c # CHECK: bc1f 1332
+0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332
+0x45 0x01 0x01 0x4c # CHECK: bc1t 1332
+0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332
+0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332
+0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
+0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
+0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332
+0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332
+0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332
+0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14
+0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7
+0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14
+0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7
+0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14
+0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7
+0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14
+0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7
+0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14
+0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7
+0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14
+0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7
+0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14
+0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7
+0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14
+0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7
+0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14
+0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7
+0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14
+0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7
+0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14
+0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7
+0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14
+0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7
+0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14
+0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18
+0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14
+0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7
+0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14
+0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7
+0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14
+0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7
+0x46 0x20 0x18 0x4a # CHECK: ceil.l.d $f1, $f3
+0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
+0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14
+0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7
+0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7
+0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7
+0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7
+0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7
+0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
+0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7
+0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
+0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14
+0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7
+0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
+0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14
+0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7
+0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14
+0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7
+0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra
+0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705
+0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705
+0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705
+0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705
+0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705
+0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586
+0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra
+0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079
+0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
+0x70 0xd2 0x90 0x25 # CHECK: dclo $18, $6
+0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
+0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
+0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
+0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
+0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
+0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
+0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
+0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
+0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
+0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
+0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
+0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
+0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
+0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10
+0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10
+0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19
+0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10
+0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10
+0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19
+0x00 0x13 0x9d 0xfa # CHECK: dsrl $19, $19, 23
+0x00 0x06 0x9d 0xfa # CHECK: dsrl $19, $6, 23
+0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20
+0x00 0x13 0x9d 0xfe # CHECK: dsrl32 $19, $19, 23
+0x00 0x06 0x9d 0xfe # CHECK: dsrl32 $19, $6, 23
+0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20
+0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8
+0x7c 0x0e 0x18 0xa4 # CHECK: dsbh $3, $14
+0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp
+0x62 0x9d 0x6c 0x39 # CHECK: daddi $sp, $20, 27705
+0x63 0xbd 0x6c 0x39 # CHECK: daddi $sp, $sp, 27705
+0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26
+0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025
+0x65 0xce 0x11 0xea # CHECK: daddiu $14, $14, 4586
+0x41 0x7e 0x60 0x00 # CHECK: di $fp
+0x41 0x60 0x60 0x00 # CHECK: di
+0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15
+0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15
+0x00 0x21 0x0b 0xfe # CHECK: drotr32 $1, $1, 15
+0x00 0x2e 0x0b 0xfe # CHECK: drotr32 $1, $14, 15
+0x01 0xee 0x08 0x56 # CHECK: drotrv $1, $14, $15
+0x41 0x6e 0x60 0x20 # CHECK: ei $14
+0x41 0x60 0x60 0x20 # CHECK: ei
+0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7
+0x46 0x00 0x2b 0x0b # CHECK: floor.l.s $f12, $f5
+0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14
+0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7
+0x7d 0x33 0x61 0x84 # CHECK: ins $19, $9, 6, 7
+0x08 0x00 0x01 0x4c # CHECK: j 1328
+0x0c 0x00 0x01 0x4c # CHECK: jal 1328
+0x74 0x00 0x01 0x4c # CHECK: jalx 1328
+0x00 0xe0 0xf8 0x09 # CHECK: jalr $7
+0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
+0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
+0x00 0xe0 0x00 0x08 # CHECK: jr $7
+0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5)
+0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5)
+0xde 0x3d 0x90 0x1b # CHECK: ld $sp, -28645($17)
+0x6b 0x18 0xef 0xb9 # CHECK: ldl $24, -4167($24)
+0x6e 0x8e 0x89 0x6a # CHECK: ldr $14, -30358($20)
+0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7)
+0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15)
+0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5)
+0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5)
+0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7)
+0xd3 0xe0 0xc6 0x70 # CHECK: lld $zero, -14736($ra)
+0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767
+0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
+0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5)
+0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7)
+0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4)
+0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
+0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
+0x9c 0x73 0xa1 0xea # CHECK: lwu $19, -24086($3)
+0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
+0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
+0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
+0x00 0x00 0x28 0x10 # CHECK: mfhi $5
+0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
+0x00 0x00 0x28 0x12 # CHECK: mflo $5
+0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
+0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
+0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
+0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
+0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
+0x00 0xe0 0x00 0x11 # CHECK: mthi $7
+0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
+0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
+0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
+0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
+0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7
+0x00 0x65 0x00 0x18 # CHECK: mult $3, $5
+0x00 0x65 0x00 0x19 # CHECK: multu $3, $5
+0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14
+0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7
+0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
+0x00 0x00 0x00 0x00 # CHECK: nop
+0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7
+0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
+0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5
+0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767
+0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7
+0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7
+0x46 0x20 0x0b 0x08 # CHECK: round.l.d $f12, $f1
+0x46 0x00 0x2e 0x48 # CHECK: round.l.s $f25, $f5
+0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14
+0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7
+0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5)
+0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5)
+0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7)
+0xf3 0xaf 0xdf 0xcd # CHECK: scd $15, -8243($sp)
+0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10)
+0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7)
+0xb3 0xc7 0xae 0x1f # CHECK: sdl $7, -20961($fp)
+0xb5 0x8b 0xb0 0x39 # CHECK: sdr $11, -20423($12)
+0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25)
+0x7c 0x07 0x34 0x20 # CHECK: seb $6, $7
+0x7c 0x07 0x36 0x20 # CHECK: seh $6, $7
+0xa4 0xa4 0x23 0xc6 # CHECK: sh $4, 9158($5)
+0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7
+0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5
+0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5
+0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103
+0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
+0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
+0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14
+0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7
+0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7
+0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5
+0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7
+0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5
+0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14
+0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7
+0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7
+0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5
+0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5)
+0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5)
+0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7)
+0xa8 0xa4 0x00 0x10 # CHECK: swl $4, 16($5)
+0xb8 0xe6 0x00 0x10 # CHECK: swr $6, 16($7)
+0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22)
+0x00 0x00 0x01 0xcf # CHECK: sync 7
+0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23
+0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
+0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14
+0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7
+0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7
+0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5
+0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767
diff --git a/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt b/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt
new file mode 100644
index 00000000000..8c58eb1c9e3
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt
@@ -0,0 +1,76 @@
+# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips64r3 | FileCheck %s
+# XFAIL: *
+0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
+0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
+0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
+0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
+0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
+0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
+0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3
+0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
+0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
+0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
+0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
+0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
+0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
+0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
+0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
+0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
+0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
+0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
+0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
+0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
+0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
+0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
+0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
+0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
+0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
+0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
+0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
+0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
+0x46 0xc0 0x45 0x85 # CHECK: abs.ps $f22, $f8
+0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
+0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10
+0x46 0xcc 0x66 0x30 # CHECK: c.f.ps $fcc6, $f12, $f12
+0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20
+0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
+0x46 0xda 0x10 0x3d # CHECK: c.nge.ps $f2, $f26
+0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
+0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20
+0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
+0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8
+0x46 0xd0 0x32 0x34 # CHECK: c.olt.ps $fcc2, $f6, $f16
+0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14
+0x46 0xc6 0x26 0x38 # CHECK: c.sf.ps $fcc6, $f4, $f6
+0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28
+0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2
+0x46 0xc0 0x76 0x35 # CHECK: c.ult.ps $fcc6, $f14, $f0
+0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
+0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
+0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
+0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
+0x4c 0x42 0x75 0xa6 # CHECK: madd.ps $f22, $f2, $f14, $f2
+0x46 0xc0 0x85 0x86 # CHECK: mov.ps $f22, $f16
+0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6
+0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
+0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
+0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
+0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
+0x4d 0xd0 0xe3 0x2e # CHECK: msub.ps $f12, $f14, $f28, $f16
+0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
+0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
+0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
+0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
+0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
+0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
+0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
+0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
+0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
+0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
+0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
+0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5
diff --git a/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
new file mode 100644
index 00000000000..3d97a2b30ce
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
@@ -0,0 +1,234 @@
+# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mcpu=mips64r5 | FileCheck %s
+# CHECK: .text
+0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
+0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
+0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
+0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
+0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
+0x67 0x45 0xc9 0x20 # CHECK: addi $9, $6, 17767
+0x67 0xc5 0xc9 0x24 # CHECK: addiu $9, $6, -15001
+0x21 0x48 0xc7 0x00 # CHECK: addu $9, $6, $7
+0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
+0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
+0x4c 0x01 0x00 0x10 # CHECK: b 1332
+0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
+0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
+0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
+0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
+0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
+0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
+0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
+0x4c 0x01 0xc0 0x1c # CHECK: bgtz $6, 1332
+0x4c 0x01 0xc0 0x18 # CHECK: blez $6, 1332
+0x4c 0x01 0x26 0x15 # CHECK: bne $9, $6, 1332
+0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
+0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
+0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
+0x30 0x30 0x07 0x46 # CHECK: c.f.s $f6, $f7
+0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
+0x3e 0x30 0x07 0x46 # CHECK: c.le.s $f6, $f7
+0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
+0x3c 0x30 0x07 0x46 # CHECK: c.lt.s $f6, $f7
+0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
+0x3d 0x30 0x07 0x46 # CHECK: c.nge.s $f6, $f7
+0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
+0x3b 0x30 0x07 0x46 # CHECK: c.ngl.s $f6, $f7
+0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
+0x39 0x30 0x07 0x46 # CHECK: c.ngle.s $f6, $f7
+0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
+0x3f 0x30 0x07 0x46 # CHECK: c.ngt.s $f6, $f7
+0x36 0x60 0x2e 0x46 # CHECK: c.ole.d $f12, $f14
+0x36 0x30 0x07 0x46 # CHECK: c.ole.s $f6, $f7
+0x34 0x60 0x2e 0x46 # CHECK: c.olt.d $f12, $f14
+0x34 0x30 0x07 0x46 # CHECK: c.olt.s $f6, $f7
+0x3a 0x60 0x2e 0x46 # CHECK: c.seq.d $f12, $f14
+0x3a 0x30 0x07 0x46 # CHECK: c.seq.s $f6, $f7
+0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
+0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
+0x33 0x60 0x2e 0x46 # CHECK: c.ueq.d $f12, $f14
+0x33 0xe0 0x12 0x46 # CHECK: c.ueq.s $f28, $f18
+0x37 0x60 0x2e 0x46 # CHECK: c.ule.d $f12, $f14
+0x37 0x30 0x07 0x46 # CHECK: c.ule.s $f6, $f7
+0x35 0x60 0x2e 0x46 # CHECK: c.ult.d $f12, $f14
+0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7
+0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14
+0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7
+0x4a 0x18 0x20 0x46 # CHECK: ceil.l.d $f1, $f3
+0x8a 0x6c 0x00 0x46 # CHECK: ceil.l.s $f18, $f13
+0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14
+0x8e 0x39 0x00 0x46 # CHECK: ceil.w.s $f6, $f7
+0x00 0x38 0x46 0x44 # CHECK: cfc1 $6, $7
+0x21 0x30 0xe6 0x70 # CHECK: clo $6, $7
+0x20 0x30 0xe6 0x70 # CHECK: clz $6, $7
+0x00 0x38 0xc6 0x44 # CHECK: ctc1 $6, $7
+0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16
+0xa1 0x39 0x00 0x46 # CHECK: cvt.d.s $f6, $f7
+0x21 0x73 0x80 0x46 # CHECK: cvt.d.w $f12, $f14
+0x25 0x73 0x20 0x46 # CHECK: cvt.l.d $f12, $f14
+0xa5 0x39 0x00 0x46 # CHECK: cvt.l.s $f6, $f7
+0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
+0x20 0x73 0x20 0x46 # CHECK: cvt.s.d $f12, $f14
+0xa0 0x39 0x80 0x46 # CHECK: cvt.s.w $f6, $f7
+0x24 0x73 0x20 0x46 # CHECK: cvt.w.d $f12, $f14
+0xa4 0x39 0x00 0x46 # CHECK: cvt.w.s $f6, $f7
+0x2c 0x98 0x3f 0x00 # CHECK: dadd $19, $1, $ra
+0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
+0xc7 0x93 0xbd 0x63 # CHECK: daddi $sp, $sp, -27705
+0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
+0xc7 0x93 0x9d 0x62 # CHECK: daddi $sp, $20, -27705
+0xc7 0x93 0xbd 0x63 # CHECK: daddi $sp, $sp, -27705
+0x16 0xee 0xda 0x66 # CHECK: daddiu $26, $22, -4586
+0x2d 0x98 0x3f 0x00 # CHECK: daddu $19, $1, $ra
+0x9f 0x46 0x58 0x64 # CHECK: daddiu $24, $2, 18079
+0x3f 0x69 0x73 0x66 # CHECK: daddiu $19, $19, 26943
+0x25 0x90 0xd2 0x70 # CHECK: dclo $18, $6
+0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
+0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
+0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17
+0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
+0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
+0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9
+0x1d 0x00 0xa6 0x00 # CHECK: dmultu $5, $6
+0xb8 0x04 0x00 0x00 # CHECK: dsll $zero, $zero, 18
+0xb8 0x04 0x14 0x00 # CHECK: dsll $zero, $20, 18
+0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
+0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18
+0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18
+0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
+0xbb 0xe2 0x1c 0x00 # CHECK: dsra $gp, $gp, 10
+0xbb 0xe2 0x12 0x00 # CHECK: dsra $gp, $18, 10
+0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
+0xbf 0xe2 0x1c 0x00 # CHECK: dsra32 $gp, $gp, 10
+0xbf 0xe2 0x12 0x00 # CHECK: dsra32 $gp, $18, 10
+0x17 0xe0 0x72 0x02 # CHECK: dsrav $gp, $18, $19
+0xfa 0x9d 0x13 0x00 # CHECK: dsrl $19, $19, 23
+0xfa 0x9d 0x06 0x00 # CHECK: dsrl $19, $6, 23
+0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
+0xfe 0x9d 0x13 0x00 # CHECK: dsrl32 $19, $19, 23
+0xfe 0x9d 0x06 0x00 # CHECK: dsrl32 $19, $6, 23
+0x16 0x98 0x86 0x02 # CHECK: dsrlv $19, $6, $20
+0x2e 0x38 0xc8 0x02 # CHECK: dsub $7, $22, $8
+0xa4 0x18 0x0e 0x7c # CHECK: dsbh $3, $14
+0x64 0x11 0x1d 0x7c # CHECK: dshd $2, $sp
+0x39 0x6c 0x9d 0x62 # CHECK: daddi $sp, $20, 27705
+0x39 0x6c 0xbd 0x63 # CHECK: daddi $sp, $sp, 27705
+0x2f 0x28 0xba 0x00 # CHECK: dsubu $5, $5, $26
+0x5f 0xec 0x6f 0x65 # CHECK: daddiu $15, $11, -5025
+0xea 0x11 0xce 0x65 # CHECK: daddiu $14, $14, 4586
+0x00 0x60 0x7e 0x41 # CHECK: di $fp
+0x00 0x60 0x60 0x41 # CHECK: di
+0xfa 0x0b 0x21 0x00 # CHECK: drotr $1, $1, 15
+0xfa 0x0b 0x2e 0x00 # CHECK: drotr $1, $14, 15
+0xfe 0x0b 0x21 0x00 # CHECK: drotr32 $1, $1, 15
+0xfe 0x0b 0x2e 0x00 # CHECK: drotr32 $1, $14, 15
+0x56 0x08 0xee 0x01 # CHECK: drotrv $1, $14, $15
+0x20 0x60 0x6e 0x41 # CHECK: ei $14
+0x20 0x60 0x60 0x41 # CHECK: ei
+0x8b 0x3e 0x20 0x46 # CHECK: floor.l.d $f26, $f7
+0x0b 0x2b 0x00 0x46 # CHECK: floor.l.s $f12, $f5
+0x0f 0x73 0x20 0x46 # CHECK: floor.w.d $f12, $f14
+0x8f 0x39 0x00 0x46 # CHECK: floor.w.s $f6, $f7
+0x84 0x61 0x33 0x7d # CHECK: ins $19, $9, 6, 7
+0x4c 0x01 0x00 0x08 # CHECK: j 1328
+0x4c 0x01 0x00 0x0c # CHECK: jal 1328
+0x4c 0x01 0x00 0x74 # CHECK: jalx 1328
+0x09 0xf8 0xe0 0x00 # CHECK: jalr $7
+0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
+0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
+0x08 0x00 0xe0 0x00 # CHECK: jr $7
+0xc6 0x23 0xa4 0x80 # CHECK: lb $4, 9158($5)
+0x06 0x00 0xa4 0x90 # CHECK: lbu $4, 6($5)
+0x1b 0x90 0x3d 0xde # CHECK: ld $sp, -28645($17)
+0xb9 0xef 0x18 0x6b # CHECK: ldl $24, -4167($24)
+0x6a 0x89 0x8e 0x6e # CHECK: ldr $14, -30358($20)
+0xc6 0x23 0xe9 0xd4 # CHECK: ldc1 $f9, 9158($7)
+0x01 0x02 0xf7 0x4d # CHECK: ldxc1 $f8, $23($15)
+0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
+0x0c 0x00 0xa4 0x84 # CHECK: lh $4, 12($5)
+0xc6 0x23 0xe9 0xc0 # CHECK: ll $9, 9158($7)
+0x70 0xc6 0xe0 0xd3 # CHECK: lld $zero, -14736($ra)
+0x67 0x45 0x06 0x3c # CHECK: lui $6, 17767
+0x05 0x00 0xa6 0x4c # CHECK: luxc1 $f0, $6($5)
+0x18 0x00 0xa4 0x8c # CHECK: lw $4, 24($5)
+0xc6 0x23 0xe9 0xc4 # CHECK: lwc1 $f9, 9158($7)
+0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
+0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
+0x00 0x05 0xcc 0x4d # CHECK: lwxc1 $f20, $12($14)
+0xea 0xa1 0x73 0x9c # CHECK: lwu $19, -24086($3)
+0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
+0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
+0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
+0x10 0x28 0x00 0x00 # CHECK: mfhi $5
+0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
+0x12 0x28 0x00 0x00 # CHECK: mflo $5
+0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
+0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
+0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
+0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
+0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
+0x11 0x00 0xe0 0x00 # CHECK: mthi $7
+0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
+0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
+0x02 0x62 0x2e 0x46 # CHECK: mul.d $f8, $f12, $f14
+0x42 0x32 0x07 0x46 # CHECK: mul.s $f9, $f6, $f7
+0x02 0x48 0xc7 0x70 # CHECK: mul $9, $6, $7
+0x18 0x00 0x65 0x00 # CHECK: mult $3, $5
+0x19 0x00 0x65 0x00 # CHECK: multu $3, $5
+0x07 0x73 0x20 0x46 # CHECK: neg.d $f12, $f14
+0x87 0x39 0x00 0x46 # CHECK: neg.s $f6, $f7
+0x30 0xc8 0xac 0x4c # CHECK: nmadd.s $f0, $f5, $f25, $f12
+0x00 0x00 0x00 0x00 # CHECK: nop
+0x27 0x48 0xc7 0x00 # CHECK: nor $9, $6, $7
+0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
+0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
+0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
+0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
+0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
+0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
+0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
+0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
+0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
+0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
+0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
+0xcd 0xdf 0xaf 0xf3 # CHECK: scd $15, -8243($sp)
+0xcb 0x16 0x4c 0xfd # CHECK: sd $12, 5835($10)
+0xc6 0x23 0xe9 0xf4 # CHECK: sdc1 $f9, 9158($7)
+0x1f 0xae 0xc7 0xb3 # CHECK: sdl $7, -20961($fp)
+0x39 0xb0 0x8b 0xb5 # CHECK: sdr $11, -20423($12)
+0x09 0x40 0x24 0x4f # CHECK: sdxc1 $f8, $4($25)
+0x20 0x34 0x07 0x7c # CHECK: seb $6, $7
+0x20 0x36 0x07 0x7c # CHECK: seh $6, $7
+0xc6 0x23 0xa4 0xa4 # CHECK: sh $4, 9158($5)
+0xc0 0x21 0x03 0x00 # CHECK: sll $4, $3, 7
+0x04 0x10 0xa3 0x00 # CHECK: sllv $2, $3, $5
+0x2a 0x18 0x65 0x00 # CHECK: slt $3, $3, $5
+0x67 0x00 0x63 0x28 # CHECK: slti $3, $3, 103
+0x67 0x00 0x63 0x2c # CHECK: sltiu $3, $3, 103
+0x2b 0x18 0x65 0x00 # CHECK: sltu $3, $3, $5
+0x04 0x73 0x20 0x46 # CHECK: sqrt.d $f12, $f14
+0x84 0x39 0x00 0x46 # CHECK: sqrt.s $f6, $f7
+0xc3 0x21 0x03 0x00 # CHECK: sra $4, $3, 7
+0x07 0x10 0xa3 0x00 # CHECK: srav $2, $3, $5
+0xc2 0x21 0x03 0x00 # CHECK: srl $4, $3, 7
+0x06 0x10 0xa3 0x00 # CHECK: srlv $2, $3, $5
+0x01 0x62 0x2e 0x46 # CHECK: sub.d $f8, $f12, $f14
+0x41 0x32 0x07 0x46 # CHECK: sub.s $f9, $f6, $f7
+0x22 0x48 0xc7 0x00 # CHECK: sub $9, $6, $7
+0x23 0x20 0x65 0x00 # CHECK: subu $4, $3, $5
+0x0d 0x20 0xb8 0x4c # CHECK: suxc1 $f4, $24($5)
+0x18 0x00 0xa4 0xac # CHECK: sw $4, 24($5)
+0xc6 0x23 0xe9 0xe4 # CHECK: swc1 $f9, 9158($7)
+0x10 0x00 0xa4 0xa8 # CHECK: swl $4, 16($5)
+0x10 0x00 0xe6 0xb8 # CHECK: swr $6, 16($7)
+0x08 0xd0 0xd2 0x4e # CHECK: swxc1 $f26, $18($22)
+0xcf 0x01 0x00 0x00 # CHECK: sync 7
+0xc9 0xbd 0x20 0x46 # CHECK: trunc.l.d $f23, $f23
+0x09 0xff 0x00 0x46 # CHECK: trunc.l.s $f28, $f31
+0x0d 0x73 0x20 0x46 # CHECK: trunc.w.d $f12, $f14
+0x8d 0x39 0x00 0x46 # CHECK: trunc.w.s $f6, $f7
+0xa0 0x30 0x07 0x7c # CHECK: wsbh $6, $7
+0x26 0x18 0x65 0x00 # CHECK: xor $3, $3, $5
+0x67 0x45 0xc9 0x38 # CHECK: xori $9, $6, 17767
diff --git a/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
new file mode 100644
index 00000000000..1f52bd14185
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
@@ -0,0 +1,234 @@
+# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r5 | FileCheck %s
+# CHECK: .text
+0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
+0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7
+0x00 0xc7 0x48 0x20 # CHECK: add $9, $6, $7
+0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14
+0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7
+0x20 0xc9 0x45 0x67 # CHECK: addi $9, $6, 17767
+0x24 0xc9 0xc5 0x67 # CHECK: addiu $9, $6, -15001
+0x00 0xc7 0x48 0x21 # CHECK: addu $9, $6, $7
+0x00 0xc7 0x48 0x24 # CHECK: and $9, $6, $7
+0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767
+0x10 0x00 0x01 0x4c # CHECK: b 1332
+0x45 0x00 0x01 0x4c # CHECK: bc1f 1332
+0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332
+0x45 0x01 0x01 0x4c # CHECK: bc1t 1332
+0x45 0x1d 0x01 0x4c # CHECK: bc1t $fcc7, 1332
+0x11 0x26 0x01 0x4c # CHECK: beq $9, $6, 1332
+0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
+0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
+0x1c 0xc0 0x01 0x4c # CHECK: bgtz $6, 1332
+0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332
+0x15 0x26 0x01 0x4c # CHECK: bne $9, $6, 1332
+0x46 0x2e 0x60 0x32 # CHECK: c.eq.d $f12, $f14
+0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7
+0x46 0x2e 0x60 0x30 # CHECK: c.f.d $f12, $f14
+0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7
+0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14
+0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7
+0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14
+0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7
+0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14
+0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7
+0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14
+0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7
+0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14
+0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7
+0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14
+0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7
+0x46 0x2e 0x60 0x36 # CHECK: c.ole.d $f12, $f14
+0x46 0x07 0x30 0x36 # CHECK: c.ole.s $f6, $f7
+0x46 0x2e 0x60 0x34 # CHECK: c.olt.d $f12, $f14
+0x46 0x07 0x30 0x34 # CHECK: c.olt.s $f6, $f7
+0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14
+0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7
+0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14
+0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7
+0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14
+0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18
+0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14
+0x46 0x07 0x30 0x37 # CHECK: c.ule.s $f6, $f7
+0x46 0x2e 0x60 0x35 # CHECK: c.ult.d $f12, $f14
+0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7
+0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14
+0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7
+0x46 0x20 0x18 0x4a # CHECK: ceil.l.d $f1, $f3
+0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
+0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14
+0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7
+0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7
+0x70 0xe6 0x30 0x21 # CHECK: clo $6, $7
+0x70 0xe6 0x30 0x20 # CHECK: clz $6, $7
+0x44 0xc6 0x38 0x00 # CHECK: ctc1 $6, $7
+0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
+0x46 0x00 0x39 0xa1 # CHECK: cvt.d.s $f6, $f7
+0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
+0x46 0x20 0x73 0x25 # CHECK: cvt.l.d $f12, $f14
+0x46 0x00 0x39 0xa5 # CHECK: cvt.l.s $f6, $f7
+0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
+0x46 0x20 0x73 0x20 # CHECK: cvt.s.d $f12, $f14
+0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7
+0x46 0x20 0x73 0x24 # CHECK: cvt.w.d $f12, $f14
+0x46 0x00 0x39 0xa4 # CHECK: cvt.w.s $f6, $f7
+0x00 0x3f 0x98 0x2c # CHECK: dadd $19, $1, $ra
+0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705
+0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705
+0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705
+0x62 0x9d 0x93 0xc7 # CHECK: daddi $sp, $20, -27705
+0x63 0xbd 0x93 0xc7 # CHECK: daddi $sp, $sp, -27705
+0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586
+0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra
+0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079
+0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
+0x70 0xd2 0x90 0x25 # CHECK: dclo $18, $6
+0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
+0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
+0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
+0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
+0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
+0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
+0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
+0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
+0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
+0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
+0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
+0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
+0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
+0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10
+0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10
+0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19
+0x00 0x1c 0xe2 0xbf # CHECK: dsra32 $gp, $gp, 10
+0x00 0x12 0xe2 0xbf # CHECK: dsra32 $gp, $18, 10
+0x02 0x72 0xe0 0x17 # CHECK: dsrav $gp, $18, $19
+0x00 0x13 0x9d 0xfa # CHECK: dsrl $19, $19, 23
+0x00 0x06 0x9d 0xfa # CHECK: dsrl $19, $6, 23
+0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20
+0x00 0x13 0x9d 0xfe # CHECK: dsrl32 $19, $19, 23
+0x00 0x06 0x9d 0xfe # CHECK: dsrl32 $19, $6, 23
+0x02 0x86 0x98 0x16 # CHECK: dsrlv $19, $6, $20
+0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8
+0x7c 0x0e 0x18 0xa4 # CHECK: dsbh $3, $14
+0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp
+0x62 0x9d 0x6c 0x39 # CHECK: daddi $sp, $20, 27705
+0x63 0xbd 0x6c 0x39 # CHECK: daddi $sp, $sp, 27705
+0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26
+0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025
+0x65 0xce 0x11 0xea # CHECK: daddiu $14, $14, 4586
+0x41 0x7e 0x60 0x00 # CHECK: di $fp
+0x41 0x60 0x60 0x00 # CHECK: di
+0x00 0x21 0x0b 0xfa # CHECK: drotr $1, $1, 15
+0x00 0x2e 0x0b 0xfa # CHECK: drotr $1, $14, 15
+0x00 0x21 0x0b 0xfe # CHECK: drotr32 $1, $1, 15
+0x00 0x2e 0x0b 0xfe # CHECK: drotr32 $1, $14, 15
+0x01 0xee 0x08 0x56 # CHECK: drotrv $1, $14, $15
+0x41 0x6e 0x60 0x20 # CHECK: ei $14
+0x41 0x60 0x60 0x20 # CHECK: ei
+0x46 0x20 0x3e 0x8b # CHECK: floor.l.d $f26, $f7
+0x46 0x00 0x2b 0x0b # CHECK: floor.l.s $f12, $f5
+0x46 0x20 0x73 0x0f # CHECK: floor.w.d $f12, $f14
+0x46 0x00 0x39 0x8f # CHECK: floor.w.s $f6, $f7
+0x7d 0x33 0x61 0x84 # CHECK: ins $19, $9, 6, 7
+0x08 0x00 0x01 0x4c # CHECK: j 1328
+0x0c 0x00 0x01 0x4c # CHECK: jal 1328
+0x74 0x00 0x01 0x4c # CHECK: jalx 1328
+0x00 0xe0 0xf8 0x09 # CHECK: jalr $7
+0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
+0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
+0x00 0xe0 0x00 0x08 # CHECK: jr $7
+0x80 0xa4 0x23 0xc6 # CHECK: lb $4, 9158($5)
+0x90 0xa4 0x00 0x06 # CHECK: lbu $4, 6($5)
+0xde 0x3d 0x90 0x1b # CHECK: ld $sp, -28645($17)
+0x6b 0x18 0xef 0xb9 # CHECK: ldl $24, -4167($24)
+0x6e 0x8e 0x89 0x6a # CHECK: ldr $14, -30358($20)
+0xd4 0xe9 0x23 0xc6 # CHECK: ldc1 $f9, 9158($7)
+0x4d 0xf7 0x02 0x01 # CHECK: ldxc1 $f8, $23($15)
+0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5)
+0x84 0xa4 0x00 0x0c # CHECK: lh $4, 12($5)
+0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7)
+0xd3 0xe0 0xc6 0x70 # CHECK: lld $zero, -14736($ra)
+0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767
+0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
+0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5)
+0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7)
+0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4)
+0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
+0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
+0x9c 0x73 0xa1 0xea # CHECK: lwu $19, -24086($3)
+0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
+0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
+0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
+0x00 0x00 0x28 0x10 # CHECK: mfhi $5
+0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
+0x00 0x00 0x28 0x12 # CHECK: mflo $5
+0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
+0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
+0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
+0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
+0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
+0x00 0xe0 0x00 0x11 # CHECK: mthi $7
+0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
+0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
+0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
+0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
+0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7
+0x00 0x65 0x00 0x18 # CHECK: mult $3, $5
+0x00 0x65 0x00 0x19 # CHECK: multu $3, $5
+0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14
+0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7
+0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
+0x00 0x00 0x00 0x00 # CHECK: nop
+0x00 0xc7 0x48 0x27 # CHECK: nor $9, $6, $7
+0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
+0x00 0x65 0x18 0x25 # CHECK: or $3, $3, $5
+0x34 0xc9 0x45 0x67 # CHECK: ori $9, $6, 17767
+0x00 0x26 0x49 0xc2 # CHECK: rotr $9, $6, 7
+0x00 0xe6 0x48 0x46 # CHECK: rotrv $9, $6, $7
+0x46 0x20 0x0b 0x08 # CHECK: round.l.d $f12, $f1
+0x46 0x00 0x2e 0x48 # CHECK: round.l.s $f25, $f5
+0x46 0x20 0x73 0x0c # CHECK: round.w.d $f12, $f14
+0x46 0x00 0x39 0x8c # CHECK: round.w.s $f6, $f7
+0xa0 0xa4 0x23 0xc6 # CHECK: sb $4, 9158($5)
+0xa0 0xa4 0x00 0x06 # CHECK: sb $4, 6($5)
+0xe0 0xe9 0x23 0xc6 # CHECK: sc $9, 9158($7)
+0xf3 0xaf 0xdf 0xcd # CHECK: scd $15, -8243($sp)
+0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10)
+0xf4 0xe9 0x23 0xc6 # CHECK: sdc1 $f9, 9158($7)
+0xb3 0xc7 0xae 0x1f # CHECK: sdl $7, -20961($fp)
+0xb5 0x8b 0xb0 0x39 # CHECK: sdr $11, -20423($12)
+0x4f 0x24 0x40 0x09 # CHECK: sdxc1 $f8, $4($25)
+0x7c 0x07 0x34 0x20 # CHECK: seb $6, $7
+0x7c 0x07 0x36 0x20 # CHECK: seh $6, $7
+0xa4 0xa4 0x23 0xc6 # CHECK: sh $4, 9158($5)
+0x00 0x03 0x21 0xc0 # CHECK: sll $4, $3, 7
+0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5
+0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5
+0x28 0x63 0x00 0x67 # CHECK: slti $3, $3, 103
+0x2c 0x63 0x00 0x67 # CHECK: sltiu $3, $3, 103
+0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
+0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14
+0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7
+0x00 0x03 0x21 0xc3 # CHECK: sra $4, $3, 7
+0x00 0xa3 0x10 0x07 # CHECK: srav $2, $3, $5
+0x00 0x03 0x21 0xc2 # CHECK: srl $4, $3, 7
+0x00 0xa3 0x10 0x06 # CHECK: srlv $2, $3, $5
+0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14
+0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7
+0x00 0xc7 0x48 0x22 # CHECK: sub $9, $6, $7
+0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5
+0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5)
+0xac 0xa4 0x00 0x18 # CHECK: sw $4, 24($5)
+0xe4 0xe9 0x23 0xc6 # CHECK: swc1 $f9, 9158($7)
+0xa8 0xa4 0x00 0x10 # CHECK: swl $4, 16($5)
+0xb8 0xe6 0x00 0x10 # CHECK: swr $6, 16($7)
+0x4e 0xd2 0xd0 0x08 # CHECK: swxc1 $f26, $18($22)
+0x00 0x00 0x01 0xcf # CHECK: sync 7
+0x46 0x20 0xbd 0xc9 # CHECK: trunc.l.d $f23, $f23
+0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
+0x46 0x20 0x73 0x0d # CHECK: trunc.w.d $f12, $f14
+0x46 0x00 0x39 0x8d # CHECK: trunc.w.s $f6, $f7
+0x7c 0x07 0x30 0xa0 # CHECK: wsbh $6, $7
+0x00 0x65 0x18 0x26 # CHECK: xor $3, $3, $5
+0x38 0xc9 0x45 0x67 # CHECK: xori $9, $6, 17767
diff --git a/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt b/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt
new file mode 100644
index 00000000000..b8a98bdf73e
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt
@@ -0,0 +1,76 @@
+# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips64r5 | FileCheck %s
+# XFAIL: *
+0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
+0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
+0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
+0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
+0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
+0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
+0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3
+0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
+0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
+0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
+0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
+0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
+0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
+0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
+0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
+0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
+0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
+0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
+0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
+0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
+0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
+0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
+0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
+0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
+0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
+0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
+0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
+0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
+0x46 0xc0 0x45 0x85 # CHECK: abs.ps $f22, $f8
+0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
+0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10
+0x46 0xcc 0x66 0x30 # CHECK: c.f.ps $fcc6, $f12, $f12
+0x46 0xd4 0x42 0x3e # CHECK: c.le.ps $fcc2, $f8, $f20
+0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
+0x46 0xda 0x10 0x3d # CHECK: c.nge.ps $f2, $f26
+0x46 0xde 0xb0 0x3b # CHECK: c.ngl.ps $f22, $f30
+0x46 0xd4 0x66 0x39 # CHECK: c.ngle.ps $fcc6, $f12, $f20
+0x46 0xc6 0xf6 0x3f # CHECK: c.ngt.ps $fcc6, $f30, $f6
+0x46 0xc8 0xa6 0x36 # CHECK: c.ole.ps $fcc6, $f20, $f8
+0x46 0xd0 0x32 0x34 # CHECK: c.olt.ps $fcc2, $f6, $f16
+0x46 0xce 0xf6 0x3a # CHECK: c.seq.ps $fcc6, $f30, $f14
+0x46 0xc6 0x26 0x38 # CHECK: c.sf.ps $fcc6, $f4, $f6
+0x46 0xdc 0x20 0x33 # CHECK: c.ueq.ps $f4, $f28
+0x46 0xc2 0x86 0x37 # CHECK: c.ule.ps $fcc6, $f16, $f2
+0x46 0xc0 0x76 0x35 # CHECK: c.ult.ps $fcc6, $f14, $f0
+0x46 0xda 0x14 0x31 # CHECK: c.un.ps $fcc4, $f2, $f26
+0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2
+0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26
+0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
+0x4c 0x42 0x75 0xa6 # CHECK: madd.ps $f22, $f2, $f14, $f2
+0x46 0xc0 0x85 0x86 # CHECK: mov.ps $f22, $f16
+0x46 0xd8 0xe2 0x91 # CHECK: movf.ps $f10, $f28, $fcc6
+0x46 0xd3 0xf7 0x93 # CHECK: movn.ps $f30, $f30, s3
+0x46 0xc9 0xc5 0x11 # CHECK: movt.ps $f20, $f24, $fcc2
+0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
+0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
+0x4d 0xd0 0xe3 0x2e # CHECK: msub.ps $f12, $f14, $f28, $f16
+0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
+0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
+0x4c 0x98 0x46 0xb6 # CHECK: nmadd.ps $f26, $f4, $f8, $f24
+0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
+0x4d 0x90 0x71 0xbe # CHECK: nmsub.ps $f6, $f12, $f14, $f16
+0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
+0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28
+0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
+0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
+0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
+0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
+0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5
diff --git a/test/MC/Mips/elf_eflags.s b/test/MC/Mips/elf_eflags.s
index d8f84231f96..708894fee80 100644
--- a/test/MC/Mips/elf_eflags.s
+++ b/test/MC/Mips/elf_eflags.s
@@ -8,9 +8,13 @@
 # MIPSEL-MIPS64R6-NAN2008: Flags [ (0xA0000406)
 
 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2 %s
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r3 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2 %s
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r5 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2 %s
 # MIPSEL-MIPS64R2: Flags [ (0x80000006)
 
 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2-NAN2008 %s
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r3 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2-NAN2008 %s
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r5 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2-NAN2008 %s
 # MIPSEL-MIPS64R2-NAN2008: Flags [ (0x80000406)
 
 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64 %s
@@ -26,9 +30,13 @@
 # MIPSEL-MIPS32R6-NAN2008: Flags [ (0x90001404)
 
 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2 %s
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r3 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2 %s
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r5 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2 %s
 # MIPSEL-MIPS32R2: Flags [ (0x70001004)
 
 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2-NAN2008 %s
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r3 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2-NAN2008 %s
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r5 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2-NAN2008 %s
 # MIPSEL-MIPS32R2-NAN2008: Flags [ (0x70001404)
 
 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32 %s
diff --git a/test/MC/Mips/mips32r3/abiflags.s b/test/MC/Mips/mips32r3/abiflags.s
new file mode 100644
index 00000000000..a6c7057809f
--- /dev/null
+++ b/test/MC/Mips/mips32r3/abiflags.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r3 | \
+# RUN:   FileCheck %s -check-prefix=CHECK-ASM
+#
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r3 -filetype=obj -o - | \
+# RUN:   llvm-readobj -sections -section-data -section-relocations - | \
+# RUN:     FileCheck %s -check-prefix=CHECK-OBJ
+
+# CHECK-ASM: .module fp=32
+# CHECK-ASM: .set fp=64
+
+# Checking if the Mips.abiflags were correctly emitted.
+# CHECK-OBJ:       Section {
+# CHECK-OBJ:         Index: 5
+# CHECK-OBJ-LABEL:   Name: .MIPS.abiflags (12)
+# CHECK-OBJ:         Type: SHT_MIPS_ABIFLAGS (0x7000002A)
+# CHECK-OBJ:          Flags [ (0x2)
+# CHECK-OBJ:           SHF_ALLOC (0x2)
+# CHECK-OBJ:         ]
+# CHECK-OBJ:         Address: 0x0
+# CHECK-OBJ:         Size: 24
+# CHECK-OBJ:         Link: 0
+# CHECK-OBJ:         Info: 0
+# CHECK-OBJ:         AddressAlignment: 8
+# CHECK-OBJ:         EntrySize: 24
+# CHECK-OBJ:         Relocations [
+# CHECK-OBJ:         ]
+# CHECK-OBJ:         SectionData (
+# CHECK-OBJ:           0000: 00002003 01010001 00000000 00000000  |.. .............|
+# CHECK-OBJ:           0010: 00000001 00000000                    |........|
+# CHECK-OBJ:         )
+# CHECK-OBJ-LABEL: }
+
+        .module fp=32
+        .set fp=64
+# FIXME: Test should include gnu_attributes directive when implemented.
+#        An explicit .gnu_attribute must be checked against the effective
+#        command line options and any inconsistencies reported via a warning.
diff --git a/test/MC/Mips/mips32r3/invalid-mips64r2.s b/test/MC/Mips/mips32r3/invalid-mips64r2.s
new file mode 100644
index 00000000000..0f007e27748
--- /dev/null
+++ b/test/MC/Mips/mips32r3/invalid-mips64r2.s
@@ -0,0 +1,10 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding \
+# RUN:     -mcpu=mips32r3 2>%t1
+# RUN: FileCheck %s < %t1
+
+	.set noat
+	dsbh	$v1,$t6    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+	dshd	$v0,$sp    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+
diff --git a/test/MC/Mips/mips32r3/invalid.s b/test/MC/Mips/mips32r3/invalid.s
new file mode 100644
index 00000000000..f67f4c55ecb
--- /dev/null
+++ b/test/MC/Mips/mips32r3/invalid.s
@@ -0,0 +1,10 @@
+# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g.
+# invalid set of operands or operand's restrictions not met).
+
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r3 2>%t1
+# RUN: FileCheck %s < %t1 -check-prefix=ASM
+
+        .text
+        .set noreorder
+        jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
+        jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
diff --git a/test/MC/Mips/mips32r3/valid-xfail.s b/test/MC/Mips/mips32r3/valid-xfail.s
new file mode 100644
index 00000000000..b0fc3a1d23f
--- /dev/null
+++ b/test/MC/Mips/mips32r3/valid-xfail.s
@@ -0,0 +1,308 @@
+# Instructions that should be valid but currently fail for known reasons (e.g.
+# they aren't implemented yet).
+# This test is set up to XPASS if any instruction generates an encoding.
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 | not FileCheck %s
+# CHECK-NOT: encoding
+# XFAIL: *
+
+        .set noat
+        abs.ps          $f22,$f8
+        absq_s.ph       $8,$a0
+        absq_s.qb       $15,$s1
+        absq_s.w        $s3,$ra
+        add.ps          $f25,$f27,$f13
+        addq.ph         $s1,$15,$at
+        addq_s.ph       $s3,$s6,$s2
+        addq_s.w        $a2,$8,$at
+        addqh.ph        $s4,$14,$s1
+        addqh.w         $s7,$s7,$k1
+        addqh_r.ph      $sp,$25,$s8
+        addqh_r.w       $8,$v1,$zero
+        addsc           $s8,$15,$12
+        addu.ph         $a2,$14,$s3
+        addu.qb         $s6,$v1,$v1
+        addu_s.ph       $a3,$s3,$gp
+        addu_s.qb       $s4,$s8,$s1
+        adduh.qb        $a1,$a1,$at
+        adduh_r.qb      $a0,$9,$12
+        addwc           $k0,$s6,$s7
+        alnv.ps         $f12,$f18,$f30,$12
+        and.v           $w10,$w25,$w29
+        bitrev          $14,$at
+        bmnz.v          $w15,$w2,$w28
+        bmz.v           $w13,$w11,$w21
+        bsel.v          $w28,$w7,$w0
+        c.eq.d          $fcc1,$f15,$f15
+        c.eq.ps         $fcc5,$f0,$f9
+        c.eq.s          $fcc5,$f24,$f17
+        c.f.d           $fcc4,$f11,$f21
+        c.f.ps          $fcc6,$f11,$f11
+        c.f.s           $fcc4,$f30,$f7
+        c.le.d          $fcc4,$f18,$f1
+        c.le.ps         $fcc1,$f7,$f20
+        c.le.s          $fcc6,$f24,$f4
+        c.lt.d          $fcc3,$f9,$f3
+        c.lt.ps         $f19,$f5
+        c.lt.s          $fcc2,$f17,$f14
+        c.nge.d         $fcc5,$f21,$f16
+        c.nge.ps        $f1,$f26
+        c.nge.s         $fcc3,$f11,$f8
+        c.ngl.ps        $f21,$f30
+        c.ngl.s         $fcc2,$f31,$f23
+        c.ngle.ps       $fcc7,$f12,$f20
+        c.ngle.s        $fcc2,$f18,$f23
+        c.ngt.d         $fcc4,$f24,$f7
+        c.ngt.ps        $fcc5,$f30,$f6
+        c.ngt.s         $fcc5,$f8,$f13
+        c.ole.d         $fcc2,$f16,$f31
+        c.ole.ps        $fcc7,$f21,$f8
+        c.ole.s         $fcc3,$f7,$f20
+        c.olt.d         $fcc4,$f19,$f28
+        c.olt.ps        $fcc3,$f7,$f16
+        c.olt.s         $fcc6,$f20,$f7
+        c.seq.d         $fcc4,$f31,$f7
+        c.seq.ps        $fcc6,$f31,$f14
+        c.seq.s         $fcc7,$f1,$f25
+        c.sf.ps         $fcc6,$f4,$f6
+        c.ueq.d         $fcc4,$f13,$f25
+        c.ueq.ps        $fcc1,$f5,$f29
+        c.ueq.s         $fcc6,$f3,$f30
+        c.ule.d         $fcc7,$f25,$f18
+        c.ule.ps        $fcc6,$f17,$f3
+        c.ule.s         $fcc7,$f21,$f30
+        c.ult.d         $fcc6,$f6,$f17
+        c.ult.ps        $fcc7,$f14,$f0
+        c.ult.s         $fcc7,$f24,$f10
+        c.un.d          $fcc6,$f23,$f24
+        c.un.ps         $fcc4,$f2,$f26
+        c.un.s          $fcc1,$f30,$f4
+        ceil.l.d        $f1,$f3
+        ceil.l.s        $f18,$f13
+        cfcmsa          $s6,$19
+        cmp.eq.ph       $s7,$14
+        cmp.le.ph       $8,$14
+        cmp.lt.ph       $k0,$sp
+        cmpgdu.eq.qb    $s3,$zero,$k0
+        cmpgdu.le.qb    $v1,$15,$s2
+        cmpgdu.lt.qb    $s0,$gp,$sp
+        cmpgu.eq.qb     $14,$s6,$s8
+        cmpgu.le.qb     $9,$a3,$s4
+        cmpgu.lt.qb     $sp,$at,$8
+        cmpu.eq.qb      $v0,$24
+        cmpu.le.qb      $s1,$a1
+        cmpu.lt.qb      $at,$a3
+        ctcmsa          $31,$s7
+        cvt.d.l         $f4,$f16
+        cvt.ps.s        $f3,$f18,$f19
+        cvt.s.l         $f15,$f30
+        cvt.s.pl        $f30,$f1
+        cvt.s.pu        $f14,$f25
+        dmt $k0
+        dpa.w.ph        $ac1,$s7,$k0
+        dpaq_s.w.ph     $ac2,$a0,$13
+        dpaq_sa.l.w     $ac0,$a2,$14
+        dpaqx_s.w.ph    $ac3,$a0,$24
+        dpaqx_sa.w.ph   $ac1,$zero,$s5
+        dpau.h.qbl      $ac1,$10,$24
+        dpau.h.qbr      $ac1,$s7,$s6
+        dpax.w.ph       $ac3,$a0,$k0
+        dps.w.ph        $ac1,$a3,$a1
+        dpsq_s.w.ph     $ac0,$gp,$k0
+        dpsq_sa.l.w     $ac0,$a3,$15
+        dpsqx_s.w.ph    $ac3,$13,$a3
+        dpsqx_sa.w.ph   $ac3,$sp,$s2
+        dpsu.h.qbl      $ac2,$14,$10
+        dpsu.h.qbr      $ac2,$a1,$s6
+        dpsx.w.ph       $ac0,$s7,$gp
+        dvpe            $s6
+        emt $8
+        evpe            $v0
+        extpdpv         $s6,$ac0,$s8
+        extpv           $13,$ac0,$14
+        extrv.w         $8,$ac3,$at
+        extrv_r.w       $8,$ac1,$s6
+        extrv_rs.w      $gp,$ac1,$s6
+        extrv_s.h       $s2,$ac1,$14
+        fclass.d        $w14,$w27
+        fclass.w        $w19,$w28
+        fexupl.d        $w10,$w29
+        fexupl.w        $w12,$w27
+        fexupr.d        $w31,$w15
+        fexupr.w        $w29,$w12
+        ffint_s.d       $w1,$w30
+        ffint_s.w       $w16,$w14
+        ffint_u.d       $w23,$w18
+        ffint_u.w       $w19,$w12
+        ffql.d          $w2,$w3
+        ffql.w          $w9,$w0
+        ffqr.d          $w25,$w24
+        ffqr.w          $w10,$w6
+        fill.b          $w9,$v1
+        fill.h          $w9,$8
+        fill.w          $w31,$15
+        flog2.d         $w12,$w16
+        flog2.w         $w19,$w23
+        floor.l.d       $f26,$f7
+        floor.l.s       $f12,$f5
+        fork            $s2,$8,$a0
+        frcp.d          $w12,$w4
+        frcp.w          $w30,$w8
+        frint.d         $w20,$w8
+        frint.w         $w11,$w29
+        frsqrt.d        $w29,$w2
+        frsqrt.w        $w9,$w8
+        fsqrt.d         $w3,$w1
+        fsqrt.w         $w5,$w15
+        ftint_s.d       $w31,$w26
+        ftint_s.w       $w27,$w14
+        ftint_u.d       $w5,$w31
+        ftint_u.w       $w12,$w29
+        ftrunc_s.d      $w4,$w22
+        ftrunc_s.w      $w24,$w7
+        ftrunc_u.d      $w20,$w25
+        ftrunc_u.w      $w7,$w26
+        insv            $s2,$at
+        iret
+        lbe             $14,122($9)
+        lbue            $11,-108($10)
+        lbux            $9,$14($v0)
+        lhe             $s6,219($v1)
+        lhue            $gp,118($11)
+        lhx             $sp,$k0($15)
+        lle             $gp,-237($ra)
+        lwe             $ra,-145($14)
+        lwle            $11,-42($11)
+        lwre            $sp,-152($24)
+        lwx             $12,$12($s4)
+        madd.ps         $f22,$f3,$f14,$f3
+        maq_s.w.phl     $ac2,$25,$11
+        maq_s.w.phr     $ac0,$10,$25
+        maq_sa.w.phl    $ac3,$a1,$v1
+        maq_sa.w.phr    $ac1,$at,$10
+        mfgc0           $s6,c0_datahi1
+        mflo            $9,$ac2
+        modsub          $a3,$12,$a3
+        mov.ps          $f22,$f17
+        move.v          $w8,$w17
+        movf.ps         $f10,$f28,$fcc6
+        movn.ps         $f31,$f31,$s3
+        movt.ps         $f20,$f25,$fcc2
+        movz.ps         $f18,$f17,$ra
+        msub            $ac2,$sp,$14
+        msub.ps         $f12,$f14,$f29,$f17
+        msubu           $ac2,$a1,$24
+        mtc0            $9,c0_datahi1
+        mtgc0           $s4,$21,7
+        mthi            $v0,$ac1
+        mthlip          $a3,$ac0
+        mul.ph          $s4,$24,$s0
+        mul.ps          $f14,$f0,$f16
+        mul_s.ph        $10,$14,$15
+        muleq_s.w.phl   $11,$s4,$s4
+        muleq_s.w.phr   $s6,$a0,$s8
+        muleu_s.ph.qbl  $a2,$14,$8
+        muleu_s.ph.qbr  $a1,$ra,$9
+        mulq_rs.ph      $s2,$14,$15
+        mulq_rs.w       $at,$s4,$25
+        mulq_s.ph       $s0,$k1,$15
+        mulq_s.w        $9,$a3,$s0
+        mulsa.w.ph      $ac1,$s4,$s6
+        mulsaq_s.w.ph   $ac0,$ra,$s2
+        neg.ps          $f19,$f13
+        nloc.b          $w12,$w30
+        nloc.d          $w16,$w7
+        nloc.h          $w21,$w17
+        nloc.w          $w17,$w16
+        nlzc.b          $w12,$w7
+        nlzc.d          $w14,$w14
+        nlzc.h          $w24,$w24
+        nlzc.w          $w10,$w4
+        nmadd.ps        $f27,$f4,$f9,$f25
+        nmsub.ps        $f6,$f12,$f14,$f17
+        nor.v           $w20,$w20,$w15
+        or.v            $w13,$w23,$w12
+        packrl.ph       $ra,$24,$14
+        pcnt.b          $w30,$w15
+        pcnt.d          $w5,$w16
+        pcnt.h          $w20,$w24
+        pcnt.w          $w22,$w20
+        pick.ph         $ra,$a2,$gp
+        pick.qb         $11,$a0,$gp
+        pll.ps          $f25,$f9,$f30
+        plu.ps          $f1,$f26,$f29
+        preceq.w.phl    $s8,$gp
+        preceq.w.phr    $s5,$15
+        precequ.ph.qbl  $s7,$ra
+        precequ.ph.qbla $a0,$9
+        precequ.ph.qbr  $ra,$s3
+        precequ.ph.qbra $24,$8
+        preceu.ph.qbl   $sp,$8
+        preceu.ph.qbla  $s6,$11
+        preceu.ph.qbr   $gp,$s1
+        preceu.ph.qbra  $k1,$s0
+        precr.qb.ph     $v0,$12,$s8
+        precrq.ph.w     $14,$s8,$24
+        precrq.qb.ph    $a2,$12,$12
+        precrq_rs.ph.w  $a1,$k0,$a3
+        precrqu_s.qb.ph $zero,$gp,$s5
+        pul.ps          $f9,$f30,$f26
+        puu.ps          $f24,$f9,$f2
+        raddu.w.qb      $25,$s3
+        rdpgpr          $s3,$9
+        recip.d         $f19,$f6
+        recip.s         $f3,$f30
+        repl.ph         $at,-307
+        replv.ph        $v1,$s7
+        replv.qb        $25,$12
+        rorv            $13,$a3,$s5
+        round.l.d       $f12,$f1
+        round.l.s       $f25,$f5
+        rsqrt.d         $f3,$f28
+        rsqrt.s         $f4,$f8
+        sbe             $s7,33($s1)
+        sce             $sp,189($10)
+        she             $24,105($v0)
+        shilo           $ac1,26
+        shilov          $ac2,$10
+        shllv.ph        $10,$s0,$s0
+        shllv.qb        $gp,$v1,$zero
+        shllv_s.ph      $k1,$at,$13
+        shllv_s.w       $s1,$ra,$k0
+        shrav.ph        $25,$s2,$s1
+        shrav.qb        $zero,$24,$11
+        shrav_r.ph      $s3,$11,$25
+        shrav_r.qb      $a0,$sp,$s5
+        shrav_r.w       $s7,$s4,$s6
+        shrlv.ph        $14,$10,$9
+        shrlv.qb        $a2,$s2,$11
+        sub.ps          $f5,$f14,$f26
+        subq.ph         $ra,$9,$s8
+        subq_s.ph       $13,$s8,$s5
+        subq_s.w        $k1,$a2,$a3
+        subqh.ph        $10,$at,$9
+        subqh.w         $v0,$a2,$zero
+        subqh_r.ph      $a0,$12,$s6
+        subqh_r.w       $10,$a2,$gp
+        subu.ph         $9,$s6,$s4
+        subu.qb         $s6,$a2,$s6
+        subu_s.ph       $v1,$a1,$s3
+        subu_s.qb       $s1,$at,$ra
+        subuh.qb        $zero,$gp,$gp
+        subuh_r.qb      $s4,$s8,$s6
+        swe             $24,94($k0)
+        swle            $v1,-209($gp)
+        swre            $k0,-202($s2)
+        tlbginv
+        tlbginvf
+        tlbgp
+        tlbgr
+        tlbgwi
+        tlbgwr
+        tlbinv
+        tlbinvf
+        trunc.l.d       $f23,$f23
+        trunc.l.s       $f28,$f31
+        wrpgpr          $zero,$13
+        xor.v           $w20,$w21,$w30
+        yield           $v1,$s0
diff --git a/test/MC/Mips/mips32r3/valid.s b/test/MC/Mips/mips32r3/valid.s
new file mode 100644
index 00000000000..4280de59939
--- /dev/null
+++ b/test/MC/Mips/mips32r3/valid.s
@@ -0,0 +1,236 @@
+# Instructions that are valid
+#
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 | FileCheck %s
+
+        .set noat
+        abs.d     $f7,$f25             # CHECK: encoding:
+        abs.s     $f9,$f16
+        add       $s7,$s2,$a1
+        add       $9,$14,15176         # CHECK: addi $9, $14, 15176   # encoding: [0x21,0xc9,0x3b,0x48]
+        add       $24,-7193            # CHECK: addi $24, $24, -7193  # encoding: [0x23,0x18,0xe3,0xe7]
+        add.d     $f1,$f7,$f29
+        add.s     $f8,$f21,$f24
+        addi      $13,$9,26322
+        addi      $8,$8,~1             # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
+        addu      $9,$a0,$a2
+        addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
+        and       $s7,$v0,$12
+        and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
+        bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
+        bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
+        bc1fl     $fcc0,4688           # CHECK: bc1fl 4688      # encoding: [0x45,0x02,0x04,0x94]
+        bc1fl     4688                 # CHECK: bc1fl 4688      # encoding: [0x45,0x02,0x04,0x94]
+        bc1fl     $fcc7,27             # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06]
+        bc1t      $fcc0, 4             # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
+        bc1t      $fcc1, 4             # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
+        bc1t      4                    # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
+        bc1tl     $fcc0,4688           # CHECK: bc1tl 4688      # encoding: [0x45,0x03,0x04,0x94]
+        bc1tl     4688                 # CHECK: bc1tl 4688      # encoding: [0x45,0x03,0x04,0x94]
+        bc1tl     $fcc7,27             # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06]
+        bal       21100                # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
+        bgezal    $0, 21100            # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
+        bgezal    $6, 21100            # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
+        bltzal    $6, 21100            # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
+        beql      $14,$s3,12544        # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40]
+        bgezall   $12,7293             # CHECK: bgezall $12, 7293    # encoding: [0x05,0x93,0x07,0x1f]
+        bgezl     $4,-6858             # CHECK: bgezl $4, -6858      # encoding: [0x04,0x83,0xf9,0x4d]
+        bgtzl     $10,-3738            # CHECK: bgtzl $10, -3738     # encoding: [0x5d,0x40,0xfc,0x59]
+        blezl     $6,2974              # CHECK: blezl $6, 2974       # encoding: [0x58,0xc0,0x02,0xe7]
+        bltzall   $6,488               # CHECK: bltzall $6, 488      # encoding: [0x04,0xd2,0x00,0x7a]
+        bltzl     $s1,-9964            # CHECK: bltzl $17, -9964     # encoding: [0x06,0x22,0xf6,0x45]
+        bnel      $gp,$s4,5107         # CHECK: bnel $gp, $20, 5107  # encoding: [0x57,0x94,0x04,0xfc]
+        cache     1, 8($5)             # CHECK: cache 1, 8($5)   # encoding: [0xbc,0xa1,0x00,0x08]
+        c.ngl.d   $f29,$f29
+        c.ngle.d  $f0,$f16
+        c.sf.d    $f30,$f0
+        c.sf.s    $f14,$f22
+        ceil.w.d  $f11,$f25
+        ceil.w.s  $f6,$f20
+        cfc1      $s1,$21
+        clo       $11,$a1              # CHECK: clo $11, $5   # encoding: [0x70,0xab,0x58,0x21]
+        clz       $sp,$gp              # CHECK: clz $sp, $gp  # encoding: [0x73,0x9d,0xe8,0x20]
+        ctc1      $a2,$26
+        cvt.d.s   $f22,$f28
+        cvt.d.w   $f26,$f11
+        cvt.l.d   $f24,$f15
+        cvt.l.s   $f11,$f29
+        cvt.s.d   $f26,$f8
+        cvt.s.w   $f22,$f15
+        cvt.w.d   $f20,$f14
+        cvt.w.s   $f20,$f24
+        deret
+        di        $s8                  # CHECK: di  $fp       # encoding: [0x41,0x7e,0x60,0x00]
+        di                             # CHECK: di            # encoding: [0x41,0x60,0x60,0x00]
+        div       $zero,$25,$11
+        div.d     $f29,$f20,$f27
+        div.s     $f4,$f5,$f15
+        divu      $zero,$25,$15
+        ehb                            # CHECK: ehb # encoding:  [0x00,0x00,0x00,0xc0]
+        ei        $14                  # CHECK: ei  $14       # encoding: [0x41,0x6e,0x60,0x20]
+        ei                             # CHECK: ei            # encoding: [0x41,0x60,0x60,0x20]
+        eret
+        floor.w.d $f14,$f11
+        floor.w.s $f8,$f9
+        jr.hb     $4                   # CHECK: jr.hb  $4 # encoding: [0x00,0x80,0x04,0x08]
+        jalr.hb   $4                   # CHECK: jalr.hb  $4 # encoding: [0x00,0x80,0xfc,0x09]
+        jalr.hb   $4, $5               # CHECK: jalr.hb  $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
+        lb        $24,-14515($10)
+        lbu       $8,30195($v1)
+        ldc1      $f11,16391($s0)
+        ldc2      $8,-21181($at)        # CHECK: ldc2 $8, -21181($1)   # encoding: [0xd8,0x28,0xad,0x43]
+        ldxc1     $f8,$s7($15)
+        lh        $11,-8556($s5)
+        lhu       $s3,-22851($v0)
+        li        $at,-29773
+        li        $zero,-29889
+        ll        $v0,-7321($s2)       # CHECK: ll $2, -7321($18)     # encoding: [0xc2,0x42,0xe3,0x67]
+        luxc1     $f19,$s6($s5)
+        lw        $8,5674($a1)
+        lwc1      $f16,10225($k0)
+        lwc2      $18,-841($a2)        # CHECK: lwc2 $18, -841($6)     # encoding: [0xc8,0xd2,0xfc,0xb7]
+        lwl       $s4,-4231($15)
+        lwr       $zero,-19147($gp)
+        lwxc1     $f12,$s1($s8)
+        madd      $s6,$13
+        madd      $zero,$9
+        madd.d    $f18,$f19,$f26,$f20
+        madd.s    $f1,$f31,$f19,$f25
+        maddu     $s3,$gp
+        maddu     $24,$s2
+        mfc0      $a2,$14,1
+        mfc1      $a3,$f27
+        mfhc1     $s8,$f24
+        mfhi      $s3
+        mfhi      $sp
+        mflo      $s1
+        mov.d     $f20,$f14
+        mov.s     $f2,$f27
+        move      $s8,$a0
+        move      $25,$a2
+        movf      $gp,$8,$fcc7
+        movf.d    $f6,$f11,$fcc5
+        movf.s    $f23,$f5,$fcc6
+        movn      $v1,$s1,$s0
+        movn.d    $f27,$f21,$k0
+        movn.s    $f12,$f0,$s7
+        movt      $zero,$s4,$fcc5
+        movt.d    $f0,$f2,$fcc0
+        movt.s    $f30,$f2,$fcc1
+        movz      $a1,$s6,$9
+        movz.d    $f12,$f29,$9
+        movz.s    $f25,$f7,$v1
+        msub      $s7,$k1
+        msub.d    $f10,$f1,$f31,$f18
+        msub.s    $f12,$f19,$f10,$f16
+        msubu     $15,$a1
+        mtc0      $9,$29,3
+        mtc1      $s8,$f9
+        mthc1     $zero,$f16
+        mthi      $s1
+        mtlo      $sp
+        mtlo      $25
+        mul       $s0,$s4,$at
+        mul.d     $f20,$f20,$f16
+        mul.s     $f30,$f10,$f2
+        mult      $sp,$s4
+        mult      $sp,$v0
+        multu     $gp,$k0
+        multu     $9,$s2
+        negu      $2                   # CHECK: negu $2, $2            # encoding: [0x00,0x02,0x10,0x23]
+        negu      $2,$3                # CHECK: negu $2, $3            # encoding: [0x00,0x03,0x10,0x23]
+        neg.d     $f27,$f18
+        neg.s     $f1,$f15
+        nmadd.d   $f18,$f9,$f14,$f19
+        nmadd.s   $f0,$f5,$f25,$f12
+        nmsub.d   $f30,$f8,$f16,$f30
+        nmsub.s   $f1,$f24,$f19,$f4
+        nop
+        nor       $a3,$zero,$a3
+        or        $12,$s0,$sp
+        or        $2, 4                # CHECK: ori $2, $2, 4           # encoding: [0x34,0x42,0x00,0x04]
+        pause                          # CHECK: pause # encoding:  [0x00,0x00,0x01,0x40]
+        pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
+        # FIXME: Use the code generator in order to print the .set directives
+        #        instead of the instruction printer.
+        rdhwr     $sp,$11              # CHECK:      .set  push
+                                       # CHECK-NEXT: .set  mips32r2
+                                       # CHECK-NEXT: rdhwr $sp, $11
+                                       # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
+        rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
+        rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]
+        rotrv     $1,$14,$15           # CHECK: rotrv $1, $14, $15      # encoding: [0x01,0xee,0x08,0x46]
+        round.w.d $f6,$f4
+        round.w.s $f27,$f28
+        sb        $s6,-19857($14)
+        sc        $15,18904($s3)       # CHECK: sc $15, 18904($19)     # encoding: [0xe2,0x6f,0x49,0xd8]
+        sdbbp                          # CHECK: sdbbp                  # encoding: [0x70,0x00,0x00,0x3f]
+        sdbbp     34                   # CHECK: sdbbp 34               # encoding: [0x70,0x00,0x08,0xbf]
+        sdc1      $f31,30574($13)
+        sdc2      $20,23157($s2)       # CHECK: sdc2 $20, 23157($18)   # encoding: [0xfa,0x54,0x5a,0x75]
+        sdxc1     $f11,$10($14)
+        seb       $25,$15
+        seh       $v1,$12
+        sh        $14,-6704($15)
+        sll       $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
+        sll       $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
+        sll       $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
+        sllv      $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
+        slt       $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
+        slti      $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
+        sltiu     $25,$25,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
+        sltu      $s4,$s5,$11          # CHECK: sltu  $20, $21, $11    # encoding: [0x02,0xab,0xa0,0x2b]
+        sltu      $24,$25,-15531       # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
+        sqrt.d    $f17,$f22
+        sqrt.s    $f0,$f1
+        sra       $s1,15               # CHECK: sra $17, $17, 15       # encoding: [0x00,0x11,0x8b,0xc3]
+        sra       $s1,$s7,15           # CHECK: sra $17, $23, 15       # encoding: [0x00,0x17,0x8b,0xc3]
+        sra       $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
+        srav      $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
+        srl       $2,7                 # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+        srl       $2,$2,7              # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+        srl       $25,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
+        srlv      $25,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
+        ssnop                          # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
+        sub       $s6,$s3,$12
+        sub       $22,$17,-3126        # CHECK: addi $22, $17, 3126    # encoding: [0x22,0x36,0x0c,0x36]
+        sub       $13,6512             # CHECK: addi $13, $13, -6512   # encoding: [0x21,0xad,0xe6,0x90]
+        sub.d     $f18,$f3,$f17
+        sub.s     $f23,$f22,$f22
+        subu      $sp,$s6,$s6
+        suxc1     $f12,$k1($13)
+        sw        $ra,-10160($sp)
+        swc1      $f6,-8465($24)
+        swc2      $25,24880($s0)       # CHECK: swc2 $25, 24880($16)   # encoding: [0xea,0x19,0x61,0x30]
+        swl       $15,13694($s3)
+        swr       $s1,-26590($14)
+        swxc1     $f19,$12($k0)
+        sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+        sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+        teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
+        teq       $5,$7,620            # CHECK: teq $5, $7, 620        # encoding: [0x00,0xa7,0x9b,0x34]
+        teqi      $s5,-17504
+        tge       $7,$10               # CHECK: tge $7, $10            # encoding: [0x00,0xea,0x00,0x30]
+        tge       $5,$19,340           # CHECK: tge $5, $19, 340       # encoding: [0x00,0xb3,0x55,0x30]
+        tgei      $s1,5025
+        tgeiu     $sp,-28621
+        tgeu      $22,$28              # CHECK: tgeu $22, $gp          # encoding: [0x02,0xdc,0x00,0x31]
+        tgeu      $20,$14,379          # CHECK: tgeu $20, $14, 379     # encoding: [0x02,0x8e,0x5e,0xf1]
+        tlbp                           # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+        tlbr                           # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+        tlbwi                          # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+        tlbwr                          # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
+        tlt       $15,$13              # CHECK: tlt $15, $13           # encoding: [0x01,0xed,0x00,0x32]
+        tlt       $2,$19,133           # CHECK: tlt $2, $19, 133       # encoding: [0x00,0x53,0x21,0x72]
+        tlti      $14,-21059
+        tltiu     $ra,-5076
+        tltu      $11,$16              # CHECK: tltu $11, $16          # encoding: [0x01,0x70,0x00,0x33]
+        tltu      $16,$29,1016         # CHECK: tltu $16, $sp, 1016    # encoding: [0x02,0x1d,0xfe,0x33]
+        tne       $6,$17               # CHECK: tne $6, $17            # encoding: [0x00,0xd1,0x00,0x36]
+        tne       $7,$8,885            # CHECK: tne $7, $8, 885        # encoding: [0x00,0xe8,0xdd,0x76]
+        tnei      $12,-29647
+        trunc.w.d $f22,$f15
+        trunc.w.s $f28,$f30
+        wsbh      $k1,$9
+        xor       $s2,$a0,$s8
+        synci     -15842($a2)          # CHECK: synci -15842($6)        # encoding: [0x04,0xdf,0xc2,0x1e]
diff --git a/test/MC/Mips/mips32r5/abiflags.s b/test/MC/Mips/mips32r5/abiflags.s
new file mode 100644
index 00000000000..fa5befeaddb
--- /dev/null
+++ b/test/MC/Mips/mips32r5/abiflags.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r5 | \
+# RUN:   FileCheck %s -check-prefix=CHECK-ASM
+#
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r5 -filetype=obj -o - | \
+# RUN:   llvm-readobj -sections -section-data -section-relocations - | \
+# RUN:     FileCheck %s -check-prefix=CHECK-OBJ
+
+# CHECK-ASM: .module fp=32
+# CHECK-ASM: .set fp=64
+
+# Checking if the Mips.abiflags were correctly emitted.
+# CHECK-OBJ:       Section {
+# CHECK-OBJ:         Index: 5
+# CHECK-OBJ-LABEL:   Name: .MIPS.abiflags (12)
+# CHECK-OBJ:         Type: SHT_MIPS_ABIFLAGS (0x7000002A)
+# CHECK-OBJ:          Flags [ (0x2)
+# CHECK-OBJ:           SHF_ALLOC (0x2)
+# CHECK-OBJ:         ]
+# CHECK-OBJ:         Address: 0x0
+# CHECK-OBJ:         Size: 24
+# CHECK-OBJ:         Link: 0
+# CHECK-OBJ:         Info: 0
+# CHECK-OBJ:         AddressAlignment: 8
+# CHECK-OBJ:         EntrySize: 24
+# CHECK-OBJ:         Relocations [
+# CHECK-OBJ:         ]
+# CHECK-OBJ:         SectionData (
+# CHECK-OBJ:           0000: 00002005 01010001 00000000 00000000  |.. .............|
+# CHECK-OBJ:           0010: 00000001 00000000                    |........|
+# CHECK-OBJ:         )
+# CHECK-OBJ-LABEL: }
+
+        .module fp=32
+        .set fp=64
+# FIXME: Test should include gnu_attributes directive when implemented.
+#        An explicit .gnu_attribute must be checked against the effective
+#        command line options and any inconsistencies reported via a warning.
diff --git a/test/MC/Mips/mips32r5/invalid-mips64r2.s b/test/MC/Mips/mips32r5/invalid-mips64r2.s
new file mode 100644
index 00000000000..ed8f5c743b9
--- /dev/null
+++ b/test/MC/Mips/mips32r5/invalid-mips64r2.s
@@ -0,0 +1,10 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding \
+# RUN:     -mcpu=mips32r5 2>%t1
+# RUN: FileCheck %s < %t1
+
+	.set noat
+	dsbh	$v1,$t6    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+	dshd	$v0,$sp    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+
diff --git a/test/MC/Mips/mips32r5/invalid.s b/test/MC/Mips/mips32r5/invalid.s
new file mode 100644
index 00000000000..fec30e1426c
--- /dev/null
+++ b/test/MC/Mips/mips32r5/invalid.s
@@ -0,0 +1,10 @@
+# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g.
+# invalid set of operands or operand's restrictions not met).
+
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r5 2>%t1
+# RUN: FileCheck %s < %t1 -check-prefix=ASM
+
+        .text
+        .set noreorder
+        jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
+        jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
diff --git a/test/MC/Mips/mips32r5/valid-xfail.s b/test/MC/Mips/mips32r5/valid-xfail.s
new file mode 100644
index 00000000000..a821dddb85c
--- /dev/null
+++ b/test/MC/Mips/mips32r5/valid-xfail.s
@@ -0,0 +1,308 @@
+# Instructions that should be valid but currently fail for known reasons (e.g.
+# they aren't implemented yet).
+# This test is set up to XPASS if any instruction generates an encoding.
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r5 | not FileCheck %s
+# CHECK-NOT: encoding
+# XFAIL: *
+
+        .set noat
+        abs.ps          $f22,$f8
+        absq_s.ph       $8,$a0
+        absq_s.qb       $15,$s1
+        absq_s.w        $s3,$ra
+        add.ps          $f25,$f27,$f13
+        addq.ph         $s1,$15,$at
+        addq_s.ph       $s3,$s6,$s2
+        addq_s.w        $a2,$8,$at
+        addqh.ph        $s4,$14,$s1
+        addqh.w         $s7,$s7,$k1
+        addqh_r.ph      $sp,$25,$s8
+        addqh_r.w       $8,$v1,$zero
+        addsc           $s8,$15,$12
+        addu.ph         $a2,$14,$s3
+        addu.qb         $s6,$v1,$v1
+        addu_s.ph       $a3,$s3,$gp
+        addu_s.qb       $s4,$s8,$s1
+        adduh.qb        $a1,$a1,$at
+        adduh_r.qb      $a0,$9,$12
+        addwc           $k0,$s6,$s7
+        alnv.ps         $f12,$f18,$f30,$12
+        and.v           $w10,$w25,$w29
+        bitrev          $14,$at
+        bmnz.v          $w15,$w2,$w28
+        bmz.v           $w13,$w11,$w21
+        bsel.v          $w28,$w7,$w0
+        c.eq.d          $fcc1,$f15,$f15
+        c.eq.ps         $fcc5,$f0,$f9
+        c.eq.s          $fcc5,$f24,$f17
+        c.f.d           $fcc4,$f11,$f21
+        c.f.ps          $fcc6,$f11,$f11
+        c.f.s           $fcc4,$f30,$f7
+        c.le.d          $fcc4,$f18,$f1
+        c.le.ps         $fcc1,$f7,$f20
+        c.le.s          $fcc6,$f24,$f4
+        c.lt.d          $fcc3,$f9,$f3
+        c.lt.ps         $f19,$f5
+        c.lt.s          $fcc2,$f17,$f14
+        c.nge.d         $fcc5,$f21,$f16
+        c.nge.ps        $f1,$f26
+        c.nge.s         $fcc3,$f11,$f8
+        c.ngl.ps        $f21,$f30
+        c.ngl.s         $fcc2,$f31,$f23
+        c.ngle.ps       $fcc7,$f12,$f20
+        c.ngle.s        $fcc2,$f18,$f23
+        c.ngt.d         $fcc4,$f24,$f7
+        c.ngt.ps        $fcc5,$f30,$f6
+        c.ngt.s         $fcc5,$f8,$f13
+        c.ole.d         $fcc2,$f16,$f31
+        c.ole.ps        $fcc7,$f21,$f8
+        c.ole.s         $fcc3,$f7,$f20
+        c.olt.d         $fcc4,$f19,$f28
+        c.olt.ps        $fcc3,$f7,$f16
+        c.olt.s         $fcc6,$f20,$f7
+        c.seq.d         $fcc4,$f31,$f7
+        c.seq.ps        $fcc6,$f31,$f14
+        c.seq.s         $fcc7,$f1,$f25
+        c.sf.ps         $fcc6,$f4,$f6
+        c.ueq.d         $fcc4,$f13,$f25
+        c.ueq.ps        $fcc1,$f5,$f29
+        c.ueq.s         $fcc6,$f3,$f30
+        c.ule.d         $fcc7,$f25,$f18
+        c.ule.ps        $fcc6,$f17,$f3
+        c.ule.s         $fcc7,$f21,$f30
+        c.ult.d         $fcc6,$f6,$f17
+        c.ult.ps        $fcc7,$f14,$f0
+        c.ult.s         $fcc7,$f24,$f10
+        c.un.d          $fcc6,$f23,$f24
+        c.un.ps         $fcc4,$f2,$f26
+        c.un.s          $fcc1,$f30,$f4
+        ceil.l.d        $f1,$f3
+        ceil.l.s        $f18,$f13
+        cfcmsa          $s6,$19
+        cmp.eq.ph       $s7,$14
+        cmp.le.ph       $8,$14
+        cmp.lt.ph       $k0,$sp
+        cmpgdu.eq.qb    $s3,$zero,$k0
+        cmpgdu.le.qb    $v1,$15,$s2
+        cmpgdu.lt.qb    $s0,$gp,$sp
+        cmpgu.eq.qb     $14,$s6,$s8
+        cmpgu.le.qb     $9,$a3,$s4
+        cmpgu.lt.qb     $sp,$at,$8
+        cmpu.eq.qb      $v0,$24
+        cmpu.le.qb      $s1,$a1
+        cmpu.lt.qb      $at,$a3
+        ctcmsa          $31,$s7
+        cvt.d.l         $f4,$f16
+        cvt.ps.s        $f3,$f18,$f19
+        cvt.s.l         $f15,$f30
+        cvt.s.pl        $f30,$f1
+        cvt.s.pu        $f14,$f25
+        dmt $k0
+        dpa.w.ph        $ac1,$s7,$k0
+        dpaq_s.w.ph     $ac2,$a0,$13
+        dpaq_sa.l.w     $ac0,$a2,$14
+        dpaqx_s.w.ph    $ac3,$a0,$24
+        dpaqx_sa.w.ph   $ac1,$zero,$s5
+        dpau.h.qbl      $ac1,$10,$24
+        dpau.h.qbr      $ac1,$s7,$s6
+        dpax.w.ph       $ac3,$a0,$k0
+        dps.w.ph        $ac1,$a3,$a1
+        dpsq_s.w.ph     $ac0,$gp,$k0
+        dpsq_sa.l.w     $ac0,$a3,$15
+        dpsqx_s.w.ph    $ac3,$13,$a3
+        dpsqx_sa.w.ph   $ac3,$sp,$s2
+        dpsu.h.qbl      $ac2,$14,$10
+        dpsu.h.qbr      $ac2,$a1,$s6
+        dpsx.w.ph       $ac0,$s7,$gp
+        dvpe            $s6
+        emt $8
+        evpe            $v0
+        extpdpv         $s6,$ac0,$s8
+        extpv           $13,$ac0,$14
+        extrv.w         $8,$ac3,$at
+        extrv_r.w       $8,$ac1,$s6
+        extrv_rs.w      $gp,$ac1,$s6
+        extrv_s.h       $s2,$ac1,$14
+        fclass.d        $w14,$w27
+        fclass.w        $w19,$w28
+        fexupl.d        $w10,$w29
+        fexupl.w        $w12,$w27
+        fexupr.d        $w31,$w15
+        fexupr.w        $w29,$w12
+        ffint_s.d       $w1,$w30
+        ffint_s.w       $w16,$w14
+        ffint_u.d       $w23,$w18
+        ffint_u.w       $w19,$w12
+        ffql.d          $w2,$w3
+        ffql.w          $w9,$w0
+        ffqr.d          $w25,$w24
+        ffqr.w          $w10,$w6
+        fill.b          $w9,$v1
+        fill.h          $w9,$8
+        fill.w          $w31,$15
+        flog2.d         $w12,$w16
+        flog2.w         $w19,$w23
+        floor.l.d       $f26,$f7
+        floor.l.s       $f12,$f5
+        fork            $s2,$8,$a0
+        frcp.d          $w12,$w4
+        frcp.w          $w30,$w8
+        frint.d         $w20,$w8
+        frint.w         $w11,$w29
+        frsqrt.d        $w29,$w2
+        frsqrt.w        $w9,$w8
+        fsqrt.d         $w3,$w1
+        fsqrt.w         $w5,$w15
+        ftint_s.d       $w31,$w26
+        ftint_s.w       $w27,$w14
+        ftint_u.d       $w5,$w31
+        ftint_u.w       $w12,$w29
+        ftrunc_s.d      $w4,$w22
+        ftrunc_s.w      $w24,$w7
+        ftrunc_u.d      $w20,$w25
+        ftrunc_u.w      $w7,$w26
+        insv            $s2,$at
+        iret
+        lbe             $14,122($9)
+        lbue            $11,-108($10)
+        lbux            $9,$14($v0)
+        lhe             $s6,219($v1)
+        lhue            $gp,118($11)
+        lhx             $sp,$k0($15)
+        lle             $gp,-237($ra)
+        lwe             $ra,-145($14)
+        lwle            $11,-42($11)
+        lwre            $sp,-152($24)
+        lwx             $12,$12($s4)
+        madd.ps         $f22,$f3,$f14,$f3
+        maq_s.w.phl     $ac2,$25,$11
+        maq_s.w.phr     $ac0,$10,$25
+        maq_sa.w.phl    $ac3,$a1,$v1
+        maq_sa.w.phr    $ac1,$at,$10
+        mfgc0           $s6,c0_datahi1
+        mflo            $9,$ac2
+        modsub          $a3,$12,$a3
+        mov.ps          $f22,$f17
+        move.v          $w8,$w17
+        movf.ps         $f10,$f28,$fcc6
+        movn.ps         $f31,$f31,$s3
+        movt.ps         $f20,$f25,$fcc2
+        movz.ps         $f18,$f17,$ra
+        msub            $ac2,$sp,$14
+        msub.ps         $f12,$f14,$f29,$f17
+        msubu           $ac2,$a1,$24
+        mtc0            $9,c0_datahi1
+        mtgc0           $s4,$21,7
+        mthi            $v0,$ac1
+        mthlip          $a3,$ac0
+        mul.ph          $s4,$24,$s0
+        mul.ps          $f14,$f0,$f16
+        mul_s.ph        $10,$14,$15
+        muleq_s.w.phl   $11,$s4,$s4
+        muleq_s.w.phr   $s6,$a0,$s8
+        muleu_s.ph.qbl  $a2,$14,$8
+        muleu_s.ph.qbr  $a1,$ra,$9
+        mulq_rs.ph      $s2,$14,$15
+        mulq_rs.w       $at,$s4,$25
+        mulq_s.ph       $s0,$k1,$15
+        mulq_s.w        $9,$a3,$s0
+        mulsa.w.ph      $ac1,$s4,$s6
+        mulsaq_s.w.ph   $ac0,$ra,$s2
+        neg.ps          $f19,$f13
+        nloc.b          $w12,$w30
+        nloc.d          $w16,$w7
+        nloc.h          $w21,$w17
+        nloc.w          $w17,$w16
+        nlzc.b          $w12,$w7
+        nlzc.d          $w14,$w14
+        nlzc.h          $w24,$w24
+        nlzc.w          $w10,$w4
+        nmadd.ps        $f27,$f4,$f9,$f25
+        nmsub.ps        $f6,$f12,$f14,$f17
+        nor.v           $w20,$w20,$w15
+        or.v            $w13,$w23,$w12
+        packrl.ph       $ra,$24,$14
+        pcnt.b          $w30,$w15
+        pcnt.d          $w5,$w16
+        pcnt.h          $w20,$w24
+        pcnt.w          $w22,$w20
+        pick.ph         $ra,$a2,$gp
+        pick.qb         $11,$a0,$gp
+        pll.ps          $f25,$f9,$f30
+        plu.ps          $f1,$f26,$f29
+        preceq.w.phl    $s8,$gp
+        preceq.w.phr    $s5,$15
+        precequ.ph.qbl  $s7,$ra
+        precequ.ph.qbla $a0,$9
+        precequ.ph.qbr  $ra,$s3
+        precequ.ph.qbra $24,$8
+        preceu.ph.qbl   $sp,$8
+        preceu.ph.qbla  $s6,$11
+        preceu.ph.qbr   $gp,$s1
+        preceu.ph.qbra  $k1,$s0
+        precr.qb.ph     $v0,$12,$s8
+        precrq.ph.w     $14,$s8,$24
+        precrq.qb.ph    $a2,$12,$12
+        precrq_rs.ph.w  $a1,$k0,$a3
+        precrqu_s.qb.ph $zero,$gp,$s5
+        pul.ps          $f9,$f30,$f26
+        puu.ps          $f24,$f9,$f2
+        raddu.w.qb      $25,$s3
+        rdpgpr          $s3,$9
+        recip.d         $f19,$f6
+        recip.s         $f3,$f30
+        repl.ph         $at,-307
+        replv.ph        $v1,$s7
+        replv.qb        $25,$12
+        rorv            $13,$a3,$s5
+        round.l.d       $f12,$f1
+        round.l.s       $f25,$f5
+        rsqrt.d         $f3,$f28
+        rsqrt.s         $f4,$f8
+        sbe             $s7,33($s1)
+        sce             $sp,189($10)
+        she             $24,105($v0)
+        shilo           $ac1,26
+        shilov          $ac2,$10
+        shllv.ph        $10,$s0,$s0
+        shllv.qb        $gp,$v1,$zero
+        shllv_s.ph      $k1,$at,$13
+        shllv_s.w       $s1,$ra,$k0
+        shrav.ph        $25,$s2,$s1
+        shrav.qb        $zero,$24,$11
+        shrav_r.ph      $s3,$11,$25
+        shrav_r.qb      $a0,$sp,$s5
+        shrav_r.w       $s7,$s4,$s6
+        shrlv.ph        $14,$10,$9
+        shrlv.qb        $a2,$s2,$11
+        sub.ps          $f5,$f14,$f26
+        subq.ph         $ra,$9,$s8
+        subq_s.ph       $13,$s8,$s5
+        subq_s.w        $k1,$a2,$a3
+        subqh.ph        $10,$at,$9
+        subqh.w         $v0,$a2,$zero
+        subqh_r.ph      $a0,$12,$s6
+        subqh_r.w       $10,$a2,$gp
+        subu.ph         $9,$s6,$s4
+        subu.qb         $s6,$a2,$s6
+        subu_s.ph       $v1,$a1,$s3
+        subu_s.qb       $s1,$at,$ra
+        subuh.qb        $zero,$gp,$gp
+        subuh_r.qb      $s4,$s8,$s6
+        swe             $24,94($k0)
+        swle            $v1,-209($gp)
+        swre            $k0,-202($s2)
+        tlbginv
+        tlbginvf
+        tlbgp
+        tlbgr
+        tlbgwi
+        tlbgwr
+        tlbinv
+        tlbinvf
+        trunc.l.d       $f23,$f23
+        trunc.l.s       $f28,$f31
+        wrpgpr          $zero,$13
+        xor.v           $w20,$w21,$w30
+        yield           $v1,$s0
diff --git a/test/MC/Mips/mips32r5/valid.s b/test/MC/Mips/mips32r5/valid.s
new file mode 100644
index 00000000000..13341d5016e
--- /dev/null
+++ b/test/MC/Mips/mips32r5/valid.s
@@ -0,0 +1,236 @@
+# Instructions that are valid
+#
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r5 | FileCheck %s
+
+        .set noat
+        abs.d     $f7,$f25             # CHECK: encoding:
+        abs.s     $f9,$f16
+        add       $s7,$s2,$a1
+        add       $9,$14,15176         # CHECK: addi $9, $14, 15176   # encoding: [0x21,0xc9,0x3b,0x48]
+        add       $24,-7193            # CHECK: addi $24, $24, -7193  # encoding: [0x23,0x18,0xe3,0xe7]
+        add.d     $f1,$f7,$f29
+        add.s     $f8,$f21,$f24
+        addi      $13,$9,26322
+        addi      $8,$8,~1             # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
+        addu      $9,$a0,$a2
+        addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
+        and       $s7,$v0,$12
+        and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
+        bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
+        bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
+        bc1fl     $fcc0,4688           # CHECK: bc1fl 4688      # encoding: [0x45,0x02,0x04,0x94]
+        bc1fl     4688                 # CHECK: bc1fl 4688      # encoding: [0x45,0x02,0x04,0x94]
+        bc1fl     $fcc7,27             # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06]
+        bc1t      $fcc0, 4             # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
+        bc1t      $fcc1, 4             # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
+        bc1t      4                    # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
+        bc1tl     $fcc0,4688           # CHECK: bc1tl 4688      # encoding: [0x45,0x03,0x04,0x94]
+        bc1tl     4688                 # CHECK: bc1tl 4688      # encoding: [0x45,0x03,0x04,0x94]
+        bc1tl     $fcc7,27             # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06]
+        bal       21100                # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
+        bgezal    $0, 21100            # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
+        bgezal    $6, 21100            # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
+        bltzal    $6, 21100            # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
+        beql      $14,$s3,12544        # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40]
+        bgezall   $12,7293             # CHECK: bgezall $12, 7293    # encoding: [0x05,0x93,0x07,0x1f]
+        bgezl     $4,-6858             # CHECK: bgezl $4, -6858      # encoding: [0x04,0x83,0xf9,0x4d]
+        bgtzl     $10,-3738            # CHECK: bgtzl $10, -3738     # encoding: [0x5d,0x40,0xfc,0x59]
+        blezl     $6,2974              # CHECK: blezl $6, 2974       # encoding: [0x58,0xc0,0x02,0xe7]
+        bltzall   $6,488               # CHECK: bltzall $6, 488      # encoding: [0x04,0xd2,0x00,0x7a]
+        bltzl     $s1,-9964            # CHECK: bltzl $17, -9964     # encoding: [0x06,0x22,0xf6,0x45]
+        bnel      $gp,$s4,5107         # CHECK: bnel $gp, $20, 5107  # encoding: [0x57,0x94,0x04,0xfc]
+        cache     1, 8($5)             # CHECK: cache 1, 8($5)   # encoding: [0xbc,0xa1,0x00,0x08]
+        c.ngl.d   $f29,$f29
+        c.ngle.d  $f0,$f16
+        c.sf.d    $f30,$f0
+        c.sf.s    $f14,$f22
+        ceil.w.d  $f11,$f25
+        ceil.w.s  $f6,$f20
+        cfc1      $s1,$21
+        clo       $11,$a1              # CHECK: clo $11, $5   # encoding: [0x70,0xab,0x58,0x21]
+        clz       $sp,$gp              # CHECK: clz $sp, $gp  # encoding: [0x73,0x9d,0xe8,0x20]
+        ctc1      $a2,$26
+        cvt.d.s   $f22,$f28
+        cvt.d.w   $f26,$f11
+        cvt.l.d   $f24,$f15
+        cvt.l.s   $f11,$f29
+        cvt.s.d   $f26,$f8
+        cvt.s.w   $f22,$f15
+        cvt.w.d   $f20,$f14
+        cvt.w.s   $f20,$f24
+        deret
+        di        $s8                  # CHECK: di  $fp       # encoding: [0x41,0x7e,0x60,0x00]
+        di                             # CHECK: di            # encoding: [0x41,0x60,0x60,0x00]
+        div       $zero,$25,$11
+        div.d     $f29,$f20,$f27
+        div.s     $f4,$f5,$f15
+        divu      $zero,$25,$15
+        ehb                            # CHECK: ehb # encoding:  [0x00,0x00,0x00,0xc0]
+        ei        $14                  # CHECK: ei  $14       # encoding: [0x41,0x6e,0x60,0x20]
+        ei                             # CHECK: ei            # encoding: [0x41,0x60,0x60,0x20]
+        eret
+        floor.w.d $f14,$f11
+        floor.w.s $f8,$f9
+        jr.hb     $4                   # CHECK: jr.hb  $4 # encoding: [0x00,0x80,0x04,0x08]
+        jalr.hb   $4                   # CHECK: jalr.hb  $4 # encoding: [0x00,0x80,0xfc,0x09]
+        jalr.hb   $4, $5               # CHECK: jalr.hb  $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
+        lb        $24,-14515($10)
+        lbu       $8,30195($v1)
+        ldc1      $f11,16391($s0)
+        ldc2      $8,-21181($at)        # CHECK: ldc2 $8, -21181($1)   # encoding: [0xd8,0x28,0xad,0x43]
+        ldxc1     $f8,$s7($15)
+        lh        $11,-8556($s5)
+        lhu       $s3,-22851($v0)
+        li        $at,-29773
+        li        $zero,-29889
+        ll        $v0,-7321($s2)       # CHECK: ll $2, -7321($18)     # encoding: [0xc2,0x42,0xe3,0x67]
+        luxc1     $f19,$s6($s5)
+        lw        $8,5674($a1)
+        lwc1      $f16,10225($k0)
+        lwc2      $18,-841($a2)        # CHECK: lwc2 $18, -841($6)     # encoding: [0xc8,0xd2,0xfc,0xb7]
+        lwl       $s4,-4231($15)
+        lwr       $zero,-19147($gp)
+        lwxc1     $f12,$s1($s8)
+        madd      $s6,$13
+        madd      $zero,$9
+        madd.d    $f18,$f19,$f26,$f20
+        madd.s    $f1,$f31,$f19,$f25
+        maddu     $s3,$gp
+        maddu     $24,$s2
+        mfc0      $a2,$14,1
+        mfc1      $a3,$f27
+        mfhc1     $s8,$f24
+        mfhi      $s3
+        mfhi      $sp
+        mflo      $s1
+        mov.d     $f20,$f14
+        mov.s     $f2,$f27
+        move      $s8,$a0
+        move      $25,$a2
+        movf      $gp,$8,$fcc7
+        movf.d    $f6,$f11,$fcc5
+        movf.s    $f23,$f5,$fcc6
+        movn      $v1,$s1,$s0
+        movn.d    $f27,$f21,$k0
+        movn.s    $f12,$f0,$s7
+        movt      $zero,$s4,$fcc5
+        movt.d    $f0,$f2,$fcc0
+        movt.s    $f30,$f2,$fcc1
+        movz      $a1,$s6,$9
+        movz.d    $f12,$f29,$9
+        movz.s    $f25,$f7,$v1
+        msub      $s7,$k1
+        msub.d    $f10,$f1,$f31,$f18
+        msub.s    $f12,$f19,$f10,$f16
+        msubu     $15,$a1
+        mtc0      $9,$29,3
+        mtc1      $s8,$f9
+        mthc1     $zero,$f16
+        mthi      $s1
+        mtlo      $sp
+        mtlo      $25
+        mul       $s0,$s4,$at
+        mul.d     $f20,$f20,$f16
+        mul.s     $f30,$f10,$f2
+        mult      $sp,$s4
+        mult      $sp,$v0
+        multu     $gp,$k0
+        multu     $9,$s2
+        negu      $2                   # CHECK: negu $2, $2            # encoding: [0x00,0x02,0x10,0x23]
+        negu      $2,$3                # CHECK: negu $2, $3            # encoding: [0x00,0x03,0x10,0x23]
+        neg.d     $f27,$f18
+        neg.s     $f1,$f15
+        nmadd.d   $f18,$f9,$f14,$f19
+        nmadd.s   $f0,$f5,$f25,$f12
+        nmsub.d   $f30,$f8,$f16,$f30
+        nmsub.s   $f1,$f24,$f19,$f4
+        nop
+        nor       $a3,$zero,$a3
+        or        $12,$s0,$sp
+        or        $2, 4                # CHECK: ori $2, $2, 4           # encoding: [0x34,0x42,0x00,0x04]
+        pause                          # CHECK: pause # encoding:  [0x00,0x00,0x01,0x40]
+        pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
+        # FIXME: Use the code generator in order to print the .set directives
+        #        instead of the instruction printer.
+        rdhwr     $sp,$11              # CHECK:      .set  push
+                                       # CHECK-NEXT: .set  mips32r2
+                                       # CHECK-NEXT: rdhwr $sp, $11
+                                       # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
+        rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
+        rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]
+        rotrv     $1,$14,$15           # CHECK: rotrv $1, $14, $15      # encoding: [0x01,0xee,0x08,0x46]
+        round.w.d $f6,$f4
+        round.w.s $f27,$f28
+        sb        $s6,-19857($14)
+        sc        $15,18904($s3)       # CHECK: sc $15, 18904($19)     # encoding: [0xe2,0x6f,0x49,0xd8]
+        sdbbp                          # CHECK: sdbbp                  # encoding: [0x70,0x00,0x00,0x3f]
+        sdbbp     34                   # CHECK: sdbbp 34               # encoding: [0x70,0x00,0x08,0xbf]
+        sdc1      $f31,30574($13)
+        sdc2      $20,23157($s2)       # CHECK: sdc2 $20, 23157($18)   # encoding: [0xfa,0x54,0x5a,0x75]
+        sdxc1     $f11,$10($14)
+        seb       $25,$15
+        seh       $v1,$12
+        sh        $14,-6704($15)
+        sll       $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
+        sll       $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
+        sll       $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
+        sllv      $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
+        slt       $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
+        slti      $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
+        sltiu     $25,$25,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
+        sltu      $s4,$s5,$11          # CHECK: sltu  $20, $21, $11    # encoding: [0x02,0xab,0xa0,0x2b]
+        sltu      $24,$25,-15531       # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
+        sqrt.d    $f17,$f22
+        sqrt.s    $f0,$f1
+        sra       $s1,15               # CHECK: sra $17, $17, 15       # encoding: [0x00,0x11,0x8b,0xc3]
+        sra       $s1,$s7,15           # CHECK: sra $17, $23, 15       # encoding: [0x00,0x17,0x8b,0xc3]
+        sra       $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
+        srav      $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
+        srl       $2,7                 # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+        srl       $2,$2,7              # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+        srl       $25,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
+        srlv      $25,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
+        ssnop                          # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
+        sub       $s6,$s3,$12
+        sub       $22,$17,-3126        # CHECK: addi $22, $17, 3126    # encoding: [0x22,0x36,0x0c,0x36]
+        sub       $13,6512             # CHECK: addi $13, $13, -6512   # encoding: [0x21,0xad,0xe6,0x90]
+        sub.d     $f18,$f3,$f17
+        sub.s     $f23,$f22,$f22
+        subu      $sp,$s6,$s6
+        suxc1     $f12,$k1($13)
+        sw        $ra,-10160($sp)
+        swc1      $f6,-8465($24)
+        swc2      $25,24880($s0)       # CHECK: swc2 $25, 24880($16)   # encoding: [0xea,0x19,0x61,0x30]
+        swl       $15,13694($s3)
+        swr       $s1,-26590($14)
+        swxc1     $f19,$12($k0)
+        sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+        sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+        teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
+        teq       $5,$7,620            # CHECK: teq $5, $7, 620        # encoding: [0x00,0xa7,0x9b,0x34]
+        teqi      $s5,-17504
+        tge       $7,$10               # CHECK: tge $7, $10            # encoding: [0x00,0xea,0x00,0x30]
+        tge       $5,$19,340           # CHECK: tge $5, $19, 340       # encoding: [0x00,0xb3,0x55,0x30]
+        tgei      $s1,5025
+        tgeiu     $sp,-28621
+        tgeu      $22,$28              # CHECK: tgeu $22, $gp          # encoding: [0x02,0xdc,0x00,0x31]
+        tgeu      $20,$14,379          # CHECK: tgeu $20, $14, 379     # encoding: [0x02,0x8e,0x5e,0xf1]
+        tlbp                           # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+        tlbr                           # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+        tlbwi                          # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+        tlbwr                          # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
+        tlt       $15,$13              # CHECK: tlt $15, $13           # encoding: [0x01,0xed,0x00,0x32]
+        tlt       $2,$19,133           # CHECK: tlt $2, $19, 133       # encoding: [0x00,0x53,0x21,0x72]
+        tlti      $14,-21059
+        tltiu     $ra,-5076
+        tltu      $11,$16              # CHECK: tltu $11, $16          # encoding: [0x01,0x70,0x00,0x33]
+        tltu      $16,$29,1016         # CHECK: tltu $16, $sp, 1016    # encoding: [0x02,0x1d,0xfe,0x33]
+        tne       $6,$17               # CHECK: tne $6, $17            # encoding: [0x00,0xd1,0x00,0x36]
+        tne       $7,$8,885            # CHECK: tne $7, $8, 885        # encoding: [0x00,0xe8,0xdd,0x76]
+        tnei      $12,-29647
+        trunc.w.d $f22,$f15
+        trunc.w.s $f28,$f30
+        wsbh      $k1,$9
+        xor       $s2,$a0,$s8
+        synci     -15842($a2)          # CHECK: synci -15842($6)        # encoding: [0x04,0xdf,0xc2,0x1e]
diff --git a/test/MC/Mips/mips64r3/abi-bad.s b/test/MC/Mips/mips64r3/abi-bad.s
new file mode 100644
index 00000000000..7691601bf29
--- /dev/null
+++ b/test/MC/Mips/mips64r3/abi-bad.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc %s -triple mips-unknown-linux -mcpu=mips64r3 2>&1 | FileCheck %s
+        .set fp=xx
+# CHECK: error: '.set fp=xx' requires the O32 ABI
+# CHECK: .set fp=xx
+# CHECK:          ^
diff --git a/test/MC/Mips/mips64r3/abiflags.s b/test/MC/Mips/mips64r3/abiflags.s
new file mode 100644
index 00000000000..e89be29ca2b
--- /dev/null
+++ b/test/MC/Mips/mips64r3/abiflags.s
@@ -0,0 +1,36 @@
+# RUN: llvm-mc %s -arch=mips -mcpu=mips64r3 | \
+# RUN:   FileCheck %s -check-prefix=CHECK-ASM
+#
+# RUN: llvm-mc %s -arch=mips -mcpu=mips64r3 -filetype=obj -o - | \
+# RUN:   llvm-readobj -sections -section-data -section-relocations - | \
+# RUN:     FileCheck %s -check-prefix=CHECK-OBJ
+
+# CHECK-ASM: .module fp=64
+
+# Checking if the Mips.abiflags were correctly emitted.
+# CHECK-OBJ:       Section {
+# CHECK-OBJ:         Index: 5
+# CHECK-OBJ-LABEL:   Name: .MIPS.abiflags
+# CHECK-OBJ:         Type: SHT_MIPS_ABIFLAGS (0x7000002A)
+# CHECK-OBJ:          Flags [ (0x2)
+# CHECK-OBJ:           SHF_ALLOC (0x2)
+# CHECK-OBJ:         ]
+# CHECK-OBJ:         Address: 0x0
+# CHECK-OBJ:         Size: 24
+# CHECK-OBJ:         Link: 0
+# CHECK-OBJ:         Info: 0
+# CHECK-OBJ:         AddressAlignment: 8
+# CHECK-OBJ:         EntrySize: 24
+# CHECK-OBJ:         Relocations [
+# CHECK-OBJ:         ]
+# CHECK-OBJ:         SectionData (
+# CHECK-OBJ:           0000: 00004003 02020001 00000000 00000000  |..@.............|
+# CHECK-OBJ:           0010: 00000001 00000000                    |........|
+# CHECK-OBJ:         )
+# CHECK-OBJ-LABEL: }
+
+        .module fp=64
+
+# FIXME: Test should include gnu_attributes directive when implemented.
+#        An explicit .gnu_attribute must be checked against the effective
+#        command line options and any inconsistencies reported via a warning.
diff --git a/test/MC/Mips/mips64r3/invalid.s b/test/MC/Mips/mips64r3/invalid.s
new file mode 100644
index 00000000000..99cd0803d20
--- /dev/null
+++ b/test/MC/Mips/mips64r3/invalid.s
@@ -0,0 +1,10 @@
+# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g.
+# invalid set of operands or operand's restrictions not met).
+
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r3 2>%t1
+# RUN: FileCheck %s < %t1 -check-prefix=ASM
+
+        .text
+        .set noreorder
+        jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
+        jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
diff --git a/test/MC/Mips/mips64r3/valid-xfail.s b/test/MC/Mips/mips64r3/valid-xfail.s
new file mode 100644
index 00000000000..af07fbc805f
--- /dev/null
+++ b/test/MC/Mips/mips64r3/valid-xfail.s
@@ -0,0 +1,310 @@
+# Instructions that should be valid but currently fail for known reasons (e.g.
+# they aren't implemented yet).
+# This test is set up to XPASS if any instruction generates an encoding.
+#
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r3 | not FileCheck %s
+# CHECK-NOT: encoding
+# XFAIL: *
+
+        .set noat
+        abs.ps          $f22,$f8
+        absq_s.ph       $8,$a0
+        absq_s.qb       $15,$s1
+        absq_s.w        $s3,$ra
+        add.ps          $f25,$f27,$f13
+        addq.ph         $s1,$15,$at
+        addq_s.ph       $s3,$s6,$s2
+        addq_s.w        $a2,$8,$at
+        addqh.ph        $s4,$14,$s1
+        addqh.w         $s7,$s7,$k1
+        addqh_r.ph      $sp,$25,$s8
+        addqh_r.w       $8,$v1,$zero
+        addsc           $s8,$15,$12
+        addu.ph         $a2,$14,$s3
+        addu.qb         $s6,$v1,$v1
+        addu_s.ph       $a3,$s3,$gp
+        addu_s.qb       $s4,$s8,$s1
+        adduh.qb        $a1,$a1,$at
+        adduh_r.qb      $a0,$9,$12
+        addwc           $k0,$s6,$s7
+        alnv.ob         $v22,$v19,$v30,$v1
+        alnv.ob         $v31,$v23,$v30,$at
+        alnv.ob         $v8,$v17,$v30,$a1
+        alnv.ps         $f12,$f18,$f30,$12
+        and.v           $w10,$w25,$w29
+        bitrev          $14,$at
+        bmnz.v          $w15,$w2,$w28
+        bmz.v           $w13,$w11,$w21
+        bsel.v          $w28,$w7,$w0
+        c.eq.d          $fcc1,$f15,$f15
+        c.eq.ps         $fcc5,$f0,$f9
+        c.eq.s          $fcc5,$f24,$f17
+        c.f.d           $fcc4,$f11,$f21
+        c.f.ps          $fcc6,$f11,$f11
+        c.f.s           $fcc4,$f30,$f7
+        c.le.d          $fcc4,$f18,$f1
+        c.le.ps         $fcc1,$f7,$f20
+        c.le.s          $fcc6,$f24,$f4
+        c.lt.d          $fcc3,$f9,$f3
+        c.lt.ps         $f19,$f5
+        c.lt.s          $fcc2,$f17,$f14
+        c.nge.d         $fcc5,$f21,$f16
+        c.nge.ps        $f1,$f26
+        c.nge.s         $fcc3,$f11,$f8
+        c.ngl.ps        $f21,$f30
+        c.ngl.s         $fcc2,$f31,$f23
+        c.ngle.ps       $fcc7,$f12,$f20
+        c.ngle.s        $fcc2,$f18,$f23
+        c.ngt.d         $fcc4,$f24,$f7
+        c.ngt.ps        $fcc5,$f30,$f6
+        c.ngt.s         $fcc5,$f8,$f13
+        c.ole.d         $fcc2,$f16,$f31
+        c.ole.ps        $fcc7,$f21,$f8
+        c.ole.s         $fcc3,$f7,$f20
+        c.olt.d         $fcc4,$f19,$f28
+        c.olt.ps        $fcc3,$f7,$f16
+        c.olt.s         $fcc6,$f20,$f7
+        c.seq.d         $fcc4,$f31,$f7
+        c.seq.ps        $fcc6,$f31,$f14
+        c.seq.s         $fcc7,$f1,$f25
+        c.sf.ps         $fcc6,$f4,$f6
+        c.ueq.d         $fcc4,$f13,$f25
+        c.ueq.ps        $fcc1,$f5,$f29
+        c.ueq.s         $fcc6,$f3,$f30
+        c.ule.d         $fcc7,$f25,$f18
+        c.ule.ps        $fcc6,$f17,$f3
+        c.ule.s         $fcc7,$f21,$f30
+        c.ult.d         $fcc6,$f6,$f17
+        c.ult.ps        $fcc7,$f14,$f0
+        c.ult.s         $fcc7,$f24,$f10
+        c.un.d          $fcc6,$f23,$f24
+        c.un.ps         $fcc4,$f2,$f26
+        c.un.s          $fcc1,$f30,$f4
+        cvt.ps.s        $f3,$f18,$f19
+        cmp.eq.ph       $s7,$14
+        cmp.le.ph       $8,$14
+        cmp.lt.ph       $k0,$sp
+        cmpgdu.eq.qb    $s3,$zero,$k0
+        cmpgdu.le.qb    $v1,$15,$s2
+        cmpgdu.lt.qb    $s0,$gp,$sp
+        cmpgu.eq.qb     $14,$s6,$s8
+        cmpgu.le.qb     $9,$a3,$s4
+        cmpgu.lt.qb     $sp,$at,$8
+        cmpu.eq.qb      $v0,$24
+        cmpu.le.qb      $s1,$a1
+        cmpu.lt.qb      $at,$a3
+        cvt.s.pl        $f30,$f1
+        cvt.s.pu        $f14,$f25
+        dmfc0           $10,c0_watchhi,2
+        dmfgc0          $gp,c0_perfcnt,6
+        dmt $k0
+        dmtc0           $15,c0_datalo
+        dmtgc0          $a2,c0_watchlo,2
+        dpa.w.ph        $ac1,$s7,$k0
+        dpaq_s.w.ph     $ac2,$a0,$13
+        dpaq_sa.l.w     $ac0,$a2,$14
+        dpaqx_s.w.ph    $ac3,$a0,$24
+        dpaqx_sa.w.ph   $ac1,$zero,$s5
+        dpau.h.qbl      $ac1,$10,$24
+        dpau.h.qbr      $ac1,$s7,$s6
+        dpax.w.ph       $ac3,$a0,$k0
+        dps.w.ph        $ac1,$a3,$a1
+        dpsq_s.w.ph     $ac0,$gp,$k0
+        dpsq_sa.l.w     $ac0,$a3,$15
+        dpsqx_s.w.ph    $ac3,$13,$a3
+        dpsqx_sa.w.ph   $ac3,$sp,$s2
+        dpsu.h.qbl      $ac2,$14,$10
+        dpsu.h.qbr      $ac2,$a1,$s6
+        dpsx.w.ph       $ac0,$s7,$gp
+        drorv           $at,$a1,$s7
+        dvpe            $s6
+        emt $8
+        evpe            $v0
+        extpdpv         $s6,$ac0,$s8
+        extpv           $13,$ac0,$14
+        extrv.w         $8,$ac3,$at
+        extrv_r.w       $8,$ac1,$s6
+        extrv_rs.w      $gp,$ac1,$s6
+        extrv_s.h       $s2,$ac1,$14
+        fclass.d        $w14,$w27
+        fclass.w        $w19,$w28
+        fexupl.d        $w10,$w29
+        fexupl.w        $w12,$w27
+        fexupr.d        $w31,$w15
+        fexupr.w        $w29,$w12
+        ffint_s.d       $w1,$w30
+        ffint_s.w       $w16,$w14
+        ffint_u.d       $w23,$w18
+        ffint_u.w       $w19,$w12
+        ffql.d          $w2,$w3
+        ffql.w          $w9,$w0
+        ffqr.d          $w25,$w24
+        ffqr.w          $w10,$w6
+        fill.b          $w9,$v1
+        fill.d          $w28,$8
+        fill.h          $w9,$8
+        fill.w          $w31,$15
+        flog2.d         $w12,$w16
+        flog2.w         $w19,$w23
+        fork            $s2,$8,$a0
+        frcp.d          $w12,$w4
+        frcp.w          $w30,$w8
+        frint.d         $w20,$w8
+        frint.w         $w11,$w29
+        frsqrt.d        $w29,$w2
+        frsqrt.w        $w9,$w8
+        fsqrt.d         $w3,$w1
+        fsqrt.w         $w5,$w15
+        ftint_s.d       $w31,$w26
+        ftint_s.w       $w27,$w14
+        ftint_u.d       $w5,$w31
+        ftint_u.w       $w12,$w29
+        ftrunc_s.d      $w4,$w22
+        ftrunc_s.w      $w24,$w7
+        ftrunc_u.d      $w20,$w25
+        ftrunc_u.w      $w7,$w26
+        insv            $s2,$at
+        iret
+        lbe $14,122($9)
+        lbue            $11,-108($10)
+        lbux            $9,$14($v0)
+        lhe $s6,219($v1)
+        lhue            $gp,118($11)
+        lhx $sp,$k0($15)
+        lle $gp,-237($ra)
+        lwe $ra,-145($14)
+        lwle            $11,-42($11)
+        lwre            $sp,-152($24)
+        lwx $12,$12($s4)
+        madd.d          $f18,$f19,$f26,$f20
+        madd.ps         $f22,$f3,$f14,$f3
+        maq_s.w.phl     $ac2,$25,$11
+        maq_s.w.phr     $ac0,$10,$25
+        maq_sa.w.phl    $ac3,$a1,$v1
+        maq_sa.w.phr    $ac1,$at,$10
+        mfgc0           $s6,c0_datahi1
+        mflo            $9,$ac2
+        modsub          $a3,$12,$a3
+        mov.ps          $f22,$f17
+        movf.ps         $f10,$f28,$fcc6
+        movn.ps         $f31,$f31,$s3
+        movt.ps         $f20,$f25,$fcc2
+        movz.ps         $f18,$f17,$ra
+        msgn.qh         $v0,$v24,$v20
+        msgn.qh         $v12,$v21,$v0[1]
+        msub            $ac2,$sp,$14
+        msub.d          $f10,$f1,$f31,$f18
+        msub.ps         $f12,$f14,$f29,$f17
+        msubu           $ac2,$a1,$24
+        mtc0            $9,c0_datahi1
+        mtgc0           $s4,$21,7
+        mthi            $v0,$ac1
+        mthlip          $a3,$ac0
+        mul.ph          $s4,$24,$s0
+        mul.ps          $f14,$f0,$f16
+        mul_s.ph        $10,$14,$15
+        muleq_s.w.phl   $11,$s4,$s4
+        muleq_s.w.phr   $s6,$a0,$s8
+        muleu_s.ph.qbl  $a2,$14,$8
+        muleu_s.ph.qbr  $a1,$ra,$9
+        mulq_rs.ph      $s2,$14,$15
+        mulq_rs.w       $at,$s4,$25
+        mulq_s.ph       $s0,$k1,$15
+        mulq_s.w        $9,$a3,$s0
+        mulsa.w.ph      $ac1,$s4,$s6
+        mulsaq_s.w.ph   $ac0,$ra,$s2
+        neg.ps          $f19,$f13
+        nloc.b          $w12,$w30
+        nloc.d          $w16,$w7
+        nloc.h          $w21,$w17
+        nloc.w          $w17,$w16
+        nlzc.b          $w12,$w7
+        nlzc.d          $w14,$w14
+        nlzc.h          $w24,$w24
+        nlzc.w          $w10,$w4
+        nmadd.d         $f18,$f9,$f14,$f19
+        nmadd.ps        $f27,$f4,$f9,$f25
+        nmsub.d         $f30,$f8,$f16,$f30
+        nmsub.ps        $f6,$f12,$f14,$f17
+        nor.v           $w20,$w20,$w15
+        or.v            $w13,$w23,$w12
+        packrl.ph       $ra,$24,$14
+        pcnt.b          $w30,$w15
+        pcnt.d          $w5,$w16
+        pcnt.h          $w20,$w24
+        pcnt.w          $w22,$w20
+        pick.ph         $ra,$a2,$gp
+        pick.qb         $11,$a0,$gp
+        pll.ps          $f25,$f9,$f30
+        plu.ps          $f1,$f26,$f29
+        preceq.w.phl    $s8,$gp
+        preceq.w.phr    $s5,$15
+        precequ.ph.qbl  $s7,$ra
+        precequ.ph.qbla $a0,$9
+        precequ.ph.qbr  $ra,$s3
+        precequ.ph.qbra $24,$8
+        preceu.ph.qbl   $sp,$8
+        preceu.ph.qbla  $s6,$11
+        preceu.ph.qbr   $gp,$s1
+        preceu.ph.qbra  $k1,$s0
+        precr.qb.ph     $v0,$12,$s8
+        precrq.ph.w     $14,$s8,$24
+        precrq.qb.ph    $a2,$12,$12
+        precrq_rs.ph.w  $a1,$k0,$a3
+        precrqu_s.qb.ph $zero,$gp,$s5
+        pul.ps          $f9,$f30,$f26
+        puu.ps          $f24,$f9,$f2
+        raddu.w.qb      $25,$s3
+        rdpgpr          $s3,$9
+        recip.d         $f19,$f6
+        recip.s         $f3,$f30
+        repl.ph         $at,-307
+        replv.ph        $v1,$s7
+        replv.qb        $25,$12
+        rorv            $13,$a3,$s5
+        rsqrt.d         $f3,$f28
+        rsqrt.s         $f4,$f8
+        sbe $s7,33($s1)
+        sce $sp,189($10)
+        she $24,105($v0)
+        shilo           $ac1,26
+        shilov          $ac2,$10
+        shllv.ph        $10,$s0,$s0
+        shllv.qb        $gp,$v1,$zero
+        shllv_s.ph      $k1,$at,$13
+        shllv_s.w       $s1,$ra,$k0
+        shrav.ph        $25,$s2,$s1
+        shrav.qb        $zero,$24,$11
+        shrav_r.ph      $s3,$11,$25
+        shrav_r.qb      $a0,$sp,$s5
+        shrav_r.w       $s7,$s4,$s6
+        shrlv.ph        $14,$10,$9
+        shrlv.qb        $a2,$s2,$11
+        sub.ps          $f5,$f14,$f26
+        subq.ph         $ra,$9,$s8
+        subq_s.ph       $13,$s8,$s5
+        subq_s.w        $k1,$a2,$a3
+        subqh.ph        $10,$at,$9
+        subqh.w         $v0,$a2,$zero
+        subqh_r.ph      $a0,$12,$s6
+        subqh_r.w       $10,$a2,$gp
+        subu.ph         $9,$s6,$s4
+        subu.qb         $s6,$a2,$s6
+        subu_s.ph       $v1,$a1,$s3
+        subu_s.qb       $s1,$at,$ra
+        subuh.qb        $zero,$gp,$gp
+        subuh_r.qb      $s4,$s8,$s6
+        swe $24,94($k0)
+        swle            $v1,-209($gp)
+        swre            $k0,-202($s2)
+        tlbginv
+        tlbginvf
+        tlbgp
+        tlbgr
+        tlbgwi
+        tlbgwr
+        tlbinv
+        tlbinvf
+        wrpgpr          $zero,$13
+        xor.v           $w20,$w21,$w30
+        yield           $v1,$s0
diff --git a/test/MC/Mips/mips64r3/valid.s b/test/MC/Mips/mips64r3/valid.s
new file mode 100644
index 00000000000..d8f1721754c
--- /dev/null
+++ b/test/MC/Mips/mips64r3/valid.s
@@ -0,0 +1,305 @@
+# Instructions that are valid
+#
+# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r3 | FileCheck %s
+
+        .set noat
+        abs.d     $f7,$f25             # CHECK: encoding:
+        abs.s     $f9,$f16
+        add       $s7,$s2,$a1
+        add       $9,$14,15176         # CHECK: addi $9, $14, 15176   # encoding: [0x21,0xc9,0x3b,0x48]
+        add       $24,-7193            # CHECK: addi $24, $24, -7193  # encoding: [0x23,0x18,0xe3,0xe7]
+        add.d     $f1,$f7,$f29
+        add.s     $f8,$f21,$f24
+        addi      $13,$9,26322
+        addi      $8,$8,~1             # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
+        addu      $9,$a0,$a2
+        addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
+        and       $s7,$v0,$12
+        and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
+        bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
+        bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
+        bc1fl     $fcc0,4688           # CHECK: bc1fl 4688      # encoding: [0x45,0x02,0x04,0x94]
+        bc1fl     4688                 # CHECK: bc1fl 4688      # encoding: [0x45,0x02,0x04,0x94]
+        bc1fl     $fcc7,27             # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06]
+        bc1t      $fcc0, 4             # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
+        bc1t      $fcc1, 4             # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
+        bc1t      4                    # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
+        bc1tl     $fcc0,4688           # CHECK: bc1tl 4688      # encoding: [0x45,0x03,0x04,0x94]
+        bc1tl     4688                 # CHECK: bc1tl 4688      # encoding: [0x45,0x03,0x04,0x94]
+        bc1tl     $fcc7,27             # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06]
+        bal       21100                # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
+        bgezal    $0, 21100            # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
+        bgezal    $6, 21100            # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
+        bltzal    $6, 21100            # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
+        beql      $14,$s3,12544        # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40]
+        bgezall   $12,7293             # CHECK: bgezall $12, 7293    # encoding: [0x05,0x93,0x07,0x1f]
+        bgezl     $4,-6858             # CHECK: bgezl $4, -6858      # encoding: [0x04,0x83,0xf9,0x4d]
+        bgtzl     $10,-3738            # CHECK: bgtzl $10, -3738     # encoding: [0x5d,0x40,0xfc,0x59]
+        blezl     $6,2974              # CHECK: blezl $6, 2974       # encoding: [0x58,0xc0,0x02,0xe7]
+        bltzall   $6,488               # CHECK: bltzall $6, 488      # encoding: [0x04,0xd2,0x00,0x7a]
+        bltzl     $s1,-9964            # CHECK: bltzl $17, -9964     # encoding: [0x06,0x22,0xf6,0x45]
+        bnel      $gp,$s4,5107         # CHECK: bnel $gp, $20, 5107  # encoding: [0x57,0x94,0x04,0xfc]
+        cache     1, 8($5)             # CHECK: cache 1, 8($5)   # encoding: [0xbc,0xa1,0x00,0x08]
+        c.ngl.d   $f29,$f29
+        c.ngle.d  $f0,$f16
+        c.sf.d    $f30,$f0
+        c.sf.s    $f14,$f22
+        ceil.l.d  $f1,$f3
+        ceil.l.s  $f18,$f13
+        ceil.w.d  $f11,$f25
+        ceil.w.s  $f6,$f20
+        cfc1      $s1,$21
+        clo       $11,$a1              # CHECK: clo $11, $5   # encoding: [0x70,0xab,0x58,0x21]
+        clz       $sp,$gp              # CHECK: clz $sp, $gp  # encoding: [0x73,0x9d,0xe8,0x20]
+        ctc1      $a2,$26
+        cvt.d.l   $f4,$f16
+        cvt.d.s   $f22,$f28
+        cvt.d.w   $f26,$f11
+        cvt.l.d   $f24,$f15
+        cvt.l.s   $f11,$f29
+        cvt.s.d   $f26,$f8
+        cvt.s.l   $f15,$f30
+        cvt.s.w   $f22,$f15
+        cvt.w.d   $f20,$f14
+        cvt.w.s   $f20,$f24
+        dadd      $s3,$at,$ra
+        dadd      $sp,$s4,-27705       # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
+        dadd      $sp,-27705           # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
+        daddi     $sp,$s4,-27705
+        daddi     $sp,$s4,-27705       # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
+        daddi     $sp,-27705           # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
+        daddiu    $k0,$s6,-4586
+        daddu     $s3,$at,$ra
+        daddu     $24,$2,18079         # CHECK: daddiu $24, $2, 18079  # encoding: [0x64,0x58,0x46,0x9f]
+        daddu     $19,26943            # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f]
+        dclo      $s2,$a2              # CHECK: dclo $18, $6   # encoding: [0x70,0xd2,0x90,0x25]
+        dclz      $s0,$25              # CHECK: dclz $16, $25  # encoding: [0x73,0x30,0x80,0x24]
+        deret
+        di        $s8                  # CHECK: di  $fp        # encoding: [0x41,0x7e,0x60,0x00]
+        di                             # CHECK: di             # encoding: [0x41,0x60,0x60,0x00]
+        ddiv      $zero,$k0,$s3
+        ddivu     $zero,$s0,$s1
+        div       $zero,$25,$11
+        div.d     $f29,$f20,$f27
+        div.s     $f4,$f5,$f15
+        divu      $zero,$25,$15
+        dmfc1     $12,$f13
+        dmtc1     $s0,$f14
+        dmult     $s7,$9
+        dmultu    $a1,$a2
+        drotr     $1,15                # CHECK: drotr $1, $1, 15            # encoding: [0x00,0x21,0x0b,0xfa]
+        drotr     $1,$14,15            # CHECK: drotr $1, $14, 15           # encoding: [0x00,0x2e,0x0b,0xfa]
+        drotr32   $1,15                # CHECK: drotr32 $1, $1, 15          # encoding: [0x00,0x21,0x0b,0xfe]
+        drotr32   $1,$14,15            # CHECK: drotr32 $1, $14, 15         # encoding: [0x00,0x2e,0x0b,0xfe]
+        drotrv    $1,$14,$15           # CHECK: drotrv $1, $14, $15         # encoding: [0x01,0xee,0x08,0x56]
+        dsbh      $v1,$14
+        dshd      $v0,$sp
+        dsll      $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
+        dsll      $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
+        dsll      $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
+        dsll32    $zero,18             # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
+        dsll32    $zero,$zero,18       # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
+        dsllv     $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
+        dsra      $gp,10               # CHECK: dsra $gp, $gp, 10           # encoding: [0x00,0x1c,0xe2,0xbb]
+        dsra      $gp,$s2,10           # CHECK: dsra $gp, $18, 10           # encoding: [0x00,0x12,0xe2,0xbb]
+        dsra      $gp,$s2,$s3          # CHECK: dsrav $gp, $18, $19         # encoding: [0x02,0x72,0xe0,0x17]
+        dsra32    $gp,10               # CHECK: dsra32 $gp, $gp, 10         # encoding: [0x00,0x1c,0xe2,0xbf]
+        dsra32    $gp,$s2,10           # CHECK: dsra32 $gp, $18, 10         # encoding: [0x00,0x12,0xe2,0xbf]
+        dsrav     $gp,$s2,$s3          # CHECK: dsrav $gp, $18, $19         # encoding: [0x02,0x72,0xe0,0x17]
+        dsrl      $s3,23               # CHECK: dsrl $19, $19, 23           # encoding: [0x00,0x13,0x9d,0xfa]
+        dsrl      $s3,$6,23            # CHECK: dsrl $19, $6, 23            # encoding: [0x00,0x06,0x9d,0xfa]
+        dsrl      $s3,$6,$s4           # CHECK: dsrlv $19, $6, $20          # encoding: [0x02,0x86,0x98,0x16]
+        dsrl32    $s3,23               # CHECK: dsrl32 $19, $19, 23         # encoding: [0x00,0x13,0x9d,0xfe]
+        dsrl32    $s3,$6,23            # CHECK: dsrl32 $19, $6, 23          # encoding: [0x00,0x06,0x9d,0xfe]
+        dsrlv     $s3,$6,$s4           # CHECK: dsrlv $19, $6, $20          # encoding: [0x02,0x86,0x98,0x16]
+        dsub      $a3,$s6,$8
+        dsub      $a3,$s6,$8
+        dsub      $sp,$s4,-27705       # CHECK: daddi $sp, $20, 27705  # encoding: [0x62,0x9d,0x6c,0x39]
+        dsub      $sp,-27705           # CHECK: daddi $sp, $sp, 27705  # encoding: [0x63,0xbd,0x6c,0x39]
+        dsubi     $sp,$s4,-27705       # CHECK: daddi $sp, $20, 27705  # encoding: [0x62,0x9d,0x6c,0x39]
+        dsubi     $sp,-27705           # CHECK: daddi $sp, $sp, 27705  # encoding: [0x63,0xbd,0x6c,0x39]
+        dsubu     $a1,$a1,$k0
+        dsubu     $a1,$a1,$k0
+        dsubu     $15,$11,5025         # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
+        dsubu     $14,-4586            # CHECK: daddiu $14, $14, 4586  # encoding: [0x65,0xce,0x11,0xea]
+        ehb                            # CHECK: ehb # encoding:  [0x00,0x00,0x00,0xc0]
+        ei        $14                  # CHECK: ei  $14       # encoding: [0x41,0x6e,0x60,0x20]
+        ei                             # CHECK: ei            # encoding: [0x41,0x60,0x60,0x20]
+        eret
+        floor.l.d $f26,$f7
+        floor.l.s $f12,$f5
+        floor.w.d $f14,$f11
+        floor.w.s $f8,$f9
+        jr.hb     $4                   # CHECK: jr.hb  $4 # encoding: [0x00,0x80,0x04,0x08]
+        jalr.hb   $4                   # CHECK: jalr.hb  $4 # encoding: [0x00,0x80,0xfc,0x09]
+        jalr.hb   $4, $5               # CHECK: jalr.hb  $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
+        lb        $24,-14515($10)
+        lbu       $8,30195($v1)
+        ld        $sp,-28645($s1)
+        ldc1      $f11,16391($s0)
+        ldc2      $8,-21181($at)        # CHECK: ldc2 $8, -21181($1)   # encoding: [0xd8,0x28,0xad,0x43]
+        ldl       $24,-4167($24)
+        ldr       $14,-30358($s4)
+        ldxc1     $f8,$s7($15)
+        lh        $11,-8556($s5)
+        lhu       $s3,-22851($v0)
+        li        $at,-29773
+        li        $zero,-29889
+        ll        $v0,-7321($s2)       # CHECK: ll $2, -7321($18)     # encoding: [0xc2,0x42,0xe3,0x67]
+        lld       $zero,-14736($ra)    # CHECK: lld $zero, -14736($ra) # encoding: [0xd3,0xe0,0xc6,0x70]
+        luxc1     $f19,$s6($s5)
+        lw        $8,5674($a1)
+        lwc1      $f16,10225($k0)
+        lwc2      $18,-841($a2)        # CHECK: lwc2 $18, -841($6)     # encoding: [0xc8,0xd2,0xfc,0xb7]
+        lwl       $s4,-4231($15)
+        lwr       $zero,-19147($gp)
+        lwu       $s3,-24086($v1)
+        lwxc1     $f12,$s1($s8)
+        madd      $s6,$13
+        madd      $zero,$9
+        madd.s    $f1,$f31,$f19,$f25
+        maddu     $s3,$gp
+        maddu     $24,$s2
+        mfc0      $a2,$14,1
+        mfc1      $a3,$f27
+        mfhc1     $s8,$f24
+        mfhi      $s3
+        mfhi      $sp
+        mflo      $s1
+        mov.d     $f20,$f14
+        mov.s     $f2,$f27
+        move      $a0,$a3
+        move      $s5,$a0
+        move      $s8,$a0
+        move      $25,$a2
+        movf      $gp,$8,$fcc7
+        movf.d    $f6,$f11,$fcc5
+        movf.s    $f23,$f5,$fcc6
+        movn      $v1,$s1,$s0
+        movn.d    $f27,$f21,$k0
+        movn.s    $f12,$f0,$s7
+        movt      $zero,$s4,$fcc5
+        movt.d    $f0,$f2,$fcc0
+        movt.s    $f30,$f2,$fcc1
+        movz      $a1,$s6,$9
+        movz.d    $f12,$f29,$9
+        movz.s    $f25,$f7,$v1
+        msub      $s7,$k1
+        msub.s    $f12,$f19,$f10,$f16
+        msubu     $15,$a1
+        mtc0      $9,$29,3
+        mtc1      $s8,$f9
+        mthc1     $zero,$f16
+        mthi      $s1
+        mtlo      $sp
+        mtlo      $25
+        mul       $s0,$s4,$at
+        mul.d     $f20,$f20,$f16
+        mul.s     $f30,$f10,$f2
+        mult      $sp,$s4
+        mult      $sp,$v0
+        multu     $gp,$k0
+        multu     $9,$s2
+        negu      $2                   # CHECK: negu $2, $2            # encoding: [0x00,0x02,0x10,0x23]
+        negu      $2,$3                # CHECK: negu $2, $3            # encoding: [0x00,0x03,0x10,0x23]
+        neg.d     $f27,$f18
+        neg.s     $f1,$f15
+        nmadd.s   $f0,$f5,$f25,$f12
+        nmsub.s   $f1,$f24,$f19,$f4
+        nop
+        nor       $a3,$zero,$a3
+        or        $12,$s0,$sp
+        or        $2, 4                # CHECK: ori $2, $2, 4           # encoding: [0x34,0x42,0x00,0x04]
+        pause                          # CHECK: pause # encoding:  [0x00,0x00,0x01,0x40]
+        pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
+        # FIXME: Use the code generator in order to print the .set directives
+        #        instead of the instruction printer.
+        rdhwr     $sp,$11              # CHECK:      .set  push
+                                       # CHECK-NEXT: .set  mips32r2
+                                       # CHECK-NEXT: rdhwr $sp, $11
+                                       # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
+        rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
+        rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]
+        rotrv     $1,$14,$15           # CHECK: rotrv $1, $14, $15      # encoding: [0x01,0xee,0x08,0x46]
+        round.l.d $f12,$f1
+        round.l.s $f25,$f5
+        round.w.d $f6,$f4
+        round.w.s $f27,$f28
+        sb        $s6,-19857($14)
+        sc        $15,18904($s3)       # CHECK: sc $15, 18904($19)     # encoding: [0xe2,0x6f,0x49,0xd8]
+        scd       $15,-8243($sp)       # CHECK: scd $15, -8243($sp)    # encoding: [0xf3,0xaf,0xdf,0xcd]
+        sdbbp                          # CHECK: sdbbp                  # encoding: [0x70,0x00,0x00,0x3f]
+        sdbbp     34                   # CHECK: sdbbp 34               # encoding: [0x70,0x00,0x08,0xbf]
+        sd        $12,5835($10)
+        sdc1      $f31,30574($13)
+        sdc2      $20,23157($s2)       # CHECK: sdc2 $20, 23157($18)   # encoding: [0xfa,0x54,0x5a,0x75]
+        sdl       $a3,-20961($s8)
+        sdr       $11,-20423($12)
+        sdxc1     $f11,$10($14)
+        seb       $25,$15
+        seh       $v1,$12
+        sh        $14,-6704($15)
+        sll       $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
+        sll       $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
+        sll       $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
+        sllv      $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
+        slt       $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
+        slti      $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
+        sltiu     $25,$25,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
+        sltu      $s4,$s5,$11          # CHECK: sltu  $20, $21, $11    # encoding: [0x02,0xab,0xa0,0x2b]
+        sltu      $24,$25,-15531       # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
+        sqrt.d    $f17,$f22
+        sqrt.s    $f0,$f1
+        sra       $s1,15               # CHECK: sra $17, $17, 15       # encoding: [0x00,0x11,0x8b,0xc3]
+        sra       $s1,$s7,15           # CHECK: sra $17, $23, 15       # encoding: [0x00,0x17,0x8b,0xc3]
+        sra       $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
+        srav      $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
+        srl       $2,7                 # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+        srl       $2,$2,7              # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+        srl       $25,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
+        srlv      $25,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
+        ssnop                          # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
+        sub       $s6,$s3,$12
+        sub       $22,$17,-3126        # CHECK: addi $22, $17, 3126    # encoding: [0x22,0x36,0x0c,0x36]
+        sub       $13,6512             # CHECK: addi $13, $13, -6512   # encoding: [0x21,0xad,0xe6,0x90]
+        sub.d     $f18,$f3,$f17
+        sub.s     $f23,$f22,$f22
+        subu      $sp,$s6,$s6
+        suxc1     $f12,$k1($13)
+        sw        $ra,-10160($sp)
+        swc1      $f6,-8465($24)
+        swc2      $25,24880($s0)       # CHECK: swc2 $25, 24880($16)   # encoding: [0xea,0x19,0x61,0x30]
+        swl       $15,13694($s3)
+        swr       $s1,-26590($14)
+        swxc1     $f19,$12($k0)
+        sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+        sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+        teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
+        teq       $5,$7,620            # CHECK: teq $5, $7, 620        # encoding: [0x00,0xa7,0x9b,0x34]
+        teqi      $s5,-17504
+        tge       $7,$10               # CHECK: tge $7, $10            # encoding: [0x00,0xea,0x00,0x30]
+        tge       $5,$19,340           # CHECK: tge $5, $19, 340       # encoding: [0x00,0xb3,0x55,0x30]
+        tgei      $s1,5025
+        tgeiu     $sp,-28621
+        tgeu      $22,$28              # CHECK: tgeu $22, $gp          # encoding: [0x02,0xdc,0x00,0x31]
+        tgeu      $20,$14,379          # CHECK: tgeu $20, $14, 379     # encoding: [0x02,0x8e,0x5e,0xf1]
+        tlbp                           # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+        tlbr                           # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+        tlbwi                          # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+        tlbwr                          # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
+        tlt       $15,$13              # CHECK: tlt $15, $13           # encoding: [0x01,0xed,0x00,0x32]
+        tlt       $2,$19,133           # CHECK: tlt $2, $19, 133       # encoding: [0x00,0x53,0x21,0x72]
+        tlti      $14,-21059
+        tltiu     $ra,-5076
+        tltu      $11,$16              # CHECK: tltu $11, $16          # encoding: [0x01,0x70,0x00,0x33]
+        tltu      $16,$29,1016         # CHECK: tltu $16, $sp, 1016    # encoding: [0x02,0x1d,0xfe,0x33]
+        tne       $6,$17               # CHECK: tne $6, $17            # encoding: [0x00,0xd1,0x00,0x36]
+        tne       $7,$8,885            # CHECK: tne $7, $8, 885        # encoding: [0x00,0xe8,0xdd,0x76]
+        tnei      $12,-29647
+        trunc.l.d $f23,$f23
+        trunc.l.s $f28,$f31
+        trunc.w.d $f22,$f15
+        trunc.w.s $f28,$f30
+        xor       $s2,$a0,$s8
+        wsbh      $k1,$9
diff --git a/test/MC/Mips/mips64r5/abi-bad.s b/test/MC/Mips/mips64r5/abi-bad.s
new file mode 100644
index 00000000000..c6bb29a8b20
--- /dev/null
+++ b/test/MC/Mips/mips64r5/abi-bad.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc %s -triple mips-unknown-linux -mcpu=mips64r5 2>&1 | FileCheck %s
+        .set fp=xx
+# CHECK: error: '.set fp=xx' requires the O32 ABI
+# CHECK: .set fp=xx
+# CHECK:          ^
diff --git a/test/MC/Mips/mips64r5/abiflags.s b/test/MC/Mips/mips64r5/abiflags.s
new file mode 100644
index 00000000000..43a5fe618bc
--- /dev/null
+++ b/test/MC/Mips/mips64r5/abiflags.s
@@ -0,0 +1,36 @@
+# RUN: llvm-mc %s -arch=mips -mcpu=mips64r5 | \
+# RUN:   FileCheck %s -check-prefix=CHECK-ASM
+#
+# RUN: llvm-mc %s -arch=mips -mcpu=mips64r5 -filetype=obj -o - | \
+# RUN:   llvm-readobj -sections -section-data -section-relocations - | \
+# RUN:     FileCheck %s -check-prefix=CHECK-OBJ
+
+# CHECK-ASM: .module fp=64
+
+# Checking if the Mips.abiflags were correctly emitted.
+# CHECK-OBJ:       Section {
+# CHECK-OBJ:         Index: 5
+# CHECK-OBJ-LABEL:   Name: .MIPS.abiflags
+# CHECK-OBJ:         Type: SHT_MIPS_ABIFLAGS (0x7000002A)
+# CHECK-OBJ:          Flags [ (0x2)
+# CHECK-OBJ:           SHF_ALLOC (0x2)
+# CHECK-OBJ:         ]
+# CHECK-OBJ:         Address: 0x0
+# CHECK-OBJ:         Size: 24
+# CHECK-OBJ:         Link: 0
+# CHECK-OBJ:         Info: 0
+# CHECK-OBJ:         AddressAlignment: 8
+# CHECK-OBJ:         EntrySize: 24
+# CHECK-OBJ:         Relocations [
+# CHECK-OBJ:         ]
+# CHECK-OBJ:         SectionData (
+# CHECK-OBJ:           0000: 00004005 02020001 00000000 00000000  |..@.............|
+# CHECK-OBJ:           0010: 00000001 00000000                    |........|
+# CHECK-OBJ:         )
+# CHECK-OBJ-LABEL: }
+
+        .module fp=64
+
+# FIXME: Test should include gnu_attributes directive when implemented.
+#        An explicit .gnu_attribute must be checked against the effective
+#        command line options and any inconsistencies reported via a warning.
diff --git a/test/MC/Mips/mips64r5/invalid.s b/test/MC/Mips/mips64r5/invalid.s
new file mode 100644
index 00000000000..8319debaa30
--- /dev/null
+++ b/test/MC/Mips/mips64r5/invalid.s
@@ -0,0 +1,10 @@
+# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g.
+# invalid set of operands or operand's restrictions not met).
+
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r5 2>%t1
+# RUN: FileCheck %s < %t1 -check-prefix=ASM
+
+        .text
+        .set noreorder
+        jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
+        jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
diff --git a/test/MC/Mips/mips64r5/valid-xfail.s b/test/MC/Mips/mips64r5/valid-xfail.s
new file mode 100644
index 00000000000..b8f26c6cf6e
--- /dev/null
+++ b/test/MC/Mips/mips64r5/valid-xfail.s
@@ -0,0 +1,310 @@
+# Instructions that should be valid but currently fail for known reasons (e.g.
+# they aren't implemented yet).
+# This test is set up to XPASS if any instruction generates an encoding.
+#
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r5 | not FileCheck %s
+# CHECK-NOT: encoding
+# XFAIL: *
+
+        .set noat
+        abs.ps          $f22,$f8
+        absq_s.ph       $8,$a0
+        absq_s.qb       $15,$s1
+        absq_s.w        $s3,$ra
+        add.ps          $f25,$f27,$f13
+        addq.ph         $s1,$15,$at
+        addq_s.ph       $s3,$s6,$s2
+        addq_s.w        $a2,$8,$at
+        addqh.ph        $s4,$14,$s1
+        addqh.w         $s7,$s7,$k1
+        addqh_r.ph      $sp,$25,$s8
+        addqh_r.w       $8,$v1,$zero
+        addsc           $s8,$15,$12
+        addu.ph         $a2,$14,$s3
+        addu.qb         $s6,$v1,$v1
+        addu_s.ph       $a3,$s3,$gp
+        addu_s.qb       $s4,$s8,$s1
+        adduh.qb        $a1,$a1,$at
+        adduh_r.qb      $a0,$9,$12
+        addwc           $k0,$s6,$s7
+        alnv.ob         $v22,$v19,$v30,$v1
+        alnv.ob         $v31,$v23,$v30,$at
+        alnv.ob         $v8,$v17,$v30,$a1
+        alnv.ps         $f12,$f18,$f30,$12
+        and.v           $w10,$w25,$w29
+        bitrev          $14,$at
+        bmnz.v          $w15,$w2,$w28
+        bmz.v           $w13,$w11,$w21
+        bsel.v          $w28,$w7,$w0
+        c.eq.d          $fcc1,$f15,$f15
+        c.eq.ps         $fcc5,$f0,$f9
+        c.eq.s          $fcc5,$f24,$f17
+        c.f.d           $fcc4,$f11,$f21
+        c.f.ps          $fcc6,$f11,$f11
+        c.f.s           $fcc4,$f30,$f7
+        c.le.d          $fcc4,$f18,$f1
+        c.le.ps         $fcc1,$f7,$f20
+        c.le.s          $fcc6,$f24,$f4
+        c.lt.d          $fcc3,$f9,$f3
+        c.lt.ps         $f19,$f5
+        c.lt.s          $fcc2,$f17,$f14
+        c.nge.d         $fcc5,$f21,$f16
+        c.nge.ps        $f1,$f26
+        c.nge.s         $fcc3,$f11,$f8
+        c.ngl.ps        $f21,$f30
+        c.ngl.s         $fcc2,$f31,$f23
+        c.ngle.ps       $fcc7,$f12,$f20
+        c.ngle.s        $fcc2,$f18,$f23
+        c.ngt.d         $fcc4,$f24,$f7
+        c.ngt.ps        $fcc5,$f30,$f6
+        c.ngt.s         $fcc5,$f8,$f13
+        c.ole.d         $fcc2,$f16,$f31
+        c.ole.ps        $fcc7,$f21,$f8
+        c.ole.s         $fcc3,$f7,$f20
+        c.olt.d         $fcc4,$f19,$f28
+        c.olt.ps        $fcc3,$f7,$f16
+        c.olt.s         $fcc6,$f20,$f7
+        c.seq.d         $fcc4,$f31,$f7
+        c.seq.ps        $fcc6,$f31,$f14
+        c.seq.s         $fcc7,$f1,$f25
+        c.sf.ps         $fcc6,$f4,$f6
+        c.ueq.d         $fcc4,$f13,$f25
+        c.ueq.ps        $fcc1,$f5,$f29
+        c.ueq.s         $fcc6,$f3,$f30
+        c.ule.d         $fcc7,$f25,$f18
+        c.ule.ps        $fcc6,$f17,$f3
+        c.ule.s         $fcc7,$f21,$f30
+        c.ult.d         $fcc6,$f6,$f17
+        c.ult.ps        $fcc7,$f14,$f0
+        c.ult.s         $fcc7,$f24,$f10
+        c.un.d          $fcc6,$f23,$f24
+        c.un.ps         $fcc4,$f2,$f26
+        c.un.s          $fcc1,$f30,$f4
+        cvt.ps.s        $f3,$f18,$f19
+        cmp.eq.ph       $s7,$14
+        cmp.le.ph       $8,$14
+        cmp.lt.ph       $k0,$sp
+        cmpgdu.eq.qb    $s3,$zero,$k0
+        cmpgdu.le.qb    $v1,$15,$s2
+        cmpgdu.lt.qb    $s0,$gp,$sp
+        cmpgu.eq.qb     $14,$s6,$s8
+        cmpgu.le.qb     $9,$a3,$s4
+        cmpgu.lt.qb     $sp,$at,$8
+        cmpu.eq.qb      $v0,$24
+        cmpu.le.qb      $s1,$a1
+        cmpu.lt.qb      $at,$a3
+        cvt.s.pl        $f30,$f1
+        cvt.s.pu        $f14,$f25
+        dmfc0           $10,c0_watchhi,2
+        dmfgc0          $gp,c0_perfcnt,6
+        dmt $k0
+        dmtc0           $15,c0_datalo
+        dmtgc0          $a2,c0_watchlo,2
+        dpa.w.ph        $ac1,$s7,$k0
+        dpaq_s.w.ph     $ac2,$a0,$13
+        dpaq_sa.l.w     $ac0,$a2,$14
+        dpaqx_s.w.ph    $ac3,$a0,$24
+        dpaqx_sa.w.ph   $ac1,$zero,$s5
+        dpau.h.qbl      $ac1,$10,$24
+        dpau.h.qbr      $ac1,$s7,$s6
+        dpax.w.ph       $ac3,$a0,$k0
+        dps.w.ph        $ac1,$a3,$a1
+        dpsq_s.w.ph     $ac0,$gp,$k0
+        dpsq_sa.l.w     $ac0,$a3,$15
+        dpsqx_s.w.ph    $ac3,$13,$a3
+        dpsqx_sa.w.ph   $ac3,$sp,$s2
+        dpsu.h.qbl      $ac2,$14,$10
+        dpsu.h.qbr      $ac2,$a1,$s6
+        dpsx.w.ph       $ac0,$s7,$gp
+        drorv           $at,$a1,$s7
+        dvpe            $s6
+        emt $8
+        evpe            $v0
+        extpdpv         $s6,$ac0,$s8
+        extpv           $13,$ac0,$14
+        extrv.w         $8,$ac3,$at
+        extrv_r.w       $8,$ac1,$s6
+        extrv_rs.w      $gp,$ac1,$s6
+        extrv_s.h       $s2,$ac1,$14
+        fclass.d        $w14,$w27
+        fclass.w        $w19,$w28
+        fexupl.d        $w10,$w29
+        fexupl.w        $w12,$w27
+        fexupr.d        $w31,$w15
+        fexupr.w        $w29,$w12
+        ffint_s.d       $w1,$w30
+        ffint_s.w       $w16,$w14
+        ffint_u.d       $w23,$w18
+        ffint_u.w       $w19,$w12
+        ffql.d          $w2,$w3
+        ffql.w          $w9,$w0
+        ffqr.d          $w25,$w24
+        ffqr.w          $w10,$w6
+        fill.b          $w9,$v1
+        fill.d          $w28,$8
+        fill.h          $w9,$8
+        fill.w          $w31,$15
+        flog2.d         $w12,$w16
+        flog2.w         $w19,$w23
+        fork            $s2,$8,$a0
+        frcp.d          $w12,$w4
+        frcp.w          $w30,$w8
+        frint.d         $w20,$w8
+        frint.w         $w11,$w29
+        frsqrt.d        $w29,$w2
+        frsqrt.w        $w9,$w8
+        fsqrt.d         $w3,$w1
+        fsqrt.w         $w5,$w15
+        ftint_s.d       $w31,$w26
+        ftint_s.w       $w27,$w14
+        ftint_u.d       $w5,$w31
+        ftint_u.w       $w12,$w29
+        ftrunc_s.d      $w4,$w22
+        ftrunc_s.w      $w24,$w7
+        ftrunc_u.d      $w20,$w25
+        ftrunc_u.w      $w7,$w26
+        insv            $s2,$at
+        iret
+        lbe $14,122($9)
+        lbue            $11,-108($10)
+        lbux            $9,$14($v0)
+        lhe $s6,219($v1)
+        lhue            $gp,118($11)
+        lhx $sp,$k0($15)
+        lle $gp,-237($ra)
+        lwe $ra,-145($14)
+        lwle            $11,-42($11)
+        lwre            $sp,-152($24)
+        lwx $12,$12($s4)
+        madd.d          $f18,$f19,$f26,$f20
+        madd.ps         $f22,$f3,$f14,$f3
+        maq_s.w.phl     $ac2,$25,$11
+        maq_s.w.phr     $ac0,$10,$25
+        maq_sa.w.phl    $ac3,$a1,$v1
+        maq_sa.w.phr    $ac1,$at,$10
+        mfgc0           $s6,c0_datahi1
+        mflo            $9,$ac2
+        modsub          $a3,$12,$a3
+        mov.ps          $f22,$f17
+        movf.ps         $f10,$f28,$fcc6
+        movn.ps         $f31,$f31,$s3
+        movt.ps         $f20,$f25,$fcc2
+        movz.ps         $f18,$f17,$ra
+        msgn.qh         $v0,$v24,$v20
+        msgn.qh         $v12,$v21,$v0[1]
+        msub            $ac2,$sp,$14
+        msub.d          $f10,$f1,$f31,$f18
+        msub.ps         $f12,$f14,$f29,$f17
+        msubu           $ac2,$a1,$24
+        mtc0            $9,c0_datahi1
+        mtgc0           $s4,$21,7
+        mthi            $v0,$ac1
+        mthlip          $a3,$ac0
+        mul.ph          $s4,$24,$s0
+        mul.ps          $f14,$f0,$f16
+        mul_s.ph        $10,$14,$15
+        muleq_s.w.phl   $11,$s4,$s4
+        muleq_s.w.phr   $s6,$a0,$s8
+        muleu_s.ph.qbl  $a2,$14,$8
+        muleu_s.ph.qbr  $a1,$ra,$9
+        mulq_rs.ph      $s2,$14,$15
+        mulq_rs.w       $at,$s4,$25
+        mulq_s.ph       $s0,$k1,$15
+        mulq_s.w        $9,$a3,$s0
+        mulsa.w.ph      $ac1,$s4,$s6
+        mulsaq_s.w.ph   $ac0,$ra,$s2
+        neg.ps          $f19,$f13
+        nloc.b          $w12,$w30
+        nloc.d          $w16,$w7
+        nloc.h          $w21,$w17
+        nloc.w          $w17,$w16
+        nlzc.b          $w12,$w7
+        nlzc.d          $w14,$w14
+        nlzc.h          $w24,$w24
+        nlzc.w          $w10,$w4
+        nmadd.d         $f18,$f9,$f14,$f19
+        nmadd.ps        $f27,$f4,$f9,$f25
+        nmsub.d         $f30,$f8,$f16,$f30
+        nmsub.ps        $f6,$f12,$f14,$f17
+        nor.v           $w20,$w20,$w15
+        or.v            $w13,$w23,$w12
+        packrl.ph       $ra,$24,$14
+        pcnt.b          $w30,$w15
+        pcnt.d          $w5,$w16
+        pcnt.h          $w20,$w24
+        pcnt.w          $w22,$w20
+        pick.ph         $ra,$a2,$gp
+        pick.qb         $11,$a0,$gp
+        pll.ps          $f25,$f9,$f30
+        plu.ps          $f1,$f26,$f29
+        preceq.w.phl    $s8,$gp
+        preceq.w.phr    $s5,$15
+        precequ.ph.qbl  $s7,$ra
+        precequ.ph.qbla $a0,$9
+        precequ.ph.qbr  $ra,$s3
+        precequ.ph.qbra $24,$8
+        preceu.ph.qbl   $sp,$8
+        preceu.ph.qbla  $s6,$11
+        preceu.ph.qbr   $gp,$s1
+        preceu.ph.qbra  $k1,$s0
+        precr.qb.ph     $v0,$12,$s8
+        precrq.ph.w     $14,$s8,$24
+        precrq.qb.ph    $a2,$12,$12
+        precrq_rs.ph.w  $a1,$k0,$a3
+        precrqu_s.qb.ph $zero,$gp,$s5
+        pul.ps          $f9,$f30,$f26
+        puu.ps          $f24,$f9,$f2
+        raddu.w.qb      $25,$s3
+        rdpgpr          $s3,$9
+        recip.d         $f19,$f6
+        recip.s         $f3,$f30
+        repl.ph         $at,-307
+        replv.ph        $v1,$s7
+        replv.qb        $25,$12
+        rorv            $13,$a3,$s5
+        rsqrt.d         $f3,$f28
+        rsqrt.s         $f4,$f8
+        sbe $s7,33($s1)
+        sce $sp,189($10)
+        she $24,105($v0)
+        shilo           $ac1,26
+        shilov          $ac2,$10
+        shllv.ph        $10,$s0,$s0
+        shllv.qb        $gp,$v1,$zero
+        shllv_s.ph      $k1,$at,$13
+        shllv_s.w       $s1,$ra,$k0
+        shrav.ph        $25,$s2,$s1
+        shrav.qb        $zero,$24,$11
+        shrav_r.ph      $s3,$11,$25
+        shrav_r.qb      $a0,$sp,$s5
+        shrav_r.w       $s7,$s4,$s6
+        shrlv.ph        $14,$10,$9
+        shrlv.qb        $a2,$s2,$11
+        sub.ps          $f5,$f14,$f26
+        subq.ph         $ra,$9,$s8
+        subq_s.ph       $13,$s8,$s5
+        subq_s.w        $k1,$a2,$a3
+        subqh.ph        $10,$at,$9
+        subqh.w         $v0,$a2,$zero
+        subqh_r.ph      $a0,$12,$s6
+        subqh_r.w       $10,$a2,$gp
+        subu.ph         $9,$s6,$s4
+        subu.qb         $s6,$a2,$s6
+        subu_s.ph       $v1,$a1,$s3
+        subu_s.qb       $s1,$at,$ra
+        subuh.qb        $zero,$gp,$gp
+        subuh_r.qb      $s4,$s8,$s6
+        swe $24,94($k0)
+        swle            $v1,-209($gp)
+        swre            $k0,-202($s2)
+        tlbginv
+        tlbginvf
+        tlbgp
+        tlbgr
+        tlbgwi
+        tlbgwr
+        tlbinv
+        tlbinvf
+        wrpgpr          $zero,$13
+        xor.v           $w20,$w21,$w30
+        yield           $v1,$s0
diff --git a/test/MC/Mips/mips64r5/valid.s b/test/MC/Mips/mips64r5/valid.s
new file mode 100644
index 00000000000..17068526cd8
--- /dev/null
+++ b/test/MC/Mips/mips64r5/valid.s
@@ -0,0 +1,305 @@
+# Instructions that are valid
+#
+# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r5 | FileCheck %s
+
+        .set noat
+        abs.d     $f7,$f25             # CHECK: encoding:
+        abs.s     $f9,$f16
+        add       $s7,$s2,$a1
+        add       $9,$14,15176         # CHECK: addi $9, $14, 15176   # encoding: [0x21,0xc9,0x3b,0x48]
+        add       $24,-7193            # CHECK: addi $24, $24, -7193  # encoding: [0x23,0x18,0xe3,0xe7]
+        add.d     $f1,$f7,$f29
+        add.s     $f8,$f21,$f24
+        addi      $13,$9,26322
+        addi      $8,$8,~1             # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
+        addu      $9,$a0,$a2
+        addu      $9,10                # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
+        and       $s7,$v0,$12
+        and       $2,4                 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
+        bc1f      $fcc0, 4             # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
+        bc1f      $fcc1, 4             # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
+        bc1f      4                    # CHECK: bc1f 4        # encoding: [0x45,0x00,0x00,0x01]
+        bc1fl     $fcc0,4688           # CHECK: bc1fl 4688      # encoding: [0x45,0x02,0x04,0x94]
+        bc1fl     4688                 # CHECK: bc1fl 4688      # encoding: [0x45,0x02,0x04,0x94]
+        bc1fl     $fcc7,27             # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06]
+        bc1t      $fcc0, 4             # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
+        bc1t      $fcc1, 4             # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
+        bc1t      4                    # CHECK: bc1t 4        # encoding: [0x45,0x01,0x00,0x01]
+        bc1tl     $fcc0,4688           # CHECK: bc1tl 4688      # encoding: [0x45,0x03,0x04,0x94]
+        bc1tl     4688                 # CHECK: bc1tl 4688      # encoding: [0x45,0x03,0x04,0x94]
+        bc1tl     $fcc7,27             # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06]
+        bal       21100                # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
+        bgezal    $0, 21100            # CHECK: bal 21100     # encoding: [0x04,0x11,0x14,0x9b]
+        bgezal    $6, 21100            # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
+        bltzal    $6, 21100            # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
+        beql      $14,$s3,12544        # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40]
+        bgezall   $12,7293             # CHECK: bgezall $12, 7293    # encoding: [0x05,0x93,0x07,0x1f]
+        bgezl     $4,-6858             # CHECK: bgezl $4, -6858      # encoding: [0x04,0x83,0xf9,0x4d]
+        bgtzl     $10,-3738            # CHECK: bgtzl $10, -3738     # encoding: [0x5d,0x40,0xfc,0x59]
+        blezl     $6,2974              # CHECK: blezl $6, 2974       # encoding: [0x58,0xc0,0x02,0xe7]
+        bltzall   $6,488               # CHECK: bltzall $6, 488      # encoding: [0x04,0xd2,0x00,0x7a]
+        bltzl     $s1,-9964            # CHECK: bltzl $17, -9964     # encoding: [0x06,0x22,0xf6,0x45]
+        bnel      $gp,$s4,5107         # CHECK: bnel $gp, $20, 5107  # encoding: [0x57,0x94,0x04,0xfc]
+        cache     1, 8($5)             # CHECK: cache 1, 8($5)   # encoding: [0xbc,0xa1,0x00,0x08]
+        c.ngl.d   $f29,$f29
+        c.ngle.d  $f0,$f16
+        c.sf.d    $f30,$f0
+        c.sf.s    $f14,$f22
+        ceil.l.d  $f1,$f3
+        ceil.l.s  $f18,$f13
+        ceil.w.d  $f11,$f25
+        ceil.w.s  $f6,$f20
+        cfc1      $s1,$21
+        clo       $11,$a1              # CHECK: clo $11, $5   # encoding: [0x70,0xab,0x58,0x21]
+        clz       $sp,$gp              # CHECK: clz $sp, $gp  # encoding: [0x73,0x9d,0xe8,0x20]
+        ctc1      $a2,$26
+        cvt.d.l   $f4,$f16
+        cvt.d.s   $f22,$f28
+        cvt.d.w   $f26,$f11
+        cvt.l.d   $f24,$f15
+        cvt.l.s   $f11,$f29
+        cvt.s.d   $f26,$f8
+        cvt.s.l   $f15,$f30
+        cvt.s.w   $f22,$f15
+        cvt.w.d   $f20,$f14
+        cvt.w.s   $f20,$f24
+        dadd      $s3,$at,$ra
+        dadd      $sp,$s4,-27705       # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
+        dadd      $sp,-27705           # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
+        daddi     $sp,$s4,-27705
+        daddi     $sp,$s4,-27705       # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
+        daddi     $sp,-27705           # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
+        daddiu    $k0,$s6,-4586
+        daddu     $s3,$at,$ra
+        daddu     $24,$2,18079         # CHECK: daddiu $24, $2, 18079  # encoding: [0x64,0x58,0x46,0x9f]
+        daddu     $19,26943            # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f]
+        dclo      $s2,$a2              # CHECK: dclo $18, $6   # encoding: [0x70,0xd2,0x90,0x25]
+        dclz      $s0,$25              # CHECK: dclz $16, $25  # encoding: [0x73,0x30,0x80,0x24]
+        deret
+        di        $s8                  # CHECK: di  $fp        # encoding: [0x41,0x7e,0x60,0x00]
+        di                             # CHECK: di             # encoding: [0x41,0x60,0x60,0x00]
+        ddiv      $zero,$k0,$s3
+        ddivu     $zero,$s0,$s1
+        div       $zero,$25,$11
+        div.d     $f29,$f20,$f27
+        div.s     $f4,$f5,$f15
+        divu      $zero,$25,$15
+        dmfc1     $12,$f13
+        dmtc1     $s0,$f14
+        dmult     $s7,$9
+        dmultu    $a1,$a2
+        drotr     $1,15                # CHECK: drotr $1, $1, 15            # encoding: [0x00,0x21,0x0b,0xfa]
+        drotr     $1,$14,15            # CHECK: drotr $1, $14, 15           # encoding: [0x00,0x2e,0x0b,0xfa]
+        drotr32   $1,15                # CHECK: drotr32 $1, $1, 15          # encoding: [0x00,0x21,0x0b,0xfe]
+        drotr32   $1,$14,15            # CHECK: drotr32 $1, $14, 15         # encoding: [0x00,0x2e,0x0b,0xfe]
+        drotrv    $1,$14,$15           # CHECK: drotrv $1, $14, $15         # encoding: [0x01,0xee,0x08,0x56]
+        dsbh      $v1,$14
+        dshd      $v0,$sp
+        dsll      $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
+        dsll      $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
+        dsll      $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
+        dsll32    $zero,18             # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
+        dsll32    $zero,$zero,18       # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
+        dsllv     $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
+        dsra      $gp,10               # CHECK: dsra $gp, $gp, 10           # encoding: [0x00,0x1c,0xe2,0xbb]
+        dsra      $gp,$s2,10           # CHECK: dsra $gp, $18, 10           # encoding: [0x00,0x12,0xe2,0xbb]
+        dsra      $gp,$s2,$s3          # CHECK: dsrav $gp, $18, $19         # encoding: [0x02,0x72,0xe0,0x17]
+        dsra32    $gp,10               # CHECK: dsra32 $gp, $gp, 10         # encoding: [0x00,0x1c,0xe2,0xbf]
+        dsra32    $gp,$s2,10           # CHECK: dsra32 $gp, $18, 10         # encoding: [0x00,0x12,0xe2,0xbf]
+        dsrav     $gp,$s2,$s3          # CHECK: dsrav $gp, $18, $19         # encoding: [0x02,0x72,0xe0,0x17]
+        dsrl      $s3,23               # CHECK: dsrl $19, $19, 23           # encoding: [0x00,0x13,0x9d,0xfa]
+        dsrl      $s3,$6,23            # CHECK: dsrl $19, $6, 23            # encoding: [0x00,0x06,0x9d,0xfa]
+        dsrl      $s3,$6,$s4           # CHECK: dsrlv $19, $6, $20          # encoding: [0x02,0x86,0x98,0x16]
+        dsrl32    $s3,23               # CHECK: dsrl32 $19, $19, 23         # encoding: [0x00,0x13,0x9d,0xfe]
+        dsrl32    $s3,$6,23            # CHECK: dsrl32 $19, $6, 23          # encoding: [0x00,0x06,0x9d,0xfe]
+        dsrlv     $s3,$6,$s4           # CHECK: dsrlv $19, $6, $20          # encoding: [0x02,0x86,0x98,0x16]
+        dsub      $a3,$s6,$8
+        dsub      $a3,$s6,$8
+        dsub      $sp,$s4,-27705       # CHECK: daddi $sp, $20, 27705  # encoding: [0x62,0x9d,0x6c,0x39]
+        dsub      $sp,-27705           # CHECK: daddi $sp, $sp, 27705  # encoding: [0x63,0xbd,0x6c,0x39]
+        dsubi     $sp,$s4,-27705       # CHECK: daddi $sp, $20, 27705  # encoding: [0x62,0x9d,0x6c,0x39]
+        dsubi     $sp,-27705           # CHECK: daddi $sp, $sp, 27705  # encoding: [0x63,0xbd,0x6c,0x39]
+        dsubu     $a1,$a1,$k0
+        dsubu     $a1,$a1,$k0
+        dsubu     $15,$11,5025         # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
+        dsubu     $14,-4586            # CHECK: daddiu $14, $14, 4586  # encoding: [0x65,0xce,0x11,0xea]
+        ehb                            # CHECK: ehb # encoding:  [0x00,0x00,0x00,0xc0]
+        ei        $14                  # CHECK: ei  $14       # encoding: [0x41,0x6e,0x60,0x20]
+        ei                             # CHECK: ei            # encoding: [0x41,0x60,0x60,0x20]
+        eret
+        floor.l.d $f26,$f7
+        floor.l.s $f12,$f5
+        floor.w.d $f14,$f11
+        floor.w.s $f8,$f9
+        jr.hb     $4                   # CHECK: jr.hb  $4 # encoding: [0x00,0x80,0x04,0x08]
+        jalr.hb   $4                   # CHECK: jalr.hb  $4 # encoding: [0x00,0x80,0xfc,0x09]
+        jalr.hb   $4, $5               # CHECK: jalr.hb  $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
+        lb        $24,-14515($10)
+        lbu       $8,30195($v1)
+        ld        $sp,-28645($s1)
+        ldc1      $f11,16391($s0)
+        ldc2      $8,-21181($at)        # CHECK: ldc2 $8, -21181($1)   # encoding: [0xd8,0x28,0xad,0x43]
+        ldl       $24,-4167($24)
+        ldr       $14,-30358($s4)
+        ldxc1     $f8,$s7($15)
+        lh        $11,-8556($s5)
+        lhu       $s3,-22851($v0)
+        li        $at,-29773
+        li        $zero,-29889
+        ll        $v0,-7321($s2)       # CHECK: ll $2, -7321($18)     # encoding: [0xc2,0x42,0xe3,0x67]
+        lld       $zero,-14736($ra)    # CHECK: lld $zero, -14736($ra) # encoding: [0xd3,0xe0,0xc6,0x70]
+        luxc1     $f19,$s6($s5)
+        lw        $8,5674($a1)
+        lwc1      $f16,10225($k0)
+        lwc2      $18,-841($a2)        # CHECK: lwc2 $18, -841($6)     # encoding: [0xc8,0xd2,0xfc,0xb7]
+        lwl       $s4,-4231($15)
+        lwr       $zero,-19147($gp)
+        lwu       $s3,-24086($v1)
+        lwxc1     $f12,$s1($s8)
+        madd      $s6,$13
+        madd      $zero,$9
+        madd.s    $f1,$f31,$f19,$f25
+        maddu     $s3,$gp
+        maddu     $24,$s2
+        mfc0      $a2,$14,1
+        mfc1      $a3,$f27
+        mfhc1     $s8,$f24
+        mfhi      $s3
+        mfhi      $sp
+        mflo      $s1
+        mov.d     $f20,$f14
+        mov.s     $f2,$f27
+        move      $a0,$a3
+        move      $s5,$a0
+        move      $s8,$a0
+        move      $25,$a2
+        movf      $gp,$8,$fcc7
+        movf.d    $f6,$f11,$fcc5
+        movf.s    $f23,$f5,$fcc6
+        movn      $v1,$s1,$s0
+        movn.d    $f27,$f21,$k0
+        movn.s    $f12,$f0,$s7
+        movt      $zero,$s4,$fcc5
+        movt.d    $f0,$f2,$fcc0
+        movt.s    $f30,$f2,$fcc1
+        movz      $a1,$s6,$9
+        movz.d    $f12,$f29,$9
+        movz.s    $f25,$f7,$v1
+        msub      $s7,$k1
+        msub.s    $f12,$f19,$f10,$f16
+        msubu     $15,$a1
+        mtc0      $9,$29,3
+        mtc1      $s8,$f9
+        mthc1     $zero,$f16
+        mthi      $s1
+        mtlo      $sp
+        mtlo      $25
+        mul       $s0,$s4,$at
+        mul.d     $f20,$f20,$f16
+        mul.s     $f30,$f10,$f2
+        mult      $sp,$s4
+        mult      $sp,$v0
+        multu     $gp,$k0
+        multu     $9,$s2
+        negu      $2                   # CHECK: negu $2, $2            # encoding: [0x00,0x02,0x10,0x23]
+        negu      $2,$3                # CHECK: negu $2, $3            # encoding: [0x00,0x03,0x10,0x23]
+        neg.d     $f27,$f18
+        neg.s     $f1,$f15
+        nmadd.s   $f0,$f5,$f25,$f12
+        nmsub.s   $f1,$f24,$f19,$f4
+        nop
+        nor       $a3,$zero,$a3
+        or        $12,$s0,$sp
+        or        $2, 4                # CHECK: ori $2, $2, 4           # encoding: [0x34,0x42,0x00,0x04]
+        pause                          # CHECK: pause # encoding:  [0x00,0x00,0x01,0x40]
+        pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
+        # FIXME: Use the code generator in order to print the .set directives
+        #        instead of the instruction printer.
+        rdhwr     $sp,$11              # CHECK:      .set  push
+                                       # CHECK-NEXT: .set  mips32r2
+                                       # CHECK-NEXT: rdhwr $sp, $11
+                                       # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
+        rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
+        rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]
+        rotrv     $1,$14,$15           # CHECK: rotrv $1, $14, $15      # encoding: [0x01,0xee,0x08,0x46]
+        round.l.d $f12,$f1
+        round.l.s $f25,$f5
+        round.w.d $f6,$f4
+        round.w.s $f27,$f28
+        sb        $s6,-19857($14)
+        sc        $15,18904($s3)       # CHECK: sc $15, 18904($19)     # encoding: [0xe2,0x6f,0x49,0xd8]
+        scd       $15,-8243($sp)       # CHECK: scd $15, -8243($sp)    # encoding: [0xf3,0xaf,0xdf,0xcd]
+        sdbbp                          # CHECK: sdbbp                  # encoding: [0x70,0x00,0x00,0x3f]
+        sdbbp     34                   # CHECK: sdbbp 34               # encoding: [0x70,0x00,0x08,0xbf]
+        sd        $12,5835($10)
+        sdc1      $f31,30574($13)
+        sdc2      $20,23157($s2)       # CHECK: sdc2 $20, 23157($18)   # encoding: [0xfa,0x54,0x5a,0x75]
+        sdl       $a3,-20961($s8)
+        sdr       $11,-20423($12)
+        sdxc1     $f11,$10($14)
+        seb       $25,$15
+        seh       $v1,$12
+        sh        $14,-6704($15)
+        sll       $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
+        sll       $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
+        sll       $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
+        sllv      $a3,$zero,$9         # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
+        slt       $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
+        slti      $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
+        sltiu     $25,$25,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
+        sltu      $s4,$s5,$11          # CHECK: sltu  $20, $21, $11    # encoding: [0x02,0xab,0xa0,0x2b]
+        sltu      $24,$25,-15531       # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
+        sqrt.d    $f17,$f22
+        sqrt.s    $f0,$f1
+        sra       $s1,15               # CHECK: sra $17, $17, 15       # encoding: [0x00,0x11,0x8b,0xc3]
+        sra       $s1,$s7,15           # CHECK: sra $17, $23, 15       # encoding: [0x00,0x17,0x8b,0xc3]
+        sra       $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
+        srav      $s1,$s7,$sp          # CHECK: srav $17, $23, $sp     # encoding: [0x03,0xb7,0x88,0x07]
+        srl       $2,7                 # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+        srl       $2,$2,7              # CHECK: srl $2, $2, 7          # encoding: [0x00,0x02,0x11,0xc2]
+        srl       $25,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
+        srlv      $25,$s4,$a0          # CHECK: srlv $25, $20, $4      # encoding: [0x00,0x94,0xc8,0x06]
+        ssnop                          # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
+        sub       $s6,$s3,$12
+        sub       $22,$17,-3126        # CHECK: addi $22, $17, 3126    # encoding: [0x22,0x36,0x0c,0x36]
+        sub       $13,6512             # CHECK: addi $13, $13, -6512   # encoding: [0x21,0xad,0xe6,0x90]
+        sub.d     $f18,$f3,$f17
+        sub.s     $f23,$f22,$f22
+        subu      $sp,$s6,$s6
+        suxc1     $f12,$k1($13)
+        sw        $ra,-10160($sp)
+        swc1      $f6,-8465($24)
+        swc2      $25,24880($s0)       # CHECK: swc2 $25, 24880($16)   # encoding: [0xea,0x19,0x61,0x30]
+        swl       $15,13694($s3)
+        swr       $s1,-26590($14)
+        swxc1     $f19,$12($k0)
+        sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+        sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+        teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
+        teq       $5,$7,620            # CHECK: teq $5, $7, 620        # encoding: [0x00,0xa7,0x9b,0x34]
+        teqi      $s5,-17504
+        tge       $7,$10               # CHECK: tge $7, $10            # encoding: [0x00,0xea,0x00,0x30]
+        tge       $5,$19,340           # CHECK: tge $5, $19, 340       # encoding: [0x00,0xb3,0x55,0x30]
+        tgei      $s1,5025
+        tgeiu     $sp,-28621
+        tgeu      $22,$28              # CHECK: tgeu $22, $gp          # encoding: [0x02,0xdc,0x00,0x31]
+        tgeu      $20,$14,379          # CHECK: tgeu $20, $14, 379     # encoding: [0x02,0x8e,0x5e,0xf1]
+        tlbp                           # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
+        tlbr                           # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
+        tlbwi                          # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
+        tlbwr                          # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
+        tlt       $15,$13              # CHECK: tlt $15, $13           # encoding: [0x01,0xed,0x00,0x32]
+        tlt       $2,$19,133           # CHECK: tlt $2, $19, 133       # encoding: [0x00,0x53,0x21,0x72]
+        tlti      $14,-21059
+        tltiu     $ra,-5076
+        tltu      $11,$16              # CHECK: tltu $11, $16          # encoding: [0x01,0x70,0x00,0x33]
+        tltu      $16,$29,1016         # CHECK: tltu $16, $sp, 1016    # encoding: [0x02,0x1d,0xfe,0x33]
+        tne       $6,$17               # CHECK: tne $6, $17            # encoding: [0x00,0xd1,0x00,0x36]
+        tne       $7,$8,885            # CHECK: tne $7, $8, 885        # encoding: [0x00,0xe8,0xdd,0x76]
+        tnei      $12,-29647
+        trunc.l.d $f23,$f23
+        trunc.l.s $f28,$f31
+        trunc.w.d $f22,$f15
+        trunc.w.s $f28,$f30
+        xor       $s2,$a0,$s8
+        wsbh      $k1,$9
diff --git a/test/MC/Mips/set-arch.s b/test/MC/Mips/set-arch.s
index 626746836ad..834718c5d55 100644
--- a/test/MC/Mips/set-arch.s
+++ b/test/MC/Mips/set-arch.s
@@ -16,12 +16,24 @@
     clo         $2, $2
     .set arch=mips32r2
     rotr        $2, $2, 15
+    .set arch=mips32
+    .set arch=mips32r3
+    rotr        $2, $2, 15
+    .set arch=mips32
+    .set arch=mips32r5
+    rotr        $2, $2, 15
     .set arch=mips32r6
     mod         $2, $4, $6
     .set arch=mips64
     daddi       $2, $2, 10
     .set arch=mips64r2
     drotr32     $1, $14, 15
+    .set arch=mips64
+    .set arch=mips64r3
+    drotr32     $1, $14, 15
+    .set arch=mips64
+    .set arch=mips64r5
+    drotr32     $1, $14, 15
     .set arch=mips64r6
     mod         $2, $4, $6
     .set arch=cnmips
diff --git a/test/MC/Mips/set-mips-directives-bad.s b/test/MC/Mips/set-mips-directives-bad.s
index 67269875659..68a0da856b2 100644
--- a/test/MC/Mips/set-mips-directives-bad.s
+++ b/test/MC/Mips/set-mips-directives-bad.s
@@ -21,10 +21,22 @@
         rotr    $2,15 # CHECK: error: instruction requires a CPU feature not currently enabled
         .set mips32r2
         mod $2, $4, $6 # CHECK: error:instruction requires a CPU feature not currently enabled
+        .set mips64r3
+        .set mips32r3
+        daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled
+        .set mips64r3
+        .set mips32r5
+        daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled
         .set mips32r6
         daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled
         .set mips64
         drotr32 $1,$14,15 # CHECK: error: instruction requires a CPU feature not currently enabled
         .set mips64r2
         mod $2, $4, $6 # CHECK: error: instruction requires a CPU feature not currently enabled
+        .set mips64r6
+        .set mips64r3
+        mod $2, $4, $6 # CHECK: error: instruction requires a CPU feature not currently enabled
+        .set mips64r6
+        .set mips64r5
+        mod $2, $4, $6 # CHECK: error: instruction requires a CPU feature not currently enabled
 
diff --git a/test/MC/Mips/set-mips-directives.s b/test/MC/Mips/set-mips-directives.s
index 96c23088676..5225968aadd 100644
--- a/test/MC/Mips/set-mips-directives.s
+++ b/test/MC/Mips/set-mips-directives.s
@@ -17,12 +17,24 @@
         clo  $2,$2
         .set mips32r2
         rotr    $2,15
+        .set mips32
+        .set mips32r3
+        rotr    $2,15
+        .set mips32
+        .set mips32r5
+        rotr    $2,15
         .set mips32r6
         mod $2, $4, $6
         .set mips64
         daddi $2, $2, 10
         .set mips64r2
         drotr32 $1,$14,15
+        .set mips64
+        .set mips64r3
+        drotr32 $1,$14,15
+        .set mips64
+        .set mips64r5
+        drotr32 $1,$14,15
         .set mips64r6
         mod $2, $4, $6
 
@@ -41,11 +53,23 @@
 # CHECK: clo $2, $2
 # CHECK: .set mips32r2
 # CHECK: rotr $2, $2, 15
+# CHECK: .set mips32
+# CHECK: .set mips32r3
+# CHECK: rotr $2, $2, 15
+# CHECK: .set mips32
+# CHECK: .set mips32r5
+# CHECK: rotr $2, $2, 15
 # CHECK: .set mips32r6
 # CHECK: mod $2, $4, $6
 # CHECK: .set mips64
 # CHECK: daddi $2, $2, 10
 # CHECK: .set mips64r2
 # CHECK:  drotr32 $1, $14, 15
+# CHECK: .set mips64
+# CHECK: .set mips64r3
+# CHECK:  drotr32 $1, $14, 15
+# CHECK: .set mips64
+# CHECK: .set mips64r5
+# CHECK:  drotr32 $1, $14, 15
 # CHECK: .set mips64r6
 # CHECK: mod $2, $4, $6