From 7efadce56e2a1e6a92edbc5c9d4531cfd88a019b Mon Sep 17 00:00:00 2001
From: Andrew Lenharth <andrewl@lenharth.org>
Date: Mon, 31 Jan 2005 01:44:26 +0000
Subject: [PATCH] fp to int and back conversion sequences

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19944 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Alpha/AlphaISelPattern.cpp | 46 +++++++++++++++++++--------
 lib/Target/Alpha/AlphaInstrInfo.td    |  2 +-
 2 files changed, 34 insertions(+), 14 deletions(-)

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index a92aa1b2c6d..731f30337a9 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -412,6 +412,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
     {
       assert (N.getOperand(0).getValueType() == MVT::i64 && "only quads can be loaded from");
       Tmp1 = SelectExpr(N.getOperand(0));  // Get the operand register
+      Tmp2 = MakeReg(MVT::f64);
 
       //The hard way:
       // Spill the integer to memory and reload it from there.
@@ -419,12 +420,10 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
       MachineFunction *F = BB->getParent();
       int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size);
 
-      //STL LDS
-      //STQ LDT
-      Opc = DestType == MVT::f64 ? Alpha::STQ : Alpha::STL;
-      BuildMI(BB, Opc, 2).addReg(Tmp1).addFrameIndex(FrameIdx).addReg(Alpha::F31);
-      Opc = DestType == MVT::f64 ? Alpha::LDT : Alpha::LDS;
-      BuildMI(BB, Opc, 1, Result).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+      BuildMI(BB, Alpha::STQ, 3).addReg(Tmp1).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+      BuildMI(BB, Alpha::LDT, 2, Tmp2).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+      Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
+      BuildMI(BB, Opc, 1, Result).addReg(Tmp2);
 
       //The easy way: doesn't work
 //       //so these instructions are not supported on ev56
@@ -965,13 +964,34 @@ unsigned ISel::SelectExpr(SDOperand N) {
     return Result;
 //     //  case ISD::UINT_TO_FP:
 
-//   case ISD::FP_TO_SINT:
-//     assert (N.getValueType() == MVT::f64 && "Only can convert for doubles");
-//     Tmp1 = SelectExpr(N.getOperand(0));  // Get the operand register
-//     Tmp2 = MakeReg(SrcTy);
-//     BuildMI(BB, CVTTQ, 1, Tmp2).addReg(Tmp1);
-//     BuildMI(BB, FTOIT, 1, Result).addReg(Tmp2);
-//     return result;
+
+  case ISD::FP_TO_SINT:
+   {
+      assert (DestType == MVT::i64 && "only quads can be loaded to");
+      MVT::ValueType SrcType = N.getOperand(0).getValueType();
+      Tmp1 = SelectExpr(N.getOperand(0));  // Get the operand register
+
+      //The hard way:
+      // Spill the integer to memory and reload it from there.
+      unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
+      MachineFunction *F = BB->getParent();
+      int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8);
+
+      //CVTTQ STT LDQ
+      //CVTST CVTTQ STT LDQ
+      if (SrcType == MVT::f32)
+        {
+          Tmp2 = MakeReg(MVT::f64);
+          BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1);
+          Tmp1 = Tmp2;
+        }
+      Tmp2 = MakeReg(MVT::f64);
+      BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Tmp1);
+      BuildMI(BB, Alpha::STT, 3).addReg(Tmp2).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+      BuildMI(BB, Alpha::LDQ, 2, Result).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+      
+      return Result;
+   }
 
 //     //  case ISD::FP_TO_UINT: 
  
diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td
index a1edf3d4116..5f4d21e99a2 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/lib/Target/Alpha/AlphaInstrInfo.td
@@ -331,7 +331,7 @@ def ITOFT : FPForm<0x14, 0x024, (ops FPRC:$RC, GPRC:$RA), "itoft $RA,$RC">; //In
 def CVTQS : FPForm<0x16, 0x0BC,  (ops FPRC:$RC, FPRC:$RA), "cvtqs $RA,$RC">; //Convert quadword to S_floating
 def CVTQT : FPForm<0x16, 0x0BE,  (ops FPRC:$RC, FPRC:$RA), "cvtqt $RA,$RC">; //Convert quadword to T_floating
 def CVTST : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtst $RA,$RC">; //Convert S_floating to T_floating
-//CVTTQ F-P 16.0AF Convert T_floating to quadword
+def CVTTQ : FPForm<0x16, 0x0AF,  (ops FPRC:$RC, FPRC:$RA), "cvttq $RA,$RC">; //Convert T_floating to quadword
 def CVTTS : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtts $RA,$RC">; //Convert T_floating to S_floating
 
 //S_floating : IEEE Single