mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
All sorts of stuff.
Getting in on the custom lowering thing, yay evilness with fp setcc, yuck trivial int select, hmmm in memory args for functions, yay DIV and REM, always handy. They should be custom lowered though. Lots more stuff compiles now (go go single source!). Of course, none of it probably works, but that is what the nightly tester can find out :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24533 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
5b5b8c2755
commit
7f0db91f86
@ -16,6 +16,7 @@
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#include "AlphaTargetMachine.h"
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#include "AlphaISelLowering.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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@ -278,6 +279,7 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
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CurDAG->SelectNodeTo(N, Alpha::LDAr, MVT::i64, CPI, Tmp);
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return SDOperand(N, 0);
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}
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break;
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}
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case ISD::ConstantFP:
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if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
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@ -296,7 +298,76 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
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} else {
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abort();
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}
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break;
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}
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::UREM:
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case ISD::SREM:
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if (MVT::isInteger(N->getValueType(0))) {
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const char* opstr = 0;
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switch(N->getOpcode()) {
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case ISD::UREM: opstr = "__remqu"; break;
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case ISD::SREM: opstr = "__remq"; break;
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case ISD::UDIV: opstr = "__divqu"; break;
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case ISD::SDIV: opstr = "__divq"; break;
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}
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SDOperand Tmp1 = Select(N->getOperand(0)),
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Tmp2 = Select(N->getOperand(1)),
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Addr = CurDAG->getExternalSymbol(opstr, AlphaLowering.getPointerTy());
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SDOperand Tmp3 = Select(Addr);
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SDOperand Chain = CurDAG->getCopyToReg(CurDAG->getRoot(), Alpha::R24,
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Tmp1, SDOperand());
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Chain = CurDAG->getCopyToReg(CurDAG->getRoot(), Alpha::R25,
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Tmp2, Chain.getValue(1));
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Chain = CurDAG->getCopyToReg(CurDAG->getRoot(), Alpha::R27,
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Tmp3, Chain.getValue(1));
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Chain = CurDAG->getTargetNode(Alpha::JSRs, MVT::i64, MVT::Flag,
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CurDAG->getRegister(Alpha::R27, MVT::i64),
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getI64Imm(0));
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return CurDAG->getCopyFromReg(Chain.getValue(1), Alpha::R27, MVT::i64,
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Chain.getValue(1));
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}
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break;
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case ISD::SETCC:
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if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
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unsigned Opc = Alpha::WTF;
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ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
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bool rev = false;
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switch(CC) {
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default: N->dump(); assert(0 && "Unknown FP comparison!");
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case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
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case ISD::SETLT: Opc = Alpha::CMPTLT; break;
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case ISD::SETLE: Opc = Alpha::CMPTLE; break;
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case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
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case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
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//case ISD::SETNE: Opc = Alpha::CMPTEQ; inv = true; break;
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};
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SDOperand tmp1 = Select(N->getOperand(0)),
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tmp2 = Select(N->getOperand(1));
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SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64,
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rev?tmp2:tmp1,
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rev?tmp1:tmp2);
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SDOperand LD;
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if (AlphaLowering.hasITOF()) {
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LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, cmp);
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} else {
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int FrameIdx =
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CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
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SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
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SDOperand ST = CurDAG->getTargetNode(Alpha::STT, MVT::Other,
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cmp, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
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LD = CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
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CurDAG->getRegister(Alpha::R31, MVT::i64),
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ST);
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}
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SDOperand FP = CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
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CurDAG->getRegister(Alpha::R31, MVT::i64),
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LD);
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return FP;
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}
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break;
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}
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return SelectCode(Op);
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@ -328,13 +399,26 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
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for (int i = 0; i < std::min(6, count); ++i) {
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if (MVT::isInteger(TypeOperands[i])) {
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Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i]);
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} else if (TypeOperands[i] == MVT::f64 || TypeOperands[i] == MVT::f64) {
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} else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
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Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i]);
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} else
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assert(0 && "Unknown operand");
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}
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assert(CallOperands.size() <= 6 && "Too big a call");
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for (int i = 6; i < count; ++i) {
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unsigned Opc = Alpha::WTF;
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if (MVT::isInteger(TypeOperands[i])) {
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Opc = Alpha::STQ;
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} else if (TypeOperands[i] == MVT::f32) {
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Opc = Alpha::STS;
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} else if (TypeOperands[i] == MVT::f64) {
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Opc = Alpha::STT;
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} else
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assert(0 && "Unknown operand");
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Chain = CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i],
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getI64Imm((i - 6) * 8),
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CurDAG->getRegister(Alpha::R30, MVT::i64),
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Chain);
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}
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Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr);
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// Finally, once everything is in registers to pass to the call, emit the
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@ -72,6 +72,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
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setOperationAction(ISD::FREM, MVT::f64, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
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setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
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if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
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setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
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@ -101,10 +102,12 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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computeRegisterProperties();
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addLegalFPImmediate(+0.0); //F31
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addLegalFPImmediate(-0.0); //-F31
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computeRegisterProperties();
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useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
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}
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@ -385,3 +388,31 @@ void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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default: assert(0 && "Wasn't expecting to be able to lower this!");
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case ISD::SINT_TO_FP: {
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assert(MVT::i64 == Op.getOperand(0).getValueType() &&
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"Unhandled SINT_TO_FP type in custom expander!");
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SDOperand LD;
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bool isDouble = MVT::f64 == Op.getValueType();
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if (useITOF) {
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LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
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} else {
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int FrameIdx =
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DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
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SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
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SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
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Op.getOperand(0), FI, DAG.getSrcValue(0));
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LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
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}
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SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
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isDouble?MVT::f64:MVT::f32, LD);
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return FP;
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}
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}
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return SDOperand();
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}
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@ -25,6 +25,8 @@ namespace llvm {
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enum NodeType {
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// Start the numbering where the builting ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END+Alpha::INSTRUCTION_LIST_END,
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//These corrospond to the identical Instruction
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ITOFT_, FTOIT_, CVTQT_, CVTQS_,
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};
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}
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@ -33,9 +35,14 @@ namespace llvm {
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int VarArgsBase; // What is the base FrameIndex
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unsigned GP; //GOT vreg
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unsigned RA; //Return Address
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bool useITOF;
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public:
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AlphaTargetLowering(TargetMachine &TM);
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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/// LowerArguments - This hook must be implemented to indicate how we should
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/// lower the arguments for the specified function, into the specified DAG.
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virtual std::vector<SDOperand>
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@ -61,6 +68,7 @@ namespace llvm {
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void restoreRA(MachineBasicBlock* BB);
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unsigned getVRegGP() { return GP; }
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unsigned getVRegRA() { return RA; }
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bool hasITOF() { return useITOF; }
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};
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}
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@ -1559,17 +1559,17 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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}
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return Result;
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case ISD::SINT_TO_FP:
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{
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assert (N.getOperand(0).getValueType() == MVT::i64
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&& "only quads can be loaded from");
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Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
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Tmp2 = MakeReg(MVT::f64);
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MoveInt2FP(Tmp1, Tmp2, true);
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Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
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BuildMI(BB, Opc, 1, Result).addReg(Tmp2);
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return Result;
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}
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case AlphaISD::CVTQT_:
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BuildMI(BB, Alpha::CVTQT, 1, Result).addReg(SelectExpr(N.getOperand(0)));
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return Result;
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case AlphaISD::CVTQS_:
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BuildMI(BB, Alpha::CVTQS, 1, Result).addReg(SelectExpr(N.getOperand(0)));
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return Result;
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case AlphaISD::ITOFT_:
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BuildMI(BB, Alpha::ITOFT, 1, Result).addReg(SelectExpr(N.getOperand(0)));
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return Result;
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case ISD::AssertSext:
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case ISD::AssertZext:
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@ -40,6 +40,16 @@ class InstAlpha<bits<6> op, dag OL, string asmstr>
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}
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//3.3.1
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class MFormAlt<bits<6> opcode, string asmstr>
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: InstAlphaAlt<opcode, asmstr> {
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bits<5> Ra;
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bits<16> disp;
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bits<5> Rb;
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-0} = disp;
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}
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class MForm<bits<6> opcode, string asmstr>
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: InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), asmstr> {
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bits<5> Ra;
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@ -12,6 +12,20 @@
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include "AlphaInstrFormats.td"
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//********************
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//Custom DAG Nodes
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//********************
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def SDTFPUnaryOpUnC : SDTypeProfile<1, 1, [
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SDTCisFP<1>, SDTCisFP<0>
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]>;
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def Alpha_itoft : SDNode<"AlphaISD::ITOFT_", SDTIntToFPOp, []>;
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def Alpha_ftoit : SDNode<"AlphaISD::FTOIT_", SDTFPToIntOp, []>;
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def Alpha_cvtqt : SDNode<"AlphaISD::CVTQT_", SDTFPUnaryOpUnC, []>;
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def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>;
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//********************
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//Paterns for matching
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//********************
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@ -143,6 +157,10 @@ def CMOVLTi : OForm4L< 0x11, 0x44, "cmovlt $RCOND,$L,$RDEST">; //CMOVE if RCOND
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def CMOVNE : OForm4< 0x11, 0x26, "cmovne $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND != zero
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def CMOVNEi : OForm4L< 0x11, 0x26, "cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero
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//FIXME: fold setcc with select
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def : Pat<(select GPRC:$which, GPRC:$src1, GPRC:$src2),
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(CMOVEQ GPRC:$src1, GPRC:$src2, GPRC:$which)>;
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//conditional moves, fp
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let OperandList = (ops F8RC:$RDEST, F8RC:$RSRC2, F8RC:$RSRC, F8RC:$RCOND),
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isTwoAddress = 1 in {
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@ -409,12 +427,16 @@ def LDBU : MForm<0x0A, "ldbu $RA,$DISP($RB)">; //Load zero-extended byte
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def LDWU : MForm<0x0C, "ldwu $RA,$DISP($RB)">; //Load zero-extended word
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//Stores, float
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def STS : MForm<0x26, "sts $RA,$DISP($RB)">; //Store S_floating
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def STT : MForm<0x27, "stt $RA,$DISP($RB)">; //Store T_floating
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let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def STS : MFormAlt<0x26, "sts $RA,$DISP($RB)">; //Store S_floating
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let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def STT : MFormAlt<0x27, "stt $RA,$DISP($RB)">; //Store T_floating
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//Loads, float
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def LDS : MForm<0x22, "lds $RA,$DISP($RB)">; //Load S_floating
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def LDT : MForm<0x23, "ldt $RA,$DISP($RB)">; //Load T_floating
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let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def LDS : MFormAlt<0x22, "lds $RA,$DISP($RB)">; //Load S_floating
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let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def LDT : MFormAlt<0x23, "ldt $RA,$DISP($RB)">; //Load T_floating
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//Load address
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def LDA : MForm<0x08, "lda $RA,$DISP($RB)">; //Load address
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@ -428,8 +450,10 @@ def LDBUr : MForm<0x0A, "ldbu $RA,$DISP($RB)\t\t!gprellow">; //Load zero-extende
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def LDWUr : MForm<0x0C, "ldwu $RA,$DISP($RB)\t\t!gprellow">; //Load zero-extended word
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//Loads, float, Rellocated Low form
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def LDSr : MForm<0x22, "lds $RA,$DISP($RB)\t\t!gprellow">; //Load S_floating
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def LDTr : MForm<0x23, "ldt $RA,$DISP($RB)\t\t!gprellow">; //Load T_floating
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let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def LDSr : MFormAlt<0x22, "lds $RA,$DISP($RB)\t\t!gprellow">; //Load S_floating
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let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def LDTr : MFormAlt<0x23, "ldt $RA,$DISP($RB)\t\t!gprellow">; //Load T_floating
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//Load address, rellocated low and high form
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def LDAr : MForm<0x08, "lda $RA,$DISP($RB)\t\t!gprellow">; //Load address
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@ -450,8 +474,10 @@ def STLr : MForm<0x2C, "stl $RA,$DISP($RB)\t\t!gprellow">; // Store longword
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def STQr : MForm<0x2D, "stq $RA,$DISP($RB)\t\t!gprellow">; //Store quadword
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//Stores, float
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def STSr : MForm<0x26, "sts $RA,$DISP($RB)\t\t!gprellow">; //Store S_floating
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def STTr : MForm<0x27, "stt $RA,$DISP($RB)\t\t!gprellow">; //Store T_floating
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let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def STSr : MFormAlt<0x26, "sts $RA,$DISP($RB)\t\t!gprellow">; //Store S_floating
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let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def STTr : MFormAlt<0x27, "stt $RA,$DISP($RB)\t\t!gprellow">; //Store T_floating
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//Branches, int
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@ -533,17 +559,21 @@ def CMPTUN : FPForm<0x16, 0x5A4, "cmptun/su $RA,$RB,$RC", []>;
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let OperandList = (ops GPRC:$RC, F4RC:$RA), Fb = 31 in
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def FTOIS : FPForm<0x1C, 0x078, "ftois $RA,$RC",[]>; //Floating to integer move, S_floating
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let OperandList = (ops GPRC:$RC, F8RC:$RA), Fb = 31 in
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def FTOIT : FPForm<0x1C, 0x070, "ftoit $RA,$RC",[]>; //Floating to integer move, T_floating
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def FTOIT : FPForm<0x1C, 0x070, "ftoit $RA,$RC",
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[(set GPRC:$RC, (Alpha_ftoit F8RC:$RA))]>; //Floating to integer move
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let OperandList = (ops F4RC:$RC, GPRC:$RA), Fb = 31 in
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def ITOFS : FPForm<0x14, 0x004, "itofs $RA,$RC",[]>; //Integer to floating move, S_floating
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let OperandList = (ops F8RC:$RC, GPRC:$RA), Fb = 31 in
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def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC",[]>; //Integer to floating move, T_floating
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def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC",
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[(set F8RC:$RC, (Alpha_itoft GPRC:$RA))]>; //Integer to floating move
|
||||
|
||||
|
||||
let OperandList = (ops F4RC:$RC, F8RC:$RB), Fa = 31 in
|
||||
def CVTQS : FPForm<0x16, 0x7BC, "cvtqs/sui $RB,$RC",[]>; //Convert quadword to S_floating
|
||||
def CVTQS : FPForm<0x16, 0x7BC, "cvtqs/sui $RB,$RC",
|
||||
[(set F4RC:$RC, (Alpha_cvtqs F8RC:$RB))]>;
|
||||
let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in
|
||||
def CVTQT : FPForm<0x16, 0x7BE, "cvtqt/sui $RB,$RC",[]>; //Convert quadword to T_floating
|
||||
def CVTQT : FPForm<0x16, 0x7BE, "cvtqt/sui $RB,$RC",
|
||||
[(set F8RC:$RC, (Alpha_cvtqt F8RC:$RB))]>;
|
||||
let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in
|
||||
def CVTTQ : FPForm<0x16, 0x52F, "cvttq/svc $RB,$RC",[]>; //Convert T_floating to quadword
|
||||
let OperandList = (ops F8RC:$RC, F4RC:$RB), Fa = 31 in
|
||||
@ -648,3 +678,11 @@ def : Pat<(sext_inreg GPRC:$RB, i32),
|
||||
def : Pat<(select GPRC:$which, GPRC:$src1, GPRC:$src2),
|
||||
(CMOVEQ GPRC:$src1, GPRC:$src2, GPRC:$which)>; //may be CMOVNE
|
||||
|
||||
def : Pat<(fabs F8RC:$RB),
|
||||
(CPYST F31, F8RC:$RB)>;
|
||||
def : Pat<(fabs F4RC:$RB),
|
||||
(CPYSS F31, F4RC:$RB)>;
|
||||
def : Pat<(fneg F8RC:$RB),
|
||||
(CPYSNT F8RC:$RB, F8RC:$RB)>;
|
||||
def : Pat<(fneg F4RC:$RB),
|
||||
(CPYSNS F4RC:$RB, F4RC:$RB)>;
|
||||
|
||||
@ -78,7 +78,6 @@ def F30 : FPR<30, "$f30">; def F31 : FPR<31, "$f31">;
|
||||
// $28 is undefined after any and all calls
|
||||
|
||||
/// Register classes
|
||||
// Don't allocate 15, 28, 30, 31
|
||||
def GPRC : RegisterClass<"Alpha", i64, 64,
|
||||
// Volatile
|
||||
[R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
|
||||
@ -89,7 +88,8 @@ def GPRC : RegisterClass<"Alpha", i64, 64,
|
||||
R29, //global offset table address
|
||||
// Non-volatile
|
||||
R9, R10, R11, R12, R13, R14,
|
||||
R31 ]> //zero
|
||||
// Don't allocate 15, 30, 31
|
||||
R15, R30, R31 ]> //zero
|
||||
{
|
||||
let MethodProtos = [{
|
||||
iterator allocation_order_end(MachineFunction &MF) const;
|
||||
@ -97,7 +97,7 @@ def GPRC : RegisterClass<"Alpha", i64, 64,
|
||||
let MethodBodies = [{
|
||||
GPRCClass::iterator
|
||||
GPRCClass::allocation_order_end(MachineFunction &MF) const {
|
||||
return end()-1;
|
||||
return end()-3;
|
||||
}
|
||||
}];
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user