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Remove intrinsic specific instructions for CVTPD2DQ. Replace with patterns.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159105 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-06-24 05:33:24 +00:00
parent 3eab3c4d40
commit 7f2ea14c68
2 changed files with 12 additions and 25 deletions
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2
lib/Target/X86/X86InstrInfo.cpp
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@ -410,7 +410,6 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
{ X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
{ X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
{ X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
{ X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, TB_ALIGN_16 },
{ X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, TB_ALIGN_16 },
{ X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, TB_ALIGN_16 },
{ X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
@ -494,7 +493,6 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
// AVX 128-bit versions of foldable instructions
{ X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
{ X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
{ X86::Int_VCVTPD2DQrr, X86::Int_VCVTPD2DQrm, TB_ALIGN_16 },
{ X86::Int_VCVTPD2PSrr, X86::Int_VCVTPD2PSrm, TB_ALIGN_16 },
{ X86::Int_VCVTPS2DQrr, X86::Int_VCVTPS2DQrm, TB_ALIGN_16 },
{ X86::Int_VCVTPS2PDrr, X86::Int_VCVTPS2PDrm, 0 },

35
lib/Target/X86/X86InstrSSE.td
View File

@ -1861,30 +1861,19 @@ def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"cvtpd2dq\t{$src, $dst|$dst, $src}", [],
IIC_SSE_CVT_PD_RR>;
// SSE2 packed instructions with XD prefix
def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"vcvtpd2dq\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
IIC_SSE_CVT_PD_RR>,
XD, VEX, Requires<[HasAVX]>;
def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
"vcvtpd2dq\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse2_cvtpd2dq
(memop addr:$src)))],
IIC_SSE_CVT_PD_RM>,
XD, VEX, Requires<[HasAVX]>;
def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"cvtpd2dq\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
IIC_SSE_CVT_PD_RR>,
XD, Requires<[HasSSE2]>;
def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
"cvtpd2dq\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse2_cvtpd2dq
(memop addr:$src)))],
IIC_SSE_CVT_PD_RM>,
XD, Requires<[HasSSE2]>;
let Predicates = [HasAVX] in {
def : Pat<(int_x86_sse2_cvtpd2dq VR128:$src),
(VCVTPD2DQrr VR128:$src)>;
def : Pat<(int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)),
(VCVTPD2DQXrm addr:$src)>;
}
let Predicates = [HasSSE2] in {
def : Pat<(int_x86_sse2_cvtpd2dq VR128:$src),
(CVTPD2DQrr VR128:$src)>;
def : Pat<(int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)),
(CVTPD2DQrm addr:$src)>;
}
// Convert with truncation packed single/double fp to doubleword
// SSE2 packed instructions with XS prefix