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Ensure that the nop that should follow a bl call in PPC64 ELF actually does
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146664 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -61,6 +61,7 @@ void PPCHazardRecognizer440::EmitInstruction(SUnit *SU) {
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PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii)
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: TII(tii) {
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LastWasBL8_ELF = false;
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EndDispatchGroup();
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}
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@ -132,6 +133,14 @@ getHazardType(SUnit *SU, int Stalls) {
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unsigned Opcode = MI->getOpcode();
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// If the last instruction was a BL8_ELF, then the NOP must follow it
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// directly (this is strong requirement from the linker due to the ELF ABI).
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// We return only Hazard (and not NoopHazard) because if the NOP is necessary
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// then it will already be in the instruction stream (it is not always
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// necessary; tail calls, for example, do not need it).
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if (LastWasBL8_ELF && Opcode != PPC::NOP)
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return Hazard;
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bool isFirst, isSingle, isCracked, isLoad, isStore;
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PPCII::PPC970_Unit InstrType =
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GetInstrType(Opcode, isFirst, isSingle, isCracked,
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@ -190,6 +199,7 @@ void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) {
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return;
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unsigned Opcode = MI->getOpcode();
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LastWasBL8_ELF = (Opcode == PPC::BL8_ELF);
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bool isFirst, isSingle, isCracked, isLoad, isStore;
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PPCII::PPC970_Unit InstrType =
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@ -230,6 +240,7 @@ void PPCHazardRecognizer970::AdvanceCycle() {
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}
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void PPCHazardRecognizer970::Reset() {
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LastWasBL8_ELF = false;
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EndDispatchGroup();
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}
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@ -49,6 +49,9 @@ class PPCHazardRecognizer970 : public ScheduleHazardRecognizer {
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// HasCTRSet - If the CTR register is set in this group, disallow BCTRL.
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bool HasCTRSet;
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// Was the last instruction issued a BL8_ELF
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bool LastWasBL8_ELF;
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// StoredPtr - Keep track of the address of any store. If we see a load from
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// the same address (or one that aliases it), disallow the store. We can have
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// up to four stores in one dispatch group, hence we track up to 4.
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