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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 04:29:21 +00:00
* Lowercase the register names
* Parenthesize assert() expressions correctly * Fix spacing around for() and if() statements git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14384 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -426,8 +426,8 @@ void Printer::printOp(const MachineOperand &MO,
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}
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// FALLTHROUGH
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case MachineOperand::MO_MachineRegister:
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O << RI.get(MO.getReg()).Name;
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return;
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O << LowercaseString(RI.get(MO.getReg()).Name);
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return;
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case MachineOperand::MO_SignExtendedImmed:
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case MachineOperand::MO_UnextendedImmed:
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@ -511,15 +511,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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unsigned int ArgCount = Desc.TSFlags & PPC32II::ArgCountMask;
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unsigned int ArgType[5];
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ArgType[0] = (Desc.TSFlags>>PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask;
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ArgType[1] = (Desc.TSFlags>>PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask;
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ArgType[2] = (Desc.TSFlags>>PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask;
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ArgType[3] = (Desc.TSFlags>>PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask;
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ArgType[4] = (Desc.TSFlags>>PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask;
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ArgType[0] = (Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask;
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ArgType[1] = (Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask;
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ArgType[2] = (Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask;
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ArgType[3] = (Desc.TSFlags >> PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask;
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ArgType[4] = (Desc.TSFlags >> PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask;
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assert((Desc.TSFlags & PPC32II::VMX == 0) &&
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assert(((Desc.TSFlags & PPC32II::VMX) == 0) &&
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"Instruction requires VMX support");
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assert((Desc.TSFlags & PPC32II::PPC64 == 0) &&
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assert(((Desc.TSFlags & PPC32II::PPC64) == 0) &&
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"Instruction requires 64 bit support");
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//assert ( ValidOpcodes(MI, ArgType) && "Instruction has invalid inputs");
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++EmittedInsts;
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@ -566,7 +566,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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printOp(MI->getOperand(2));
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O << ")\n";
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} else {
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for(i = 0; i< ArgCount; i++) {
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for (i = 0; i < ArgCount; ++i) {
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if (ArgType[i] == PPC32II::Gpr0 &&
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MI->getOperand(i).getReg() == PPC32::R0)
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O << "0";
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@ -574,7 +574,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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//std::cout << "DEBUG " << (*(TM.getRegisterInfo())).get(MI->getOperand(i).getReg()).Name << "\n";
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printOp(MI->getOperand(i));
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}
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if( ArgCount - 1 == i)
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if (ArgCount - 1 == i)
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O << "\n";
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else
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O << ", ";
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@ -426,8 +426,8 @@ void Printer::printOp(const MachineOperand &MO,
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}
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// FALLTHROUGH
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case MachineOperand::MO_MachineRegister:
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O << RI.get(MO.getReg()).Name;
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return;
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O << LowercaseString(RI.get(MO.getReg()).Name);
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return;
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case MachineOperand::MO_SignExtendedImmed:
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case MachineOperand::MO_UnextendedImmed:
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@ -511,15 +511,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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unsigned int ArgCount = Desc.TSFlags & PPC32II::ArgCountMask;
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unsigned int ArgType[5];
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ArgType[0] = (Desc.TSFlags>>PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask;
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ArgType[1] = (Desc.TSFlags>>PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask;
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ArgType[2] = (Desc.TSFlags>>PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask;
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ArgType[3] = (Desc.TSFlags>>PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask;
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ArgType[4] = (Desc.TSFlags>>PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask;
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ArgType[0] = (Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask;
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ArgType[1] = (Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask;
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ArgType[2] = (Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask;
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ArgType[3] = (Desc.TSFlags >> PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask;
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ArgType[4] = (Desc.TSFlags >> PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask;
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assert((Desc.TSFlags & PPC32II::VMX == 0) &&
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assert(((Desc.TSFlags & PPC32II::VMX) == 0) &&
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"Instruction requires VMX support");
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assert((Desc.TSFlags & PPC32II::PPC64 == 0) &&
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assert(((Desc.TSFlags & PPC32II::PPC64) == 0) &&
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"Instruction requires 64 bit support");
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//assert ( ValidOpcodes(MI, ArgType) && "Instruction has invalid inputs");
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++EmittedInsts;
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@ -566,7 +566,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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printOp(MI->getOperand(2));
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O << ")\n";
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} else {
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for(i = 0; i< ArgCount; i++) {
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for (i = 0; i < ArgCount; ++i) {
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if (ArgType[i] == PPC32II::Gpr0 &&
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MI->getOperand(i).getReg() == PPC32::R0)
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O << "0";
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@ -574,7 +574,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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//std::cout << "DEBUG " << (*(TM.getRegisterInfo())).get(MI->getOperand(i).getReg()).Name << "\n";
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printOp(MI->getOperand(i));
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}
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if( ArgCount - 1 == i)
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if (ArgCount - 1 == i)
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O << "\n";
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else
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O << ", ";
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@ -426,8 +426,8 @@ void Printer::printOp(const MachineOperand &MO,
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}
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// FALLTHROUGH
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case MachineOperand::MO_MachineRegister:
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O << RI.get(MO.getReg()).Name;
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return;
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O << LowercaseString(RI.get(MO.getReg()).Name);
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return;
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case MachineOperand::MO_SignExtendedImmed:
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case MachineOperand::MO_UnextendedImmed:
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@ -511,15 +511,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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unsigned int ArgCount = Desc.TSFlags & PPC32II::ArgCountMask;
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unsigned int ArgType[5];
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ArgType[0] = (Desc.TSFlags>>PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask;
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ArgType[1] = (Desc.TSFlags>>PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask;
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ArgType[2] = (Desc.TSFlags>>PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask;
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ArgType[3] = (Desc.TSFlags>>PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask;
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ArgType[4] = (Desc.TSFlags>>PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask;
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ArgType[0] = (Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask;
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ArgType[1] = (Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask;
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ArgType[2] = (Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask;
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ArgType[3] = (Desc.TSFlags >> PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask;
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ArgType[4] = (Desc.TSFlags >> PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask;
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assert((Desc.TSFlags & PPC32II::VMX == 0) &&
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assert(((Desc.TSFlags & PPC32II::VMX) == 0) &&
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"Instruction requires VMX support");
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assert((Desc.TSFlags & PPC32II::PPC64 == 0) &&
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assert(((Desc.TSFlags & PPC32II::PPC64) == 0) &&
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"Instruction requires 64 bit support");
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//assert ( ValidOpcodes(MI, ArgType) && "Instruction has invalid inputs");
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++EmittedInsts;
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@ -566,7 +566,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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printOp(MI->getOperand(2));
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O << ")\n";
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} else {
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for(i = 0; i< ArgCount; i++) {
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for (i = 0; i < ArgCount; ++i) {
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if (ArgType[i] == PPC32II::Gpr0 &&
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MI->getOperand(i).getReg() == PPC32::R0)
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O << "0";
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@ -574,7 +574,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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//std::cout << "DEBUG " << (*(TM.getRegisterInfo())).get(MI->getOperand(i).getReg()).Name << "\n";
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printOp(MI->getOperand(i));
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}
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if( ArgCount - 1 == i)
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if (ArgCount - 1 == i)
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O << "\n";
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else
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O << ", ";
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