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[AArch64] Fix registerAllocator assigns same register for base and wback in
pre/post-index load and store. Patch by Steven Wu <stevenwu@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215390 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2998,7 +2998,7 @@ class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
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: BaseLoadStorePreIdx<sz, V, opc,
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(outs GPR64sp:$wback, regtype:$Rt),
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(ins GPR64sp:$Rn, simm9:$offset), asm,
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"$Rn = $wback", []>,
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"$Rn = $wback,@earlyclobber $wback", []>,
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Sched<[WriteLD, WriteAdr]>;
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let mayStore = 1, mayLoad = 0 in
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@ -3007,7 +3007,7 @@ class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
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: BaseLoadStorePreIdx<sz, V, opc,
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(outs GPR64sp:$wback),
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(ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
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asm, "$Rn = $wback",
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asm, "$Rn = $wback,@earlyclobber $wback",
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[(set GPR64sp:$wback,
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(storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
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Sched<[WriteAdr, WriteST]>;
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@ -3017,7 +3017,6 @@ class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
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// Load/store post-indexed
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//---
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// (pre-index) load/stores.
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class BaseLoadStorePostIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
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string asm, string cstr, list<dag> pat>
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: I<oops, iops, asm, "\t$Rt, [$Rn], $offset", cstr, pat> {
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@ -3045,7 +3044,7 @@ class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
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: BaseLoadStorePostIdx<sz, V, opc,
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(outs GPR64sp:$wback, regtype:$Rt),
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(ins GPR64sp:$Rn, simm9:$offset),
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asm, "$Rn = $wback", []>,
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asm, "$Rn = $wback,@earlyclobber $wback", []>,
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Sched<[WriteLD, WriteI]>;
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let mayStore = 1, mayLoad = 0 in
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@ -3054,7 +3053,7 @@ class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
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: BaseLoadStorePostIdx<sz, V, opc,
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(outs GPR64sp:$wback),
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(ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
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asm, "$Rn = $wback",
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asm, "$Rn = $wback,@earlyclobber $wback",
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[(set GPR64sp:$wback,
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(storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
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Sched<[WriteAdr, WriteST, ReadAdrBase]>;
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@ -3118,7 +3117,7 @@ multiclass StorePairOffset<bits<2> opc, bit V, RegisterClass regtype,
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// (pre-indexed)
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class BaseLoadStorePairPreIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
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string asm>
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: I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]!", "$Rn = $wback", []> {
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: I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]!", "$Rn = $wback,@earlyclobber $wback", []> {
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bits<5> Rt;
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bits<5> Rt2;
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bits<5> Rn;
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@ -3159,7 +3158,7 @@ class StorePairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
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class BaseLoadStorePairPostIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
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string asm>
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: I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn], $offset", "$Rn = $wback", []> {
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: I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn], $offset", "$Rn = $wback,@earlyclobber $wback", []> {
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bits<5> Rt;
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bits<5> Rt2;
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bits<5> Rn;
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@ -349,3 +349,15 @@ define i8* @preidx8sext64(i8* %src, i64* %out) {
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store i64 %ext, i64* %out, align 4
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ret i8* %ptr
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}
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; This test checks if illegal post-index is generated
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define i64* @postidx_clobber(i64* %addr) nounwind noinline ssp {
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; CHECK-LABEL: postidx_clobber:
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; CHECK-NOT: str x0, [x0], #8
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; ret
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%paddr = bitcast i64* %addr to i64**
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store i64* %addr, i64** %paddr
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%newaddr = getelementptr i64* %addr, i32 1
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ret i64* %newaddr
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}
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