6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 04:30:12 +00:00
Code Issues Projects Releases Wiki Activity

Silencing an MSVC warning about signed vs unsigned comparison mismatches.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186529 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Aaron Ballman 2013-07-17 19:43:13 +00:00
parent 27d0c68617
commit 7f6d84230c
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -781,7 +781,7 @@ SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
// all cases and are sometimes shorter. Prefer to use RISBG for ANDs though,
// since it is effectively a three-operand instruction in this case,
// and since it can handle some masks that AND IMMEDIATE can't.
if (Count < (N->getOpcode() == ISD::AND ? 1 : 2))
if (Count < (N->getOpcode() == ISD::AND ? 1U : 2U))
return 0;
// Prefer register extensions like LLC over RISBG.