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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123810 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
2011-01-19 02:26:13 +00:00
parent fc8475bde9
commit 7fa75ce11d
1 changed files with 16 additions and 16 deletions
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32
lib/Target/ARM/ARMISelLowering.cpp
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@@ -3678,7 +3678,7 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
} }
// Gather data to see if the operation can be modelled as a // Gather data to see if the operation can be modelled as a
// shuffle in combination with VEXTs. // shuffle in combination with VEXTs.
SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@@ -3688,7 +3688,7 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
SmallVector<SDValue, 2> SourceVecs; SmallVector<SDValue, 2> SourceVecs;
SmallVector<unsigned, 2> MinElts; SmallVector<unsigned, 2> MinElts;
SmallVector<unsigned, 2> MaxElts; SmallVector<unsigned, 2> MaxElts;
for (unsigned i = 0; i < NumElts; ++i) { for (unsigned i = 0; i < NumElts; ++i) {
SDValue V = Op.getOperand(i); SDValue V = Op.getOperand(i);
if (V.getOpcode() == ISD::UNDEF) if (V.getOpcode() == ISD::UNDEF)
@@ -3698,7 +3698,7 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
// elements of other vectors. // elements of other vectors.
return SDValue(); return SDValue();
} }
// Record this extraction against the appropriate vector if possible... // Record this extraction against the appropriate vector if possible...
SDValue SourceVec = V.getOperand(0); SDValue SourceVec = V.getOperand(0);
unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue(); unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
@@ -3713,7 +3713,7 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
break; break;
} }
} }
// Or record a new source if not... // Or record a new source if not...
if (!FoundSource) { if (!FoundSource) {
SourceVecs.push_back(SourceVec); SourceVecs.push_back(SourceVec);
@@ -3721,7 +3721,7 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
MaxElts.push_back(EltNo); MaxElts.push_back(EltNo);
} }
} }
// Currently only do something sane when at most two source vectors // Currently only do something sane when at most two source vectors
// involved. // involved.
if (SourceVecs.size() > 2) if (SourceVecs.size() > 2)
@@ -3729,7 +3729,7 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) }; SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
int VEXTOffsets[2] = {0, 0}; int VEXTOffsets[2] = {0, 0};
// This loop extracts the usage patterns of the source vectors // This loop extracts the usage patterns of the source vectors
// and prepares appropriate SDValues for a shuffle if possible. // and prepares appropriate SDValues for a shuffle if possible.
for (unsigned i = 0; i < SourceVecs.size(); ++i) { for (unsigned i = 0; i < SourceVecs.size(); ++i) {
@@ -3743,17 +3743,17 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
// break it down again in a shuffle. // break it down again in a shuffle.
return SDValue(); return SDValue();
} }
// Since only 64-bit and 128-bit vectors are legal on ARM and // Since only 64-bit and 128-bit vectors are legal on ARM and
// we've eliminated the other cases... // we've eliminated the other cases...
assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts && assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
"unexpected vector sizes in ReconstructShuffle"); "unexpected vector sizes in ReconstructShuffle");
if (MaxElts[i] - MinElts[i] >= NumElts) { if (MaxElts[i] - MinElts[i] >= NumElts) {
// Span too large for a VEXT to cope // Span too large for a VEXT to cope
return SDValue(); return SDValue();
} }
if (MinElts[i] >= NumElts) { if (MinElts[i] >= NumElts) {
// The extraction can just take the second half // The extraction can just take the second half
VEXTOffsets[i] = NumElts; VEXTOffsets[i] = NumElts;
@@ -3779,16 +3779,16 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
DAG.getConstant(VEXTOffsets[i], MVT::i32)); DAG.getConstant(VEXTOffsets[i], MVT::i32));
} }
} }
SmallVector<int, 8> Mask; SmallVector<int, 8> Mask;
for (unsigned i = 0; i < NumElts; ++i) { for (unsigned i = 0; i < NumElts; ++i) {
SDValue Entry = Op.getOperand(i); SDValue Entry = Op.getOperand(i);
if (Entry.getOpcode() == ISD::UNDEF) { if (Entry.getOpcode() == ISD::UNDEF) {
Mask.push_back(-1); Mask.push_back(-1);
continue; continue;
} }
SDValue ExtractVec = Entry.getOperand(0); SDValue ExtractVec = Entry.getOperand(0);
int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i) int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
.getOperand(1))->getSExtValue(); .getOperand(1))->getSExtValue();
@@ -3798,12 +3798,12 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]); Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
} }
} }
// Final check before we try to produce nonsense... // Final check before we try to produce nonsense...
if (isShuffleMaskLegal(Mask, VT)) if (isShuffleMaskLegal(Mask, VT))
return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1], return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
&Mask[0]); &Mask[0]);
return SDValue(); return SDValue();
} }
@@ -4603,7 +4603,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
case ARM::BCCZi64: { case ARM::BCCZi64: {
// If there is an unconditional branch to the other successor, remove it. // If there is an unconditional branch to the other successor, remove it.
BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
// Compare both parts that make up the double comparison separately for // Compare both parts that make up the double comparison separately for
// equality. // equality.
bool RHSisZero = MI->getOpcode() == ARM::BCCZi64; bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;