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R600/SI: add constant for inline zero operand

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Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175747 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christian Konig 2013-02-21 15:16:49 +00:00
parent 8c0b3a0d31
commit 7fa9957b16
1 changed files with 3 additions and 4 deletions
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7
lib/Target/R600/SIInstrInfo.td
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@ -49,9 +49,8 @@ class InlineImm <ValueType vt> : ImmLeaf <vt, [{
// SI assembler operands // SI assembler operands
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class SIOperand <ValueType vt, dag opInfo>: Operand <vt> { def SIOperand {
let EncoderMethod = "encodeOperand"; int ZERO = 0x80;
let MIOperandInfo = opInfo;
} }
class GPR4Align <RegisterClass rc> : Operand <vAny> { class GPR4Align <RegisterClass rc> : Operand <vAny> {
@ -201,7 +200,7 @@ multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
InstFlag:$omod, InstFlag:$neg), InstFlag:$omod, InstFlag:$neg),
opName, pattern opName, pattern
> { > {
let SRC2 = 0x80; let SRC2 = SIOperand.ZERO;
} }
} }