6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 20:32:21 +00:00
Code Issues Projects Releases Wiki Activity

Fixes to the X86 disassembler:

Browse Source 
Made LEA memory operands emit only 4 MCInst operands.
Made the scale operand equal 1 for instructions that have no
SIB byte.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91919 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sean Callanan 2009-12-22 21:12:55 +00:00
parent 4935a02101
commit 7fb35a2fd8
3 changed files with 20 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
lib/Target/X86/Disassembler/X86Disassembler.cpp
View File

@ -183,8 +183,12 @@ static void translateRMRegister(MCInst &mcInst,
/// @param mcInst - The MCInst to append to.
/// @param insn - The instruction to extract Mod, R/M, and SIB fields
/// from.
/// @param sr - Whether or not to emit the segment register. The
/// LEA instruction does not expect a segment-register
/// operand.
static void translateRMMemory(MCInst &mcInst,
InternalInstruction &insn) {
InternalInstruction &insn,
bool sr) {
// Addresses in an MCInst are represented as five operands:
// 1. basereg (register) The R/M base, or (if there is a SIB) the
// SIB base
@ -209,7 +213,7 @@ static void translateRMMemory(MCInst &mcInst,
default:
llvm_unreachable("Unexpected sibBase");
#define ENTRY(x) \
case SIB_BASE_##x: \
case SIB_BASE_##x: \
baseReg = MCOperand::CreateReg(X86::x); break;
ALL_SIB_BASES
#undef ENTRY
@ -222,7 +226,7 @@ static void translateRMMemory(MCInst &mcInst,
switch (insn.sibIndex) {
default:
llvm_unreachable("Unexpected sibIndex");
#define ENTRY(x) \
#define ENTRY(x) \
case SIB_INDEX_##x: \
indexReg = MCOperand::CreateReg(X86::x); break;
EA_BASES_32BIT
@ -286,6 +290,8 @@ static void translateRMMemory(MCInst &mcInst,
break;
}
}
scaleAmount = MCOperand::CreateImm(1);
}
displacement = MCOperand::CreateImm(insn.displacement);
@ -306,7 +312,9 @@ static void translateRMMemory(MCInst &mcInst,
mcInst.addOperand(scaleAmount);
mcInst.addOperand(indexReg);
mcInst.addOperand(displacement);
mcInst.addOperand(segmentReg);
if (sr)
mcInst.addOperand(segmentReg);
}
/// translateRM - Translates an operand stored in the R/M (and possibly SIB)
@ -356,7 +364,10 @@ static void translateRM(MCInst &mcInst,
case TYPE_M1616:
case TYPE_M1632:
case TYPE_M1664:
translateRMMemory(mcInst, insn);
translateRMMemory(mcInst, insn, true);
break;
case TYPE_LEA:
translateRMMemory(mcInst, insn, false);
break;
}
}

1
lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
View File

@ -245,6 +245,7 @@ struct ContextDecision {
ENUM_ENTRY(TYPE_M16, "2-byte") \
ENUM_ENTRY(TYPE_M32, "4-byte") \
ENUM_ENTRY(TYPE_M64, "8-byte") \
ENUM_ENTRY(TYPE_LEA, "Effective address") \
ENUM_ENTRY(TYPE_M128, "16-byte (SSE/SSE2)") \
ENUM_ENTRY(TYPE_M1616, "2+2-byte segment+offset address") \
ENUM_ENTRY(TYPE_M1632, "2+4-byte") \

6
utils/TableGen/X86RecognizableInstr.cpp
View File

@ -817,9 +817,9 @@ OperandType RecognizableInstr::typeFromString(const std::string &s,
TYPE("brtarget", TYPE_RELv)
TYPE("brtarget8", TYPE_REL8)
TYPE("f80mem", TYPE_M80FP)
TYPE("lea32mem", TYPE_M32)
TYPE("lea64_32mem", TYPE_M64)
TYPE("lea64mem", TYPE_M64)
TYPE("lea32mem", TYPE_LEA)
TYPE("lea64_32mem", TYPE_LEA)
TYPE("lea64mem", TYPE_LEA)
TYPE("VR64", TYPE_MM64)
TYPE("i64imm", TYPE_IMMv)
TYPE("opaque32mem", TYPE_M1616)