From 7fbcef7102732769e2dab1d37f68166b2868c963 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Fri, 24 Mar 2006 07:53:47 +0000 Subject: [PATCH] Disable the i32->float G5 optimization. It is unsafe, as documented in the comment. This fixes 177.mesa, and McCat/09-vor with the td scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27060 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCISelLowering.cpp | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index f228cc22b01..09494a596cc 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -140,7 +140,12 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) // They also have instructions for converting between i64 and fp. setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); - setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); + + // FIXME: disable this lowered code. This generates 64-bit register values, + // and we don't model the fact that the top part is clobbered by calls. We + // need to flag these together so that the value isn't live across a call. + //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); + // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); } else { @@ -359,6 +364,7 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); return FP; } + break; case ISD::SELECT_CC: { // Turn FP only select_cc's into fsel instructions.