From 7fed65a68d961eef21d4572beab64d047ece5a3e Mon Sep 17 00:00:00 2001 From: Duncan Sands Date: Mon, 17 Nov 2008 20:52:38 +0000 Subject: [PATCH] Add soft float support for a bunch more operations. Original patch by Richard Osborne, tweaked and extended by your humble servant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59464 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../SelectionDAG/LegalizeFloatTypes.cpp | 178 +++++++++++++++++- lib/CodeGen/SelectionDAG/LegalizeTypes.h | 14 ++ test/CodeGen/XCore/cos.ll | 16 ++ test/CodeGen/XCore/exp.ll | 16 ++ test/CodeGen/XCore/exp2.ll | 16 ++ test/CodeGen/XCore/fneg.ll | 8 + test/CodeGen/XCore/log.ll | 16 ++ test/CodeGen/XCore/log10.ll | 16 ++ test/CodeGen/XCore/log2.ll | 16 ++ test/CodeGen/XCore/pow.ll | 16 ++ test/CodeGen/XCore/powi.ll | 16 ++ test/CodeGen/XCore/sin.ll | 16 ++ test/CodeGen/XCore/sqrt.ll | 16 ++ 13 files changed, 356 insertions(+), 4 deletions(-) create mode 100644 test/CodeGen/XCore/cos.ll create mode 100644 test/CodeGen/XCore/exp.ll create mode 100644 test/CodeGen/XCore/exp2.ll create mode 100644 test/CodeGen/XCore/fneg.ll create mode 100644 test/CodeGen/XCore/log.ll create mode 100644 test/CodeGen/XCore/log10.ll create mode 100644 test/CodeGen/XCore/log2.ll create mode 100644 test/CodeGen/XCore/pow.ll create mode 100644 test/CodeGen/XCore/powi.ll create mode 100644 test/CodeGen/XCore/sin.ll create mode 100644 test/CodeGen/XCore/sqrt.ll diff --git a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index 9084e582da0..591f81697df 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -61,14 +61,28 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) { break; case ISD::FABS: R = SoftenFloatRes_FABS(N); break; case ISD::FADD: R = SoftenFloatRes_FADD(N); break; + case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break; case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N); break; + case ISD::FCOS: R = SoftenFloatRes_FCOS(N); break; case ISD::FDIV: R = SoftenFloatRes_FDIV(N); break; + case ISD::FEXP: R = SoftenFloatRes_FEXP(N); break; + case ISD::FEXP2: R = SoftenFloatRes_FEXP2(N); break; + case ISD::FFLOOR: R = SoftenFloatRes_FFLOOR(N); break; + case ISD::FLOG: R = SoftenFloatRes_FLOG(N); break; + case ISD::FLOG2: R = SoftenFloatRes_FLOG2(N); break; + case ISD::FLOG10: R = SoftenFloatRes_FLOG10(N); break; case ISD::FMUL: R = SoftenFloatRes_FMUL(N); break; + case ISD::FNEARBYINT: R = SoftenFloatRes_FNEARBYINT(N); break; + case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break; case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break; case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break; case ISD::FPOW: R = SoftenFloatRes_FPOW(N); break; case ISD::FPOWI: R = SoftenFloatRes_FPOWI(N); break; + case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break; + case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; + case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break; + case ISD::FTRUNC: R = SoftenFloatRes_FTRUNC(N); break; case ISD::LOAD: R = SoftenFloatRes_LOAD(N); break; case ISD::SELECT: R = SoftenFloatRes_SELECT(N); break; case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N); break; @@ -103,7 +117,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N) { unsigned Size = NVT.getSizeInBits(); // Mask = ~(1 << (Size-1)) - SDValue Mask = DAG.getConstant(APInt::getAllOnesValue(Size).clear(Size-1), + SDValue Mask = DAG.getConstant(APInt::getAllOnesValue(Size).clear(Size-1), NVT); SDValue Op = GetSoftenedFloat(N->getOperand(0)); return DAG.getNode(ISD::AND, NVT, Op, Mask); @@ -121,6 +135,17 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) { NVT, Ops, 2, false); } +SDValue DAGTypeLegalizer::SoftenFloatRes_FCEIL(SDNode *N) { + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + SDValue Op = GetSoftenedFloat(N->getOperand(0)); + return MakeLibCall(GetFPLibCall(N->getValueType(0), + RTLIB::CEIL_F32, + RTLIB::CEIL_F64, + RTLIB::CEIL_F80, + RTLIB::CEIL_PPCF128), + NVT, &Op, 1, false); +} + SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) { SDValue LHS = GetSoftenedFloat(N->getOperand(0)); SDValue RHS = BitConvertToInteger(N->getOperand(1)); @@ -160,6 +185,17 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) { return DAG.getNode(ISD::OR, LVT, LHS, SignBit); } +SDValue DAGTypeLegalizer::SoftenFloatRes_FCOS(SDNode *N) { + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + SDValue Op = GetSoftenedFloat(N->getOperand(0)); + return MakeLibCall(GetFPLibCall(N->getValueType(0), + RTLIB::COS_F32, + RTLIB::COS_F64, + RTLIB::COS_F80, + RTLIB::COS_PPCF128), + NVT, &Op, 1, false); +} + SDValue DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) { MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), @@ -172,6 +208,72 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) { NVT, Ops, 2, false); } +SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP(SDNode *N) { + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + SDValue Op = GetSoftenedFloat(N->getOperand(0)); + return MakeLibCall(GetFPLibCall(N->getValueType(0), + RTLIB::EXP_F32, + RTLIB::EXP_F64, + RTLIB::EXP_F80, + RTLIB::EXP_PPCF128), + NVT, &Op, 1, false); +} + +SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP2(SDNode *N) { + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + SDValue Op = GetSoftenedFloat(N->getOperand(0)); + return MakeLibCall(GetFPLibCall(N->getValueType(0), + RTLIB::EXP2_F32, + RTLIB::EXP2_F64, + RTLIB::EXP2_F80, + RTLIB::EXP2_PPCF128), + NVT, &Op, 1, false); +} + +SDValue DAGTypeLegalizer::SoftenFloatRes_FFLOOR(SDNode *N) { + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + SDValue Op = GetSoftenedFloat(N->getOperand(0)); + return MakeLibCall(GetFPLibCall(N->getValueType(0), + RTLIB::FLOOR_F32, + RTLIB::FLOOR_F64, + RTLIB::FLOOR_F80, + RTLIB::FLOOR_PPCF128), + NVT, &Op, 1, false); +} + +SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG(SDNode *N) { + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + SDValue Op = GetSoftenedFloat(N->getOperand(0)); + return MakeLibCall(GetFPLibCall(N->getValueType(0), + RTLIB::LOG_F32, + RTLIB::LOG_F64, + RTLIB::LOG_F80, + RTLIB::LOG_PPCF128), + NVT, &Op, 1, false); +} + +SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG2(SDNode *N) { + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + SDValue Op = GetSoftenedFloat(N->getOperand(0)); + return MakeLibCall(GetFPLibCall(N->getValueType(0), + RTLIB::LOG2_F32, + RTLIB::LOG2_F64, + RTLIB::LOG2_F80, + RTLIB::LOG2_PPCF128), + NVT, &Op, 1, false); +} + +SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG10(SDNode *N) { + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + SDValue Op = GetSoftenedFloat(N->getOperand(0)); + return MakeLibCall(GetFPLibCall(N->getValueType(0), + RTLIB::LOG10_F32, + RTLIB::LOG10_F64, + RTLIB::LOG10_F80, + RTLIB::LOG10_PPCF128), + NVT, &Op, 1, false); +} + SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) { MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), @@ -184,6 +286,30 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) { NVT, Ops, 2, false); } +SDValue DAGTypeLegalizer::SoftenFloatRes_FNEARBYINT(SDNode *N) { + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + SDValue Op = GetSoftenedFloat(N->getOperand(0)); + return MakeLibCall(GetFPLibCall(N->getValueType(0), + RTLIB::NEARBYINT_F32, + RTLIB::NEARBYINT_F64, + RTLIB::NEARBYINT_F80, + RTLIB::NEARBYINT_PPCF128), + NVT, &Op, 1, false); +} + +SDValue DAGTypeLegalizer::SoftenFloatRes_FNEG(SDNode *N) { + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + // Expand Y = FNEG(X) -> Y = SUB -0.0, X + SDValue Ops[2] = { DAG.getConstantFP(-0.0, NVT), + GetSoftenedFloat(N->getOperand(0)) }; + return MakeLibCall(GetFPLibCall(N->getValueType(0), + RTLIB::SUB_F32, + RTLIB::SUB_F64, + RTLIB::SUB_F80, + RTLIB::SUB_PPCF128), + NVT, Ops, 2, false); +} + SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) { MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = N->getOperand(0); @@ -225,6 +351,39 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) { NVT, Ops, 2, false); } +SDValue DAGTypeLegalizer::SoftenFloatRes_FRINT(SDNode *N) { + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + SDValue Op = GetSoftenedFloat(N->getOperand(0)); + return MakeLibCall(GetFPLibCall(N->getValueType(0), + RTLIB::RINT_F32, + RTLIB::RINT_F64, + RTLIB::RINT_F80, + RTLIB::RINT_PPCF128), + NVT, &Op, 1, false); +} + +SDValue DAGTypeLegalizer::SoftenFloatRes_FSIN(SDNode *N) { + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + SDValue Op = GetSoftenedFloat(N->getOperand(0)); + return MakeLibCall(GetFPLibCall(N->getValueType(0), + RTLIB::SIN_F32, + RTLIB::SIN_F64, + RTLIB::SIN_F80, + RTLIB::SIN_PPCF128), + NVT, &Op, 1, false); +} + +SDValue DAGTypeLegalizer::SoftenFloatRes_FSQRT(SDNode *N) { + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + SDValue Op = GetSoftenedFloat(N->getOperand(0)); + return MakeLibCall(GetFPLibCall(N->getValueType(0), + RTLIB::SQRT_F32, + RTLIB::SQRT_F64, + RTLIB::SQRT_F80, + RTLIB::SQRT_PPCF128), + NVT, &Op, 1, false); +} + SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) { MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), @@ -237,6 +396,17 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) { NVT, Ops, 2, false); } +SDValue DAGTypeLegalizer::SoftenFloatRes_FTRUNC(SDNode *N) { + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + SDValue Op = GetSoftenedFloat(N->getOperand(0)); + return MakeLibCall(GetFPLibCall(N->getValueType(0), + RTLIB::TRUNC_F32, + RTLIB::TRUNC_F64, + RTLIB::TRUNC_F80, + RTLIB::TRUNC_PPCF128), + NVT, &Op, 1, false); +} + SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) { LoadSDNode *L = cast(N); MVT VT = N->getValueType(0); @@ -607,7 +777,7 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) { case ISD::FPOW: ExpandFloatRes_FPOW(N, Lo, Hi); break; case ISD::FPOWI: ExpandFloatRes_FPOWI(N, Lo, Hi); break; case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break; - case ISD::FSIN: ExpandFloatRes_FABS(N, Lo, Hi); break; + case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break; case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break; case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break; case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi); break; @@ -926,14 +1096,14 @@ void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, // though. if (SrcVT.bitsLE(MVT::i32)) { // The integer can be represented exactly in an f64. - Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, + Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, MVT::i32, Src); Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT); Hi = DAG.getNode(ISD::SINT_TO_FP, NVT, Src); } else { RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; if (SrcVT.bitsLE(MVT::i64)) { - Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, + Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, MVT::i64, Src); LC = RTLIB::SINTTOFP_I64_PPCF128; } else if (SrcVT.bitsLE(MVT::i128)) { diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h index a96fbe187c6..703c68686c1 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -351,14 +351,28 @@ private: SDValue SoftenFloatRes_ConstantFP(ConstantFPSDNode *N); SDValue SoftenFloatRes_FABS(SDNode *N); SDValue SoftenFloatRes_FADD(SDNode *N); + SDValue SoftenFloatRes_FCEIL(SDNode *N); SDValue SoftenFloatRes_FCOPYSIGN(SDNode *N); + SDValue SoftenFloatRes_FCOS(SDNode *N); SDValue SoftenFloatRes_FDIV(SDNode *N); + SDValue SoftenFloatRes_FEXP(SDNode *N); + SDValue SoftenFloatRes_FEXP2(SDNode *N); + SDValue SoftenFloatRes_FFLOOR(SDNode *N); + SDValue SoftenFloatRes_FLOG(SDNode *N); + SDValue SoftenFloatRes_FLOG2(SDNode *N); + SDValue SoftenFloatRes_FLOG10(SDNode *N); SDValue SoftenFloatRes_FMUL(SDNode *N); + SDValue SoftenFloatRes_FNEARBYINT(SDNode *N); + SDValue SoftenFloatRes_FNEG(SDNode *N); SDValue SoftenFloatRes_FP_EXTEND(SDNode *N); SDValue SoftenFloatRes_FP_ROUND(SDNode *N); SDValue SoftenFloatRes_FPOW(SDNode *N); SDValue SoftenFloatRes_FPOWI(SDNode *N); + SDValue SoftenFloatRes_FRINT(SDNode *N); + SDValue SoftenFloatRes_FSIN(SDNode *N); + SDValue SoftenFloatRes_FSQRT(SDNode *N); SDValue SoftenFloatRes_FSUB(SDNode *N); + SDValue SoftenFloatRes_FTRUNC(SDNode *N); SDValue SoftenFloatRes_LOAD(SDNode *N); SDValue SoftenFloatRes_SELECT(SDNode *N); SDValue SoftenFloatRes_SELECT_CC(SDNode *N); diff --git a/test/CodeGen/XCore/cos.ll b/test/CodeGen/XCore/cos.ll new file mode 100644 index 00000000000..334f0d50561 --- /dev/null +++ b/test/CodeGen/XCore/cos.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=xcore > %t1.s +; RUN: grep "bl cosf" %t1.s | count 1 +; RUN: grep "bl cos" %t1.s | count 2 +declare double @llvm.cos.f64(double) + +define double @test(double %F) { + %result = call double @llvm.cos.f64(double %F) + ret double %result +} + +declare float @llvm.cos.f32(float) + +define float @testf(float %F) { + %result = call float @llvm.cos.f32(float %F) + ret float %result +} diff --git a/test/CodeGen/XCore/exp.ll b/test/CodeGen/XCore/exp.ll new file mode 100644 index 00000000000..8412e7a5995 --- /dev/null +++ b/test/CodeGen/XCore/exp.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=xcore > %t1.s +; RUN: grep "bl expf" %t1.s | count 1 +; RUN: grep "bl exp" %t1.s | count 2 +declare double @llvm.exp.f64(double) + +define double @test(double %F) { + %result = call double @llvm.exp.f64(double %F) + ret double %result +} + +declare float @llvm.exp.f32(float) + +define float @testf(float %F) { + %result = call float @llvm.exp.f32(float %F) + ret float %result +} diff --git a/test/CodeGen/XCore/exp2.ll b/test/CodeGen/XCore/exp2.ll new file mode 100644 index 00000000000..a53b767ad0d --- /dev/null +++ b/test/CodeGen/XCore/exp2.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=xcore > %t1.s +; RUN: grep "bl exp2f" %t1.s | count 1 +; RUN: grep "bl exp2" %t1.s | count 2 +declare double @llvm.exp2.f64(double) + +define double @test(double %F) { + %result = call double @llvm.exp2.f64(double %F) + ret double %result +} + +declare float @llvm.exp2.f32(float) + +define float @testf(float %F) { + %result = call float @llvm.exp2.f32(float %F) + ret float %result +} diff --git a/test/CodeGen/XCore/fneg.ll b/test/CodeGen/XCore/fneg.ll new file mode 100644 index 00000000000..ac30410cf89 --- /dev/null +++ b/test/CodeGen/XCore/fneg.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=xcore > %t1.s +; RUN: grep "bl __subdf3" %t1.s | count 1 +define i1 @test(double %F) nounwind { +entry: + %0 = sub double -0.000000e+00, %F + %1 = fcmp olt double 0.000000e+00, %0 + ret i1 %1 +} diff --git a/test/CodeGen/XCore/log.ll b/test/CodeGen/XCore/log.ll new file mode 100644 index 00000000000..88d9d7ffcd3 --- /dev/null +++ b/test/CodeGen/XCore/log.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=xcore > %t1.s +; RUN: grep "bl logf" %t1.s | count 1 +; RUN: grep "bl log" %t1.s | count 2 +declare double @llvm.log.f64(double) + +define double @test(double %F) { + %result = call double @llvm.log.f64(double %F) + ret double %result +} + +declare float @llvm.log.f32(float) + +define float @testf(float %F) { + %result = call float @llvm.log.f32(float %F) + ret float %result +} diff --git a/test/CodeGen/XCore/log10.ll b/test/CodeGen/XCore/log10.ll new file mode 100644 index 00000000000..f844d8fc6a2 --- /dev/null +++ b/test/CodeGen/XCore/log10.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=xcore > %t1.s +; RUN: grep "bl log10f" %t1.s | count 1 +; RUN: grep "bl log10" %t1.s | count 2 +declare double @llvm.log10.f64(double) + +define double @test(double %F) { + %result = call double @llvm.log10.f64(double %F) + ret double %result +} + +declare float @llvm.log10.f32(float) + +define float @testf(float %F) { + %result = call float @llvm.log10.f32(float %F) + ret float %result +} diff --git a/test/CodeGen/XCore/log2.ll b/test/CodeGen/XCore/log2.ll new file mode 100644 index 00000000000..b8a3dbd2317 --- /dev/null +++ b/test/CodeGen/XCore/log2.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=xcore > %t1.s +; RUN: grep "bl log2f" %t1.s | count 1 +; RUN: grep "bl log2" %t1.s | count 2 +declare double @llvm.log2.f64(double) + +define double @test(double %F) { + %result = call double @llvm.log2.f64(double %F) + ret double %result +} + +declare float @llvm.log2.f32(float) + +define float @testf(float %F) { + %result = call float @llvm.log2.f32(float %F) + ret float %result +} diff --git a/test/CodeGen/XCore/pow.ll b/test/CodeGen/XCore/pow.ll new file mode 100644 index 00000000000..a7b6318c109 --- /dev/null +++ b/test/CodeGen/XCore/pow.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=xcore > %t1.s +; RUN: grep "bl powf" %t1.s | count 1 +; RUN: grep "bl pow" %t1.s | count 2 +declare double @llvm.pow.f64(double, double) + +define double @test(double %F, double %power) { + %result = call double @llvm.pow.f64(double %F, double %power) + ret double %result +} + +declare float @llvm.pow.f32(float, float) + +define float @testf(float %F, float %power) { + %result = call float @llvm.pow.f32(float %F, float %power) + ret float %result +} diff --git a/test/CodeGen/XCore/powi.ll b/test/CodeGen/XCore/powi.ll new file mode 100644 index 00000000000..30e6d7ea88f --- /dev/null +++ b/test/CodeGen/XCore/powi.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=xcore > %t1.s +; RUN: grep "bl __powidf2" %t1.s | count 1 +; RUN: grep "bl __powisf2" %t1.s | count 1 +declare double @llvm.powi.f64(double, i32) + +define double @test(double %F, i32 %power) { + %result = call double @llvm.powi.f64(double %F, i32 %power) + ret double %result +} + +declare float @llvm.powi.f32(float, i32) + +define float @testf(float %F, i32 %power) { + %result = call float @llvm.powi.f32(float %F, i32 %power) + ret float %result +} diff --git a/test/CodeGen/XCore/sin.ll b/test/CodeGen/XCore/sin.ll new file mode 100644 index 00000000000..41aab675953 --- /dev/null +++ b/test/CodeGen/XCore/sin.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=xcore > %t1.s +; RUN: grep "bl sinf" %t1.s | count 1 +; RUN: grep "bl sin" %t1.s | count 2 +declare double @llvm.sin.f64(double) + +define double @test(double %F) { + %result = call double @llvm.sin.f64(double %F) + ret double %result +} + +declare float @llvm.sin.f32(float) + +define float @testf(float %F) { + %result = call float @llvm.sin.f32(float %F) + ret float %result +} diff --git a/test/CodeGen/XCore/sqrt.ll b/test/CodeGen/XCore/sqrt.ll new file mode 100644 index 00000000000..221d1ac1a78 --- /dev/null +++ b/test/CodeGen/XCore/sqrt.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=xcore > %t1.s +; RUN: grep "bl sqrtf" %t1.s | count 1 +; RUN: grep "bl sqrt" %t1.s | count 2 +declare double @llvm.sqrt.f64(double) + +define double @test(double %F) { + %result = call double @llvm.sqrt.f64(double %F) + ret double %result +} + +declare float @llvm.sqrt.f32(float) + +define float @testf(float %F) { + %result = call float @llvm.sqrt.f32(float %F) + ret float %result +}