diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp index 6b722fa7ec3..ca3a0512ce0 100644 --- a/lib/CodeGen/LiveVariables.cpp +++ b/lib/CodeGen/LiveVariables.cpp @@ -218,7 +218,8 @@ bool LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI, // If not found, this means an alias of one of the operand is killed. Add a // new implicit operand if required. if (!Found && AddIfNotFound) { - MI->addRegOperand(IncomingReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/); + MI->addOperand(MachineOperand::CreateReg(IncomingReg, false/*IsDef*/, + true/*IsImp*/,true/*IsKill*/)); return true; } return Found; @@ -250,8 +251,9 @@ bool LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI, // If not found, this means an alias of one of the operand is dead. Add a // new implicit operand. if (!Found && AddIfNotFound) { - MI->addRegOperand(IncomingReg, true/*IsDef*/,true/*IsImp*/,false/*IsKill*/, - true/*IsDead*/); + MI->addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/, + true/*IsImp*/,false/*IsKill*/, + true/*IsDead*/)); return true; } return Found; @@ -263,8 +265,9 @@ void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { MachineInstr *Def = PhysRegPartDef[Reg][i]; // First one is just a def. This means the use is reading some undef bits. if (i != 0) - Def->addRegOperand(Reg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/); - Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/); + Def->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, + true/*IsImp*/,true/*IsKill*/)); + Def->addOperand(MachineOperand::CreateReg(Reg,true/*IsDef*/,true/*IsImp*/)); } PhysRegPartDef[Reg].clear(); @@ -276,7 +279,8 @@ void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { !PhysRegUsed[Reg]) { MachineInstr *Def = PhysRegInfo[Reg]; if (!Def->findRegisterDefOperand(Reg)) - Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/); + Def->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, + true/*IsImp*/)); } // There is a now a proper use, forget about the last partial use. @@ -397,8 +401,10 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) { // being re-defined. Treat it as read/mod/write. // EAX = // AX = EAX, EAX - MI->addRegOperand(SuperReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/); - MI->addRegOperand(SuperReg, true/*IsDef*/,true/*IsImp*/); + MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/, + true/*IsImp*/,true/*IsKill*/)); + MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/, + true/*IsImp*/)); PhysRegInfo[SuperReg] = MI; PhysRegUsed[SuperReg] = false; PhysRegPartUse[SuperReg] = NULL; @@ -538,7 +544,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { HandlePhysRegUse(*I, Ret); // Add live-out registers as implicit uses. if (Ret->findRegisterUseOperandIdx(*I) == -1) - Ret->addRegOperand(*I, false, true); + Ret->addOperand(MachineOperand::CreateReg(*I, false, true)); } } diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index 1655cbabf28..5950c7c09a4 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -32,10 +32,10 @@ MachineInstr::MachineInstr() void MachineInstr::addImplicitDefUseOperands() { if (TID->ImplicitDefs) for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) - addRegOperand(*ImpDefs, true, true); + addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); if (TID->ImplicitUses) for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) - addRegOperand(*ImpUses, false, true); + addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); } /// MachineInstr ctor - This constructor create a MachineInstr and add the @@ -249,13 +249,8 @@ void MachineInstr::copyPredicates(const MachineInstr *MI) { if (TID->Flags & M_PREDICABLE) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) { - const MachineOperand &MO = MI->getOperand(i); // Predicated operands must be last operands. - if (MO.isRegister()) - addRegOperand(MO.getReg(), false); - else { - addImmOperand(MO.getImm()); - } + addOperand(MI->getOperand(i)); } } } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 532efd609ec..2a1bd79923f 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -379,7 +379,7 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, unsigned Reg = cast(Use->getOperand(1))->getReg(); if (MRegisterInfo::isVirtualRegister(Reg)) { VRBase = Reg; - MI->addRegOperand(Reg, true); + MI->addOperand(MachineOperand::CreateReg(Reg, true)); break; } } @@ -391,7 +391,7 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i); assert(RC && "Isn't a register operand!"); VRBase = RegMap->createVirtualRegister(RC); - MI->addRegOperand(VRBase, true); + MI->addOperand(MachineOperand::CreateReg(VRBase, true)); } bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,i), VRBase)); @@ -429,7 +429,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); bool isOptDef = (IIOpNum < TID->numOperands) ? (TID->OpInfo[IIOpNum].Flags & M_OPTIONAL_DEF_OPERAND) : false; - MI->addRegOperand(VReg, isOptDef); + MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef)); // Verify that it is right. assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); @@ -456,10 +456,10 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, } } else if (ConstantSDNode *C = dyn_cast(Op)) { - MI->addImmOperand(C->getValue()); + MI->addOperand(MachineOperand::CreateImm(C->getValue())); } else if (RegisterSDNode *R = dyn_cast(Op)) { - MI->addRegOperand(R->getReg(), false); + MI->addOperand(MachineOperand::CreateReg(R->getReg(), false)); } else if (GlobalAddressSDNode *TGA = dyn_cast(Op)) { MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset()); @@ -501,7 +501,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, Op.getValueType() != MVT::Flag && "Chain and flag operands should occur at end of operand list!"); unsigned VReg = getVR(Op, VRBaseMap); - MI->addRegOperand(VReg, false); + MI->addOperand(MachineOperand::CreateReg(VReg, false)); // Verify that it is right. assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); @@ -588,7 +588,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node, } // Add def, source, and subreg index - MI->addRegOperand(VRBase, true); + MI->addOperand(MachineOperand::CreateReg(VRBase, true)); AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); MI->addImmOperand(SubIdx); @@ -643,7 +643,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node, VRBase = RegMap->createVirtualRegister(TRC); // Create the reg } - MI->addRegOperand(VRBase, true); + MI->addOperand(MachineOperand::CreateReg(VRBase, true)); AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); if (!isUndefInput) AddOperand(MI, Node->getOperand(1), 0, 0, VRBaseMap); @@ -789,20 +789,20 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, case 1: // Use of register. for (; NumVals; --NumVals, ++i) { unsigned Reg = cast(Node->getOperand(i))->getReg(); - MI->addRegOperand(Reg, false); + MI->addOperand(MachineOperand::CreateReg(Reg, false)); } break; case 2: // Def of register. for (; NumVals; --NumVals, ++i) { unsigned Reg = cast(Node->getOperand(i))->getReg(); - MI->addRegOperand(Reg, true); + MI->addOperand(MachineOperand::CreateReg(Reg, true)); } break; case 3: { // Immediate. for (; NumVals; --NumVals, ++i) { if (ConstantSDNode *CS = dyn_cast(Node->getOperand(i))) { - MI->addImmOperand(CS->getValue()); + MI->addOperand(MachineOperand::CreateImm(CS->getValue())); } else if (GlobalAddressSDNode *GA = dyn_cast(Node->getOperand(i))) { MI->addGlobalAddressOperand(GA->getGlobal(), GA->getOffset());