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Add option to disable scheduling.

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Destroy live-variable information after scheduling so it is
recomputed before later phases (e.g., reg. allocation).
Use deterministic iterator to enumerate sched graphs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1972 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve 2002-03-24 03:44:55 +00:00
parent cf8a98f2c2
commit 802cec485f
2 changed files with 116 additions and 88 deletions
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48
lib/CodeGen/InstrSched/InstrScheduling.cpp
View File

@ -31,6 +31,7 @@ using std::vector;
cl::Enum<enum SchedDebugLevel_t> SchedDebugLevel("dsched", cl::NoFlags,
"enable instruction scheduling debugging information",
clEnumValN(Sched_NoDebugInfo, "n", "disable debug output"),
clEnumValN(Sched_Disable, "off", "disable instruction scheduling"),
clEnumValN(Sched_PrintMachineCode, "y", "print machine code after scheduling"),
clEnumValN(Sched_PrintSchedTrace, "t", "print trace of scheduling actions"),
clEnumValN(Sched_PrintSchedGraphs, "g", "print scheduling graphs"), 0);
@ -1491,30 +1492,41 @@ instrIsFeasible(const SchedulingManager& S,
namespace {
class InstructionSchedulingWithSSA : public MethodPass {
const TargetMachine &Target;
const TargetMachine &target;
public:
inline InstructionSchedulingWithSSA(const TargetMachine &T) : Target(T) {}
inline InstructionSchedulingWithSSA(const TargetMachine &T) : target(T) {}
// getAnalysisUsageInfo - We use LiveVarInfo...
virtual void getAnalysisUsageInfo(Pass::AnalysisSet &Requires,
Pass::AnalysisSet &Destroyed,
Pass::AnalysisSet &Provided) {
Requires.push_back(MethodLiveVarInfo::ID);
Destroyed.push_back(MethodLiveVarInfo::ID);
}
bool runOnMethod(Method *M) {
cerr << "Instr scheduling failed for method " << ((Value*)M)->getName()
<< "\n\n";
SchedGraphSet graphSet(M, Target);
bool runOnMethod(Method *M);
};
} // end anonymous namespace
if (SchedDebugLevel >= Sched_PrintSchedGraphs) {
bool
InstructionSchedulingWithSSA::runOnMethod(Method *M)
{
if (SchedDebugLevel == Sched_Disable)
return false;
SchedGraphSet graphSet(M, target);
if (SchedDebugLevel >= Sched_PrintSchedGraphs)
{
cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n";
graphSet.dump();
}
for (SchedGraphSet::const_iterator GI=graphSet.begin();
GI != graphSet.end(); ++GI) {
SchedGraph* graph = GI->second;
for (SchedGraphSet::const_iterator GI=graphSet.begin(), GE=graphSet.end();
GI != GE; ++GI)
{
SchedGraph* graph = (*GI);
const vector<const BasicBlock*> &bbvec = graph->getBasicBlocks();
assert(bbvec.size() == 1 && "Cannot schedule multiple basic blocks");
const BasicBlock* bb = bbvec[0];
@ -1524,25 +1536,27 @@ namespace {
// expensive!
SchedPriorities schedPrio(M, graph,getAnalysis<MethodLiveVarInfo>());
SchedulingManager S(Target, graph, schedPrio);
SchedulingManager S(target, graph, schedPrio);
ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
ForwardListSchedule(S); // computes schedule in S
RecordSchedule(GI->first, S); // records schedule in BB
RecordSchedule(bb, S); // records schedule in BB
}
if (SchedDebugLevel >= Sched_PrintMachineCode) {
if (SchedDebugLevel >= Sched_PrintMachineCode)
{
cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n";
MachineCodeForMethod::get(M).dump();
}
return false;
}
};
} // end anonymous namespace
MethodPass *createInstructionSchedulingWithSSAPass(const TargetMachine &T) {
return new InstructionSchedulingWithSSA(T);
MethodPass*
createInstructionSchedulingWithSSAPass(const TargetMachine &tgt)
{
return new InstructionSchedulingWithSSA(tgt);
}

48
lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
View File

@ -31,6 +31,7 @@ using std::vector;
cl::Enum<enum SchedDebugLevel_t> SchedDebugLevel("dsched", cl::NoFlags,
"enable instruction scheduling debugging information",
clEnumValN(Sched_NoDebugInfo, "n", "disable debug output"),
clEnumValN(Sched_Disable, "off", "disable instruction scheduling"),
clEnumValN(Sched_PrintMachineCode, "y", "print machine code after scheduling"),
clEnumValN(Sched_PrintSchedTrace, "t", "print trace of scheduling actions"),
clEnumValN(Sched_PrintSchedGraphs, "g", "print scheduling graphs"), 0);
@ -1491,30 +1492,41 @@ instrIsFeasible(const SchedulingManager& S,
namespace {
class InstructionSchedulingWithSSA : public MethodPass {
const TargetMachine &Target;
const TargetMachine &target;
public:
inline InstructionSchedulingWithSSA(const TargetMachine &T) : Target(T) {}
inline InstructionSchedulingWithSSA(const TargetMachine &T) : target(T) {}
// getAnalysisUsageInfo - We use LiveVarInfo...
virtual void getAnalysisUsageInfo(Pass::AnalysisSet &Requires,
Pass::AnalysisSet &Destroyed,
Pass::AnalysisSet &Provided) {
Requires.push_back(MethodLiveVarInfo::ID);
Destroyed.push_back(MethodLiveVarInfo::ID);
}
bool runOnMethod(Method *M) {
cerr << "Instr scheduling failed for method " << ((Value*)M)->getName()
<< "\n\n";
SchedGraphSet graphSet(M, Target);
bool runOnMethod(Method *M);
};
} // end anonymous namespace
if (SchedDebugLevel >= Sched_PrintSchedGraphs) {
bool
InstructionSchedulingWithSSA::runOnMethod(Method *M)
{
if (SchedDebugLevel == Sched_Disable)
return false;
SchedGraphSet graphSet(M, target);
if (SchedDebugLevel >= Sched_PrintSchedGraphs)
{
cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n";
graphSet.dump();
}
for (SchedGraphSet::const_iterator GI=graphSet.begin();
GI != graphSet.end(); ++GI) {
SchedGraph* graph = GI->second;
for (SchedGraphSet::const_iterator GI=graphSet.begin(), GE=graphSet.end();
GI != GE; ++GI)
{
SchedGraph* graph = (*GI);
const vector<const BasicBlock*> &bbvec = graph->getBasicBlocks();
assert(bbvec.size() == 1 && "Cannot schedule multiple basic blocks");
const BasicBlock* bb = bbvec[0];
@ -1524,25 +1536,27 @@ namespace {
// expensive!
SchedPriorities schedPrio(M, graph,getAnalysis<MethodLiveVarInfo>());
SchedulingManager S(Target, graph, schedPrio);
SchedulingManager S(target, graph, schedPrio);
ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
ForwardListSchedule(S); // computes schedule in S
RecordSchedule(GI->first, S); // records schedule in BB
RecordSchedule(bb, S); // records schedule in BB
}
if (SchedDebugLevel >= Sched_PrintMachineCode) {
if (SchedDebugLevel >= Sched_PrintMachineCode)
{
cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n";
MachineCodeForMethod::get(M).dump();
}
return false;
}
};
} // end anonymous namespace
MethodPass *createInstructionSchedulingWithSSAPass(const TargetMachine &T) {
return new InstructionSchedulingWithSSA(T);
MethodPass*
createInstructionSchedulingWithSSAPass(const TargetMachine &tgt)
{
return new InstructionSchedulingWithSSA(tgt);
}