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Verify regunit intervals along with virtreg intervals.
Don't cause regunit intervals to be computed just to verify them. Only check the already cached intervals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161183 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1170,6 +1170,11 @@ void MachineVerifier::verifyLiveIntervals() {
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assert(Reg == LI.reg && "Invalid reg to interval mapping");
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verifyLiveInterval(LI);
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}
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// Verify all the cached regunit intervals.
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for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
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if (const LiveInterval *LI = LiveInts->getCachedRegUnit(i))
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verifyLiveInterval(*LI);
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}
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void MachineVerifier::verifyLiveIntervalValue(const LiveInterval &LI,
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@ -1227,7 +1232,7 @@ void MachineVerifier::verifyLiveIntervalValue(const LiveInterval &LI,
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continue;
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} else {
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if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
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!TRI->regsOverlap(LI.reg, MOI->getReg()))
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!TRI->hasRegUnit(MOI->getReg(), LI.reg))
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continue;
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}
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hasDef = true;
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@ -1294,6 +1299,11 @@ MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI,
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if (I->end == LiveInts->getMBBEndIdx(EndMBB))
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return;
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// RegUnit intervals are allowed dead phis.
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if (!TargetRegisterInfo::isVirtualRegister(LI.reg) && VNI->isPHIDef() &&
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I->start == VNI->def && I->end == VNI->def.getDeadSlot())
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return;
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// The live segment is ending inside EndMBB
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const MachineInstr *MI =
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LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
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@ -1371,7 +1381,7 @@ MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI,
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for (;;) {
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assert(LiveInts->isLiveInToMBB(LI, MFI));
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// We don't know how to track physregs into a landing pad.
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if (TargetRegisterInfo::isPhysicalRegister(LI.reg) &&
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if (!TargetRegisterInfo::isVirtualRegister(LI.reg) &&
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MFI->isLandingPad()) {
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if (&*MFI == EndMBB)
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break;
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