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R600: Factorise VTX_WORD0 and VTX_WORD1 in tblgen def
Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173220 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -173,6 +173,55 @@ class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{
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let Word1{17-13} = alu_inst;
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}
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class VTX_WORD0 {
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field bits<32> Word0;
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bits<7> SRC_GPR;
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bits<5> VC_INST;
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bits<2> FETCH_TYPE;
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bits<1> FETCH_WHOLE_QUAD;
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bits<8> BUFFER_ID;
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bits<1> SRC_REL;
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bits<2> SRC_SEL_X;
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bits<6> MEGA_FETCH_COUNT;
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let Word0{4-0} = VC_INST;
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let Word0{6-5} = FETCH_TYPE;
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let Word0{7} = FETCH_WHOLE_QUAD;
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let Word0{15-8} = BUFFER_ID;
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let Word0{22-16} = SRC_GPR;
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let Word0{23} = SRC_REL;
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let Word0{25-24} = SRC_SEL_X;
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let Word0{31-26} = MEGA_FETCH_COUNT;
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}
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class VTX_WORD1_GPR {
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field bits<32> Word1;
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bits<7> DST_GPR;
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bits<1> DST_REL;
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bits<3> DST_SEL_X;
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bits<3> DST_SEL_Y;
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bits<3> DST_SEL_Z;
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bits<3> DST_SEL_W;
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bits<1> USE_CONST_FIELDS;
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bits<6> DATA_FORMAT;
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bits<2> NUM_FORMAT_ALL;
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bits<1> FORMAT_COMP_ALL;
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bits<1> SRF_MODE_ALL;
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let Word1{6-0} = DST_GPR;
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let Word1{7} = DST_REL;
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let Word1{8} = 0; // Reserved
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let Word1{11-9} = DST_SEL_X;
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let Word1{14-12} = DST_SEL_Y;
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let Word1{17-15} = DST_SEL_Z;
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let Word1{20-18} = DST_SEL_W;
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let Word1{21} = USE_CONST_FIELDS;
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let Word1{27-22} = DATA_FORMAT;
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let Word1{29-28} = NUM_FORMAT_ALL;
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let Word1{30} = FORMAT_COMP_ALL;
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let Word1{31} = SRF_MODE_ALL;
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}
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/*
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XXX: R600 subtarget uses a slightly different encoding than the other
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subtargets. We currently handle this in R600MCCodeEmitter, but we may
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@ -1235,37 +1284,30 @@ def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
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>;
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class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
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: InstR600ISA <outs, (ins MEMxi:$ptr), name#" $dst, $ptr", pattern> {
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// Operands
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bits<7> DST_GPR;
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bits<7> SRC_GPR;
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: InstR600ISA <outs, (ins MEMxi:$ptr), name#" $dst, $ptr", pattern>,
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VTX_WORD1_GPR, VTX_WORD0 {
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// Static fields
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bits<5> VC_INST = 0;
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bits<2> FETCH_TYPE = 2;
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bits<1> FETCH_WHOLE_QUAD = 0;
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bits<8> BUFFER_ID = buffer_id;
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bits<1> SRC_REL = 0;
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let VC_INST = 0;
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let FETCH_TYPE = 2;
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let FETCH_WHOLE_QUAD = 0;
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let BUFFER_ID = buffer_id;
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let SRC_REL = 0;
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// XXX: We can infer this field based on the SRC_GPR. This would allow us
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// to store vertex addresses in any channel, not just X.
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bits<2> SRC_SEL_X = 0;
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bits<6> MEGA_FETCH_COUNT;
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bits<1> DST_REL = 0;
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bits<3> DST_SEL_X;
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bits<3> DST_SEL_Y;
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bits<3> DST_SEL_Z;
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bits<3> DST_SEL_W;
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let SRC_SEL_X = 0;
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let DST_REL = 0;
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// The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
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// FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
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// however, based on my testing if USE_CONST_FIELDS is set, then all
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// these fields need to be set to 0.
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bits<1> USE_CONST_FIELDS = 0;
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bits<6> DATA_FORMAT;
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bits<2> NUM_FORMAT_ALL = 1;
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bits<1> FORMAT_COMP_ALL = 0;
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bits<1> SRF_MODE_ALL = 0;
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let USE_CONST_FIELDS = 0;
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let NUM_FORMAT_ALL = 1;
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let FORMAT_COMP_ALL = 0;
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let SRF_MODE_ALL = 0;
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let Inst{31-0} = Word0;
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let Inst{63-32} = Word1;
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// LLVM can only encode 64-bit instructions, so these fields are manually
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// encoded in R600CodeEmitter
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//
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@ -1276,29 +1318,7 @@ class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
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// bits<1> ALT_CONST = 0;
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// bits<2> BUFFER_INDEX_MODE = 0;
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// VTX_WORD0
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let Inst{4-0} = VC_INST;
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let Inst{6-5} = FETCH_TYPE;
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let Inst{7} = FETCH_WHOLE_QUAD;
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let Inst{15-8} = BUFFER_ID;
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let Inst{22-16} = SRC_GPR;
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let Inst{23} = SRC_REL;
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let Inst{25-24} = SRC_SEL_X;
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let Inst{31-26} = MEGA_FETCH_COUNT;
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// VTX_WORD1_GPR
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let Inst{38-32} = DST_GPR;
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let Inst{39} = DST_REL;
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let Inst{40} = 0; // Reserved
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let Inst{43-41} = DST_SEL_X;
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let Inst{46-44} = DST_SEL_Y;
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let Inst{49-47} = DST_SEL_Z;
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let Inst{52-50} = DST_SEL_W;
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let Inst{53} = USE_CONST_FIELDS;
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let Inst{59-54} = DATA_FORMAT;
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let Inst{61-60} = NUM_FORMAT_ALL;
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let Inst{62} = FORMAT_COMP_ALL;
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let Inst{63} = SRF_MODE_ALL;
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// VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
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// is done in R600CodeEmitter
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