From 806e08c5a002a8288a001350eb009679462b972d Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Tue, 7 Oct 2014 23:51:41 +0000 Subject: [PATCH] R600/SI: Refactor VOP3 instruction defs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219256 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIInstrInfo.td | 31 +++++----- lib/Target/R600/SIInstructions.td | 94 +++++++++++++++---------------- 2 files changed, 64 insertions(+), 61 deletions(-) diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index ec3cffe48f7..9024ce5b7a7 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -29,6 +29,10 @@ class vop2 si> : vop { field bits<9> SI3 = {1, 0, 0, si{5-0}}; } +class vop3 si> : vop { + field bits<9> SI3 = si; +} + // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum // in AMDGPUMCInstLower.h def SISubtarget { @@ -643,12 +647,12 @@ class VOP3_Real_si op, dag outs, dag ins, string asm, string opName> : VOP3 , SIMCInstr; -multiclass VOP3_m op, dag outs, dag ins, string asm, list pattern, +multiclass VOP3_m pattern, string opName, int NumSrcArgs, bit HasMods = 1> { def "" : VOP3_Pseudo ; - def _si : VOP3_Real_si , + def _si : VOP3_Real_si , VOP3DisableFields; @@ -677,7 +681,7 @@ multiclass VOP3_2_m ; } -multiclass VOP3b_2_m op, dag outs, dag ins, string asm, +multiclass VOP3b_2_m pattern, string opName, string revOp, bit HasMods = 1, bit UseFullOp = 0> { def "" : VOP3_Pseudo , @@ -687,7 +691,7 @@ multiclass VOP3b_2_m op, dag outs, dag ins, string asm, // can write it into any SGPR. We currently don't use the carry out, // so for now hardcode it to VCC as well. let sdst = SIOperand.VCC, Defs = [VCC] in { - def _si : VOP3b , + def _si : VOP3b , VOP3DisableFields<1, 0, HasMods>, SIMCInstr, VOP2_REV; @@ -760,20 +764,19 @@ multiclass VOP2Inst ; -multiclass VOP2b_Helper op, string opName, dag outs, +multiclass VOP2b_Helper pat32, dag ins64, string asm64, list pat64, string revOp, bit HasMods> { - def _e32 : VOP2_e32 ; + def _e32 : VOP2_e32 ; - defm _e64 : VOP3b_2_m < - {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + defm _e64 : VOP3b_2_m ; } -multiclass VOP2bInst op, string opName, VOPProfile P, +multiclass VOP2bInst : VOP2b_Helper < op, opName, P.Outs, @@ -845,12 +848,12 @@ multiclass VOPCX_I32 : multiclass VOPCX_I64 : VOPCX ; -multiclass VOP3_Helper op, string opName, dag outs, dag ins, string asm, +multiclass VOP3_Helper pat, int NumSrcArgs, bit HasMods> : VOP3_m < op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods >; -multiclass VOP3Inst op, string opName, VOPProfile P, +multiclass VOP3Inst : VOP3_Helper < op, opName, P.Outs, P.Ins64, P.Asm64, !if(!eq(P.NumSrcArgs, 3), @@ -878,7 +881,7 @@ multiclass VOP3Inst op, string opName, VOPProfile P, P.NumSrcArgs, P.HasModifiers >; -multiclass VOP3b_Helper op, RegisterClass vrc, RegisterClass arc, +multiclass VOP3b_Helper pattern> : VOP3b_2_m < op, (outs vrc:$dst0, SReg_64:$dst1), @@ -890,10 +893,10 @@ multiclass VOP3b_Helper op, RegisterClass vrc, RegisterClass arc, opName, opName, 1, 1 >; -multiclass VOP3b_64 op, string opName, list pattern> : +multiclass VOP3b_64 pattern> : VOP3b_Helper ; -multiclass VOP3b_32 op, string opName, list pattern> : +multiclass VOP3b_32 pattern> : VOP3b_Helper ; diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 86f9c22b087..097ce59bb6e 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1444,24 +1444,24 @@ defm V_MBCNT_HI_U32_B32 : VOP2Inst , "V_MBCNT_HI_U32_B32", let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC // No patterns so that the scalar instructions are always selected. // The scalar versions will be replaced with vector when needed later. -defm V_ADD_I32 : VOP2bInst <0x00000025, "V_ADD_I32", +defm V_ADD_I32 : VOP2bInst , "V_ADD_I32", VOP_I32_I32_I32, add >; -defm V_SUB_I32 : VOP2bInst <0x00000026, "V_SUB_I32", +defm V_SUB_I32 : VOP2bInst , "V_SUB_I32", VOP_I32_I32_I32, sub >; -defm V_SUBREV_I32 : VOP2bInst <0x00000027, "V_SUBREV_I32", +defm V_SUBREV_I32 : VOP2bInst , "V_SUBREV_I32", VOP_I32_I32_I32, null_frag, "V_SUB_I32" >; let Uses = [VCC] in { // Carry-in comes from VCC -defm V_ADDC_U32 : VOP2bInst <0x00000028, "V_ADDC_U32", +defm V_ADDC_U32 : VOP2bInst , "V_ADDC_U32", VOP_I32_I32_I32_VCC, adde >; -defm V_SUBB_U32 : VOP2bInst <0x00000029, "V_SUBB_U32", +defm V_SUBB_U32 : VOP2bInst , "V_SUBB_U32", VOP_I32_I32_I32_VCC, sube >; -defm V_SUBBREV_U32 : VOP2bInst <0x0000002a, "V_SUBBREV_U32", +defm V_SUBBREV_U32 : VOP2bInst , "V_SUBBREV_U32", VOP_I32_I32_I32_VCC, null_frag, "V_SUBB_U32" >; @@ -1484,58 +1484,58 @@ defm V_CVT_PKRTZ_F16_F32 : VOP2Inst , "V_CVT_PKRTZ_F16_F32", // VOP3 Instructions //===----------------------------------------------------------------------===// -defm V_MAD_LEGACY_F32 : VOP3Inst <0x00000140, "V_MAD_LEGACY_F32", +defm V_MAD_LEGACY_F32 : VOP3Inst , "V_MAD_LEGACY_F32", VOP_F32_F32_F32_F32 >; -defm V_MAD_F32 : VOP3Inst <0x00000141, "V_MAD_F32", +defm V_MAD_F32 : VOP3Inst , "V_MAD_F32", VOP_F32_F32_F32_F32, fmad >; -defm V_MAD_I32_I24 : VOP3Inst <0x00000142, "V_MAD_I32_I24", +defm V_MAD_I32_I24 : VOP3Inst , "V_MAD_I32_I24", VOP_I32_I32_I32_I32, AMDGPUmad_i24 >; -defm V_MAD_U32_U24 : VOP3Inst <0x00000143, "V_MAD_U32_U24", +defm V_MAD_U32_U24 : VOP3Inst , "V_MAD_U32_U24", VOP_I32_I32_I32_I32, AMDGPUmad_u24 >; -defm V_CUBEID_F32 : VOP3Inst <0x00000144, "V_CUBEID_F32", +defm V_CUBEID_F32 : VOP3Inst , "V_CUBEID_F32", VOP_F32_F32_F32_F32 >; -defm V_CUBESC_F32 : VOP3Inst <0x00000145, "V_CUBESC_F32", +defm V_CUBESC_F32 : VOP3Inst , "V_CUBESC_F32", VOP_F32_F32_F32_F32 >; -defm V_CUBETC_F32 : VOP3Inst <0x00000146, "V_CUBETC_F32", +defm V_CUBETC_F32 : VOP3Inst , "V_CUBETC_F32", VOP_F32_F32_F32_F32 >; -defm V_CUBEMA_F32 : VOP3Inst <0x00000147, "V_CUBEMA_F32", +defm V_CUBEMA_F32 : VOP3Inst , "V_CUBEMA_F32", VOP_F32_F32_F32_F32 >; let neverHasSideEffects = 1, mayLoad = 0, mayStore = 0 in { -defm V_BFE_U32 : VOP3Inst <0x00000148, "V_BFE_U32", +defm V_BFE_U32 : VOP3Inst , "V_BFE_U32", VOP_I32_I32_I32_I32, AMDGPUbfe_u32 >; -defm V_BFE_I32 : VOP3Inst <0x00000149, "V_BFE_I32", +defm V_BFE_I32 : VOP3Inst , "V_BFE_I32", VOP_I32_I32_I32_I32, AMDGPUbfe_i32 >; } -defm V_BFI_B32 : VOP3Inst <0x0000014a, "V_BFI_B32", +defm V_BFI_B32 : VOP3Inst , "V_BFI_B32", VOP_I32_I32_I32_I32, AMDGPUbfi >; -defm V_FMA_F32 : VOP3Inst <0x0000014b, "V_FMA_F32", +defm V_FMA_F32 : VOP3Inst , "V_FMA_F32", VOP_F32_F32_F32_F32, fma >; -defm V_FMA_F64 : VOP3Inst <0x0000014c, "V_FMA_F64", +defm V_FMA_F64 : VOP3Inst , "V_FMA_F64", VOP_F64_F64_F64_F64, fma >; //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; -defm V_ALIGNBIT_B32 : VOP3Inst <0x0000014e, "V_ALIGNBIT_B32", +defm V_ALIGNBIT_B32 : VOP3Inst , "V_ALIGNBIT_B32", VOP_I32_I32_I32_I32 >; -defm V_ALIGNBYTE_B32 : VOP3Inst <0x0000014f, "V_ALIGNBYTE_B32", +defm V_ALIGNBYTE_B32 : VOP3Inst , "V_ALIGNBYTE_B32", VOP_I32_I32_I32_I32 >; -defm V_MULLIT_F32 : VOP3Inst <0x00000150, "V_MULLIT_F32", +defm V_MULLIT_F32 : VOP3Inst , "V_MULLIT_F32", VOP_F32_F32_F32_F32>; ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>; @@ -1549,81 +1549,81 @@ defm V_MULLIT_F32 : VOP3Inst <0x00000150, "V_MULLIT_F32", //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>; //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>; //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>; -defm V_SAD_U32 : VOP3Inst <0x0000015d, "V_SAD_U32", +defm V_SAD_U32 : VOP3Inst , "V_SAD_U32", VOP_I32_I32_I32_I32 >; ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>; defm V_DIV_FIXUP_F32 : VOP3Inst < - 0x0000015f, "V_DIV_FIXUP_F32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup + vop3<0x15f>, "V_DIV_FIXUP_F32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup >; defm V_DIV_FIXUP_F64 : VOP3Inst < - 0x00000160, "V_DIV_FIXUP_F64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup + vop3<0x160>, "V_DIV_FIXUP_F64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup >; -defm V_LSHL_B64 : VOP3Inst <0x00000161, "V_LSHL_B64", +defm V_LSHL_B64 : VOP3Inst , "V_LSHL_B64", VOP_I64_I64_I32, shl >; -defm V_LSHR_B64 : VOP3Inst <0x00000162, "V_LSHR_B64", +defm V_LSHR_B64 : VOP3Inst , "V_LSHR_B64", VOP_I64_I64_I32, srl >; -defm V_ASHR_I64 : VOP3Inst <0x00000163, "V_ASHR_I64", +defm V_ASHR_I64 : VOP3Inst , "V_ASHR_I64", VOP_I64_I64_I32, sra >; let isCommutable = 1 in { -defm V_ADD_F64 : VOP3Inst <0x00000164, "V_ADD_F64", +defm V_ADD_F64 : VOP3Inst , "V_ADD_F64", VOP_F64_F64_F64, fadd >; -defm V_MUL_F64 : VOP3Inst <0x00000165, "V_MUL_F64", +defm V_MUL_F64 : VOP3Inst , "V_MUL_F64", VOP_F64_F64_F64, fmul >; -defm V_MIN_F64 : VOP3Inst <0x00000166, "V_MIN_F64", +defm V_MIN_F64 : VOP3Inst , "V_MIN_F64", VOP_F64_F64_F64 >; -defm V_MAX_F64 : VOP3Inst <0x00000167, "V_MAX_F64", +defm V_MAX_F64 : VOP3Inst , "V_MAX_F64", VOP_F64_F64_F64 >; } // isCommutable = 1 -defm V_LDEXP_F64 : VOP3Inst <0x00000168, "V_LDEXP_F64", +defm V_LDEXP_F64 : VOP3Inst , "V_LDEXP_F64", VOP_F64_F64_I32, AMDGPUldexp >; let isCommutable = 1 in { -defm V_MUL_LO_U32 : VOP3Inst <0x00000169, "V_MUL_LO_U32", +defm V_MUL_LO_U32 : VOP3Inst , "V_MUL_LO_U32", VOP_I32_I32_I32 >; -defm V_MUL_HI_U32 : VOP3Inst <0x0000016a, "V_MUL_HI_U32", +defm V_MUL_HI_U32 : VOP3Inst , "V_MUL_HI_U32", VOP_I32_I32_I32 >; -defm V_MUL_LO_I32 : VOP3Inst <0x0000016b, "V_MUL_LO_I32", +defm V_MUL_LO_I32 : VOP3Inst , "V_MUL_LO_I32", VOP_I32_I32_I32 >; -defm V_MUL_HI_I32 : VOP3Inst <0x0000016c, "V_MUL_HI_I32", +defm V_MUL_HI_I32 : VOP3Inst , "V_MUL_HI_I32", VOP_I32_I32_I32 >; } // isCommutable = 1 -defm V_DIV_SCALE_F32 : VOP3b_32 <0x0000016d, "V_DIV_SCALE_F32", []>; +defm V_DIV_SCALE_F32 : VOP3b_32 , "V_DIV_SCALE_F32", []>; // Double precision division pre-scale. -defm V_DIV_SCALE_F64 : VOP3b_64 <0x0000016e, "V_DIV_SCALE_F64", []>; +defm V_DIV_SCALE_F64 : VOP3b_64 , "V_DIV_SCALE_F64", []>; -defm V_DIV_FMAS_F32 : VOP3Inst <0x0000016f, "V_DIV_FMAS_F32", +defm V_DIV_FMAS_F32 : VOP3Inst , "V_DIV_FMAS_F32", VOP_F32_F32_F32_F32, AMDGPUdiv_fmas >; -defm V_DIV_FMAS_F64 : VOP3Inst <0x00000170, "V_DIV_FMAS_F64", +defm V_DIV_FMAS_F64 : VOP3Inst , "V_DIV_FMAS_F64", VOP_F64_F64_F64_F64, AMDGPUdiv_fmas >; //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>; //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>; //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>; defm V_TRIG_PREOP_F64 : VOP3Inst < - 0x00000174, "V_TRIG_PREOP_F64", VOP_F64_F64_I32, AMDGPUtrig_preop + vop3<0x174>, "V_TRIG_PREOP_F64", VOP_F64_F64_I32, AMDGPUtrig_preop >; //===----------------------------------------------------------------------===// @@ -2877,21 +2877,21 @@ defm V_RNDNE_F64 : VOP1Inst , "V_RNDNE_F64", VOP_F64_F64, frint >; -defm V_QSAD_PK_U16_U8 : VOP3Inst <0x00000173, "V_QSAD_PK_U16_U8", +defm V_QSAD_PK_U16_U8 : VOP3Inst , "V_QSAD_PK_U16_U8", VOP_I32_I32_I32 >; -defm V_MQSAD_U16_U8 : VOP3Inst <0x000000172, "V_MQSAD_U16_U8", +defm V_MQSAD_U16_U8 : VOP3Inst , "V_MQSAD_U16_U8", VOP_I32_I32_I32 >; -defm V_MQSAD_U32_U8 : VOP3Inst <0x00000175, "V_MQSAD_U32_U8", +defm V_MQSAD_U32_U8 : VOP3Inst , "V_MQSAD_U32_U8", VOP_I32_I32_I32 >; -defm V_MAD_U64_U32 : VOP3Inst <0x00000176, "V_MAD_U64_U32", +defm V_MAD_U64_U32 : VOP3Inst , "V_MAD_U64_U32", VOP_I64_I32_I32_I64 >; // XXX - Does this set VCC? -defm V_MAD_I64_I32 : VOP3Inst <0x00000177, "V_MAD_I64_I32", +defm V_MAD_I64_I32 : VOP3Inst , "V_MAD_I64_I32", VOP_I64_I32_I32_I64 >;