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Suppress '(x < y) ? a : 0 -> (x < y) & a' transform on X86 architectures with dedicated mask registers.
Patch by Aleksey Bader. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196386 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -17010,12 +17010,13 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
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// Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
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if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
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// Check if SETCC has already been promoted
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TLI.getSetCCResultType(*DAG.getContext(), VT) == Cond.getValueType()) {
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TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
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// Check that condition value type matches vselect operand type
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CondVT == VT) {
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assert(Cond.getValueType().isVector() &&
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"vector select expects a vector selector!");
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EVT IntVT = Cond.getValueType();
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bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
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bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
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@ -17030,7 +17031,7 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
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ISD::CondCode NewCC =
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ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
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Cond.getOperand(0).getValueType().isInteger());
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Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
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Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
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std::swap(LHS, RHS);
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TValIsAllOnes = FValIsAllOnes;
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FValIsAllZeros = TValIsAllZeros;
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@ -17043,11 +17044,11 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
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if (TValIsAllOnes && FValIsAllZeros)
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Ret = Cond;
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else if (TValIsAllOnes)
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Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
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DAG.getNode(ISD::BITCAST, DL, IntVT, RHS));
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Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
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DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
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else if (FValIsAllZeros)
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Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond,
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DAG.getNode(ISD::BITCAST, DL, IntVT, LHS));
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Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
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DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
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return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
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}
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11
test/CodeGen/X86/avx512-vselect-crash.ll
Normal file
11
test/CodeGen/X86/avx512-vselect-crash.ll
Normal file
@ -0,0 +1,11 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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; CHECK-LABEL: test
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; CHECK: vmovdqu32
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; CHECK: ret
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define <16 x i32> @test() {
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entry:
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%0 = icmp slt <16 x i32> undef, undef
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%1 = select <16 x i1> %0, <16 x i32> undef, <16 x i32> zeroinitializer
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ret <16 x i32> %1
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}
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