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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
Fix VFP conversion instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59104 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -347,6 +347,8 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
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case ARMII::VFPConv1Frm:
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case ARMII::VFPConv2Frm:
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case ARMII::VFPConv3Frm:
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case ARMII::VFPConv4Frm:
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case ARMII::VFPConv5Frm:
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emitVFPConversionInstruction(MI);
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break;
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case ARMII::VFPLdStFrm:
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@ -1095,22 +1097,9 @@ void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
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emitWordLE(Binary);
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}
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void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
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const TargetInstrDesc &TID = MI.getDesc();
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// Part of binary is determined by TableGn.
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unsigned Binary = getBinaryCodeForInstr(MI);
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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// FMDRR encodes registers in reverse order.
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unsigned Form = TID.TSFlags & ARMII::FormMask;
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unsigned OpIdx = (Form == ARMII::VFPConv2Frm)
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? MI.findFirstPredOperandIdx()-1 : 0;
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// Encode Dd / Sd.
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static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
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unsigned RegD = MI.getOperand(OpIdx).getReg();
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unsigned Binary = 0;
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bool isSPVFP = false;
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RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
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if (!isSPVFP)
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@ -1119,29 +1108,13 @@ void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
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Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
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Binary |= (RegD & 0x01) << ARMII::D_BitShift;
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}
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if (Form == ARMII::VFPConv2Frm)
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--OpIdx;
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else
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++OpIdx;
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return Binary;
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}
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if (Form == ARMII::VFPConv3Frm) {
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unsigned RegM = MI.getOperand(OpIdx).getReg();
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isSPVFP = false;
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RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
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if (!isSPVFP)
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Binary |= RegM;
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else {
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Binary |= ((RegM & 0x1E) >> 1);
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Binary |= (RegM & 0x01) << ARMII::M_BitShift;
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}
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emitWordLE(Binary);
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return;
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}
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// Encode Dn / Sn.
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static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
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unsigned RegN = MI.getOperand(OpIdx).getReg();
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isSPVFP = false;
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unsigned Binary = 0;
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bool isSPVFP = false;
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RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP);
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if (!isSPVFP)
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Binary |= RegN << ARMII::RegRnShift;
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@ -1149,23 +1122,74 @@ void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
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Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
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Binary |= (RegN & 0x01) << ARMII::N_BitShift;
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}
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if (Form == ARMII::VFPConv2Frm)
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--OpIdx;
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else
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++OpIdx;
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return Binary;
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}
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// FMRS / FMSR do not have Rm.
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if (TID.getNumOperands() > OpIdx && MI.getOperand(OpIdx).isReg()) {
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unsigned RegM = MI.getOperand(OpIdx).getReg();
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isSPVFP = false;
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RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
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if (!isSPVFP)
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Binary |= RegM;
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else {
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Binary |= ((RegM & 0x1E) >> 1);
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Binary |= (RegM & 0x01) << ARMII::M_BitShift;
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}
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static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
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unsigned RegM = MI.getOperand(OpIdx).getReg();
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unsigned Binary = 0;
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bool isSPVFP = false;
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RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
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if (!isSPVFP)
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Binary |= RegM;
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else {
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Binary |= ((RegM & 0x1E) >> 1);
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Binary |= (RegM & 0x01) << ARMII::M_BitShift;
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}
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return Binary;
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}
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void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
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const TargetInstrDesc &TID = MI.getDesc();
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unsigned Form = TID.TSFlags & ARMII::FormMask;
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// Part of binary is determined by TableGn.
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unsigned Binary = getBinaryCodeForInstr(MI);
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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switch (Form) {
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default: break;
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case ARMII::VFPConv1Frm:
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case ARMII::VFPConv2Frm:
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case ARMII::VFPConv3Frm:
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// Encode Dd / Sd.
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Binary |= encodeVFPRd(MI, 0);
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break;
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case ARMII::VFPConv4Frm:
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// Encode Dn / Sn.
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Binary |= encodeVFPRn(MI, 0);
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break;
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case ARMII::VFPConv5Frm:
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// Encode Dm / Sm.
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Binary |= encodeVFPRm(MI, 0);
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break;
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}
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switch (Form) {
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default: break;
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case ARMII::VFPConv1Frm:
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// Encode Dm / Sm.
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Binary |= encodeVFPRm(MI, 1);
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case ARMII::VFPConv2Frm:
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case ARMII::VFPConv3Frm:
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// Encode Dn / Sn.
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Binary |= encodeVFPRn(MI, 1);
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break;
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case ARMII::VFPConv4Frm:
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case ARMII::VFPConv5Frm:
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// Encode Dd / Sd.
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Binary |= encodeVFPRd(MI, 1);
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break;
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}
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if (Form == ARMII::VFPConv5Frm)
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// Encode Dn / Sn.
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Binary |= encodeVFPRn(MI, 2);
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else if (Form == ARMII::VFPConv3Frm)
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// Encode Dm / Sm.
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Binary |= encodeVFPRm(MI, 2);
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emitWordLE(Binary);
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}
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@ -42,11 +42,13 @@ def VFPBinaryFrm : Format<16>;
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def VFPConv1Frm : Format<17>;
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def VFPConv2Frm : Format<18>;
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def VFPConv3Frm : Format<19>;
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def VFPLdStFrm : Format<20>;
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def VFPLdStMulFrm : Format<21>;
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def VFPMiscFrm : Format<22>;
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def VFPConv4Frm : Format<20>;
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def VFPConv5Frm : Format<21>;
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def VFPLdStFrm : Format<22>;
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def VFPLdStMulFrm : Format<23>;
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def VFPMiscFrm : Format<24>;
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def ThumbFrm : Format<23>;
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def ThumbFrm : Format<25>;
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// Misc flag for data processing instructions that indicates whether
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// the instruction has a Rn register operand.
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@ -820,30 +822,39 @@ class ASbI<bits<8> opcod, dag oops, dag iops, string opc,
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let Inst{11-8} = 0b1010;
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}
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class AVConv1I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
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string asm, list<dag> pattern>
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// VFP conversion instructions
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class AVConv1I<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3,
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dag oops, dag iops, string opc, string asm, list<dag> pattern>
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: AI<oops, iops, VFPConv1Frm, opc, asm, pattern> {
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let Inst{27-20} = opcod1;
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let Inst{19-16} = opcod2;
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let Inst{11-8} = opcod3;
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let Inst{6} = 1;
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}
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class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
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string opc, string asm, list<dag> pattern>
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: AI<oops, iops, f, opc, asm, pattern> {
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let Inst{27-20} = opcod1;
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let Inst{11-8} = opcod2;
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let Inst{4} = 1;
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}
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class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
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string asm, list<dag> pattern>
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: AI<oops, iops, VFPConv2Frm, opc, asm, pattern> {
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let Inst{27-20} = opcod1;
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let Inst{11-8} = opcod2;
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let Inst{4} = 1;
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}
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string asm, list<dag> pattern>
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: AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, opc, asm, pattern>;
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class AVConv3I<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3,
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dag oops, dag iops, string opc, string asm, list<dag> pattern>
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: AI<oops, iops, VFPConv3Frm, opc, asm, pattern> {
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let Inst{27-20} = opcod1;
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let Inst{19-16} = opcod2;
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let Inst{11-8} = opcod3;
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let Inst{6} = 1;
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}
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class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
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string asm, list<dag> pattern>
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: AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, opc, asm, pattern>;
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class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
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string asm, list<dag> pattern>
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: AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, opc, asm, pattern>;
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class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
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string asm, list<dag> pattern>
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: AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, opc, asm, pattern>;
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//===----------------------------------------------------------------------===//
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@ -106,12 +106,14 @@ namespace ARMII {
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VFPConv1Frm = 17 << FormShift,
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VFPConv2Frm = 18 << FormShift,
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VFPConv3Frm = 19 << FormShift,
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VFPLdStFrm = 20 << FormShift,
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VFPLdStMulFrm = 21 << FormShift,
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VFPMiscFrm = 22 << FormShift,
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VFPConv4Frm = 20 << FormShift,
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VFPConv5Frm = 21 << FormShift,
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VFPLdStFrm = 22 << FormShift,
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VFPLdStMulFrm = 23 << FormShift,
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VFPMiscFrm = 24 << FormShift,
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// Thumb format
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ThumbFrm = 23 << FormShift,
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ThumbFrm = 25 << FormShift,
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//===------------------------------------------------------------------===//
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// Field shifts - such shifts are used to set field while generating
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@ -219,15 +219,15 @@ def FSQRTS : ASuI<0b11101011, 0b0001, 0b1100, (outs SPR:$dst), (ins SPR:$a),
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// FP <-> GPR Copies. Int <-> FP Conversions.
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//
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def FMRS : AVConv1I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src),
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def FMRS : AVConv2I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src),
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"fmrs", " $dst, $src",
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[(set GPR:$dst, (bitconvert SPR:$src))]>;
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def FMSR : AVConv2I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src),
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def FMSR : AVConv4I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src),
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"fmsr", " $dst, $src",
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[(set SPR:$dst, (bitconvert GPR:$src))]>;
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def FMRRD : AVConv1I<0b11000101, 0b1011,
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def FMRRD : AVConv3I<0b11000101, 0b1011,
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(outs GPR:$dst1, GPR:$dst2), (ins DPR:$src),
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"fmrrd", " $dst1, $dst2, $src",
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[/* FIXME: Can't write pattern for multiple result instr*/]>;
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@ -235,7 +235,7 @@ def FMRRD : AVConv1I<0b11000101, 0b1011,
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// FMDHR: GPR -> SPR
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// FMDLR: GPR -> SPR
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def FMDRR : AVConv2I<0b11000100, 0b1011, (outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
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def FMDRR : AVConv5I<0b11000100, 0b1011, (outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
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"fmdrr", " $dst, $src1, $src2",
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[(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>;
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@ -251,25 +251,25 @@ def FMDRR : AVConv2I<0b11000100, 0b1011, (outs DPR:$dst), (ins GPR:$src1, GPR:$s
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// Int to FP:
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def FSITOD : AVConv3I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
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def FSITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
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"fsitod", " $dst, $a",
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[(set DPR:$dst, (arm_sitof SPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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def FSITOS : AVConv3I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
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def FSITOS : AVConv1I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
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"fsitos", " $dst, $a",
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[(set SPR:$dst, (arm_sitof SPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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def FUITOD : AVConv3I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
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def FUITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
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"fuitod", " $dst, $a",
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[(set DPR:$dst, (arm_uitof SPR:$a))]> {
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let Inst{7} = 0; // Z bit
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}
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def FUITOS : AVConv3I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
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def FUITOS : AVConv1I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
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"fuitos", " $dst, $a",
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[(set SPR:$dst, (arm_uitof SPR:$a))]> {
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let Inst{7} = 1; // Z bit
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@ -278,28 +278,28 @@ def FUITOS : AVConv3I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
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// FP to Int:
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// Always set Z bit in the instruction, i.e. "round towards zero" variants.
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def FTOSIZD : AVConv3I<0b11101011, 0b1101, 0b1011,
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def FTOSIZD : AVConv1I<0b11101011, 0b1101, 0b1011,
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(outs SPR:$dst), (ins DPR:$a),
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"ftosizd", " $dst, $a",
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[(set SPR:$dst, (arm_ftosi DPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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def FTOSIZS : AVConv3I<0b11101011, 0b1101, 0b1010,
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def FTOSIZS : AVConv1I<0b11101011, 0b1101, 0b1010,
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(outs SPR:$dst), (ins SPR:$a),
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"ftosizs", " $dst, $a",
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[(set SPR:$dst, (arm_ftosi SPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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def FTOUIZD : AVConv3I<0b11101011, 0b1100, 0b1011,
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def FTOUIZD : AVConv1I<0b11101011, 0b1100, 0b1011,
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(outs SPR:$dst), (ins DPR:$a),
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"ftouizd", " $dst, $a",
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[(set SPR:$dst, (arm_ftoui DPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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def FTOUIZS : AVConv3I<0b11101011, 0b1100, 0b1010,
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def FTOUIZS : AVConv1I<0b11101011, 0b1100, 0b1010,
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(outs SPR:$dst), (ins SPR:$a),
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"ftouizs", " $dst, $a",
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[(set SPR:$dst, (arm_ftoui SPR:$a))]> {
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