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Added release notes for the Mips target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@223231 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -24,6 +24,40 @@ them.
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Non-comprehensive list of changes in this release
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Non-comprehensive list of changes in this release
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=================================================
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=================================================
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Changes to the MIPS Target
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--------------------------
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* A large number of bugs have been fixed for big-endian Mips targets using the
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N32 and N64 ABI's. Please note that some of these bugs will still affect
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LLVM-IR generated by LLVM 3.5 since correct code generation depends on
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appropriate usage of the ``inreg``, ``signext``, and ``zeroext`` attributes
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on all function arguments and returns.
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* The registers used to return a structure containing a single 128-bit floating
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point member on the N32/N64 ABI's have been changed from those specified by
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the ABI documentation to match those used by GCC. The documentation specifies
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that ``$f0`` and ``$f2`` should be used but GCC has used ``$f0`` and ``$f1``
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for many years.
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* Returning a zero-byte struct no longer causes incorrect code generation when
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using the O32 ABI.
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* The exception personality has been changed for 64-bit Mips targets to
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eliminate warnings about relocations in a read-only section.
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* Incorrect usage of odd-numbered single-precision floating point registers
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has been fixed when the fastcc calling convention is used with 64-bit FPU's
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and -mno-odd-spreg.
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* For inline assembly, the 'z' print-modifier print modifier can now be used on
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non-immediate values.
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* Attempting to disassemble l[wd]c[23], s[wd]c[23], cache, and pref no longer
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triggers an assertion.
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Non-comprehensive list of changes in 3.5
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========================================
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* All backends have been changed to use the MC asm printer and support for the
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* All backends have been changed to use the MC asm printer and support for the
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non MC one has been removed.
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non MC one has been removed.
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