mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207327 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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57d7597572
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@ -496,7 +496,8 @@ public:
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SDValue Glue) {
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SDValue Glue) {
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SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
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SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
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SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Glue };
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SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Glue };
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return getNode(ISD::CopyToReg, dl, VTs, Ops, Glue.getNode() ? 4 : 3);
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return getNode(ISD::CopyToReg, dl, VTs,
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ArrayRef<SDValue>(Ops, Glue.getNode() ? 4 : 3));
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}
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}
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// Similar to last getCopyToReg() except parameter Reg is a SDValue
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// Similar to last getCopyToReg() except parameter Reg is a SDValue
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@ -504,13 +505,14 @@ public:
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SDValue Glue) {
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SDValue Glue) {
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SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
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SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
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SDValue Ops[] = { Chain, Reg, N, Glue };
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SDValue Ops[] = { Chain, Reg, N, Glue };
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return getNode(ISD::CopyToReg, dl, VTs, Ops, Glue.getNode() ? 4 : 3);
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return getNode(ISD::CopyToReg, dl, VTs,
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ArrayRef<SDValue>(Ops, Glue.getNode() ? 4 : 3));
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}
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}
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SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT) {
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SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT) {
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SDVTList VTs = getVTList(VT, MVT::Other);
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SDVTList VTs = getVTList(VT, MVT::Other);
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SDValue Ops[] = { Chain, getRegister(Reg, VT) };
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SDValue Ops[] = { Chain, getRegister(Reg, VT) };
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return getNode(ISD::CopyFromReg, dl, VTs, Ops, 2);
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return getNode(ISD::CopyFromReg, dl, VTs, Ops);
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}
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}
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// This version of the getCopyFromReg method takes an extra operand, which
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// This version of the getCopyFromReg method takes an extra operand, which
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@ -520,7 +522,8 @@ public:
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SDValue Glue) {
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SDValue Glue) {
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SDVTList VTs = getVTList(VT, MVT::Other, MVT::Glue);
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SDVTList VTs = getVTList(VT, MVT::Other, MVT::Glue);
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SDValue Ops[] = { Chain, getRegister(Reg, VT), Glue };
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SDValue Ops[] = { Chain, getRegister(Reg, VT), Glue };
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return getNode(ISD::CopyFromReg, dl, VTs, Ops, Glue.getNode() ? 3 : 2);
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return getNode(ISD::CopyFromReg, dl, VTs,
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ArrayRef<SDValue>(Ops, Glue.getNode() ? 3 : 2));
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}
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}
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SDValue getCondCode(ISD::CondCode Cond);
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SDValue getCondCode(ISD::CondCode Cond);
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@ -563,7 +566,7 @@ public:
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SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL) {
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SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL) {
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SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
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SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
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SDValue Ops[] = { Chain, Op };
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SDValue Ops[] = { Chain, Op };
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return getNode(ISD::CALLSEQ_START, DL, VTs, Ops, 2);
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return getNode(ISD::CALLSEQ_START, DL, VTs, Ops);
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}
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}
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/// getCALLSEQ_END - Return a new CALLSEQ_END node, which always must have a
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/// getCALLSEQ_END - Return a new CALLSEQ_END node, which always must have a
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@ -576,9 +579,9 @@ public:
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Ops.push_back(Chain);
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Ops.push_back(Chain);
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Ops.push_back(Op1);
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Ops.push_back(Op1);
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Ops.push_back(Op2);
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Ops.push_back(Op2);
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if (InGlue.getNode())
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Ops.push_back(InGlue);
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Ops.push_back(InGlue);
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return getNode(ISD::CALLSEQ_END, DL, NodeTys, &Ops[0],
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return getNode(ISD::CALLSEQ_END, DL, NodeTys, Ops);
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(unsigned)Ops.size() - (InGlue.getNode()==nullptr ? 1 : 0));
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}
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}
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/// getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
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/// getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
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@ -607,12 +610,12 @@ public:
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SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
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SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
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const SDUse *Ops, unsigned NumOps);
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const SDUse *Ops, unsigned NumOps);
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SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
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SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
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const SDValue *Ops, unsigned NumOps);
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ArrayRef<SDValue> Ops);
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SDValue getNode(unsigned Opcode, SDLoc DL,
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SDValue getNode(unsigned Opcode, SDLoc DL,
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ArrayRef<EVT> ResultTys,
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ArrayRef<EVT> ResultTys,
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const SDValue *Ops, unsigned NumOps);
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ArrayRef<SDValue> Ops);
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SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
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SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
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const SDValue *Ops, unsigned NumOps);
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ArrayRef<SDValue> Ops);
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SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs);
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SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs);
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SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N);
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SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N);
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SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
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SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
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@ -1402,8 +1402,7 @@ SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
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Result = DAG.getEntryNode();
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Result = DAG.getEntryNode();
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} else {
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} else {
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// New and improved token factor.
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// New and improved token factor.
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Result = DAG.getNode(ISD::TokenFactor, SDLoc(N),
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Result = DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Ops);
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MVT::Other, &Ops[0], Ops.size());
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}
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}
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// Don't add users to work list.
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// Don't add users to work list.
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@ -4762,7 +4761,7 @@ static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
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SVT));
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SVT));
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}
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}
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return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], NumElts).getNode();
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return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Elts).getNode();
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}
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}
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// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
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// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
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@ -4846,8 +4845,7 @@ void DAGCombiner::ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
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}
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}
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Ops.push_back(SetCC->getOperand(2));
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Ops.push_back(SetCC->getOperand(2));
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CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
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CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops));
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&Ops[0], Ops.size()));
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}
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}
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}
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}
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@ -5319,7 +5317,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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N0.getOperand(1),
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N0.getOperand(1),
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cast<CondCodeSDNode>(N0.getOperand(2))->get()),
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cast<CondCodeSDNode>(N0.getOperand(2))->get()),
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DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT,
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DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT,
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&OneOps[0], OneOps.size()));
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OneOps));
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// If the desired elements are smaller or larger than the source
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// If the desired elements are smaller or larger than the source
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// elements we can use a matching integer vector type and then
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// elements we can use a matching integer vector type and then
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@ -5336,8 +5334,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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cast<CondCodeSDNode>(N0.getOperand(2))->get());
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cast<CondCodeSDNode>(N0.getOperand(2))->get());
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return DAG.getNode(ISD::AND, SDLoc(N), VT,
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return DAG.getNode(ISD::AND, SDLoc(N), VT,
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DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT),
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DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT),
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DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT,
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DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, OneOps));
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&OneOps[0], OneOps.size()));
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}
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}
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// zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
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// zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
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@ -5865,7 +5862,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
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Op.getValueType()));
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Op.getValueType()));
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}
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}
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, &Elts[0], NumElts);
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Elts);
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}
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}
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return SDValue();
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return SDValue();
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@ -5966,8 +5963,7 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
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for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset)
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for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset)
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Opnds.push_back(BuildVect.getOperand(i));
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Opnds.push_back(BuildVect.getOperand(i));
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, &Opnds[0],
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
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Opnds.size());
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}
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}
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}
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}
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@ -6042,8 +6038,7 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
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AddToWorkList(NV.getNode());
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AddToWorkList(NV.getNode());
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Opnds.push_back(NV);
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Opnds.push_back(NV);
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}
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}
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return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
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return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Opnds);
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&Opnds[0], Opnds.size());
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}
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}
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}
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}
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@ -6281,8 +6276,7 @@ ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
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DstEltVT, Op));
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DstEltVT, Op));
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AddToWorkList(Ops.back().getNode());
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AddToWorkList(Ops.back().getNode());
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}
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}
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT,
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
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&Ops[0], Ops.size());
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}
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}
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// Otherwise, we're growing or shrinking the elements. To avoid having to
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// Otherwise, we're growing or shrinking the elements. To avoid having to
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@ -6338,8 +6332,7 @@ ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
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}
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}
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EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
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EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT,
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
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&Ops[0], Ops.size());
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}
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}
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// Finally, this must be the case where we are shrinking elements: each input
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// Finally, this must be the case where we are shrinking elements: each input
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@ -6375,8 +6368,7 @@ ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
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std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
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std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
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}
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}
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT,
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
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&Ops[0], Ops.size());
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}
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}
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SDValue DAGCombiner::visitFADD(SDNode *N) {
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SDValue DAGCombiner::visitFADD(SDNode *N) {
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@ -6974,7 +6966,7 @@ SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
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{ N0.getOperand(0), N0.getOperand(1),
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{ N0.getOperand(0), N0.getOperand(1),
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DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT),
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DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT),
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N0.getOperand(2) };
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N0.getOperand(2) };
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return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops, 5);
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return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
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}
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}
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// fold (sint_to_fp (zext (setcc x, y, cc))) ->
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// fold (sint_to_fp (zext (setcc x, y, cc))) ->
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@ -6987,7 +6979,7 @@ SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
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{ N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
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{ N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
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DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT),
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DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT),
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N0.getOperand(0).getOperand(2) };
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N0.getOperand(0).getOperand(2) };
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return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops, 5);
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return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
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}
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}
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}
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}
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@ -7031,7 +7023,7 @@ SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
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{ N0.getOperand(0), N0.getOperand(1),
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{ N0.getOperand(0), N0.getOperand(1),
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DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT),
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DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT),
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N0.getOperand(2) };
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N0.getOperand(2) };
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return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops, 5);
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return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
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}
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}
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}
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}
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@ -8523,7 +8515,7 @@ bool DAGCombiner::SliceUpLoad(SDNode *N) {
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}
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}
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SDValue Chain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other,
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SDValue Chain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other,
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&ArgChains[0], ArgChains.size());
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ArgChains);
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DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
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DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
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return true;
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return true;
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}
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}
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@ -9677,8 +9669,7 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
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}
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}
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// Return the new vector
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// Return the new vector
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return DAG.getNode(ISD::BUILD_VECTOR, dl,
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return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
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VT, &Ops[0], Ops.size());
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}
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}
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SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
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SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
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@ -10010,7 +10001,7 @@ SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) {
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if (!isTypeLegal(VecVT)) return SDValue();
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if (!isTypeLegal(VecVT)) return SDValue();
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// Make the new BUILD_VECTOR.
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// Make the new BUILD_VECTOR.
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SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], Ops.size());
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SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
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// The new BUILD_VECTOR node has the potential to be further optimized.
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// The new BUILD_VECTOR node has the potential to be further optimized.
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AddToWorkList(BV.getNode());
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AddToWorkList(BV.getNode());
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@ -10078,8 +10069,7 @@ SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
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else
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else
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Opnds.push_back(In.getOperand(0));
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Opnds.push_back(In.getOperand(0));
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}
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}
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SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT,
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SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Opnds);
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&Opnds[0], Opnds.size());
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AddToWorkList(BV.getNode());
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AddToWorkList(BV.getNode());
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return DAG.getNode(Opcode, dl, VT, BV);
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return DAG.getNode(Opcode, dl, VT, BV);
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@ -10269,8 +10259,7 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
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for (unsigned i = 0; i != BuildVecNumElts; ++i)
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for (unsigned i = 0; i != BuildVecNumElts; ++i)
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Opnds.push_back(N1.getOperand(i));
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Opnds.push_back(N1.getOperand(i));
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, &Opnds[0],
|
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
|
||||||
Opnds.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR
|
// Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR
|
||||||
@ -10427,8 +10416,7 @@ static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops.data(),
|
return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
|
||||||
Ops.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
|
SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
|
||||||
@ -10643,8 +10631,7 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
|
|||||||
EVT EltVT = RVT.getVectorElementType();
|
EVT EltVT = RVT.getVectorElementType();
|
||||||
SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
|
SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
|
||||||
DAG.getConstant(0, EltVT));
|
DAG.getConstant(0, EltVT));
|
||||||
SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
|
SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), RVT, ZeroOps);
|
||||||
RVT, &ZeroOps[0], ZeroOps.size());
|
|
||||||
LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
|
LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
|
||||||
SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
|
SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
|
||||||
return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
|
return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
|
||||||
@ -10713,8 +10700,7 @@ SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (Ops.size() == LHS.getNumOperands())
|
if (Ops.size() == LHS.getNumOperands())
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
|
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), LHS.getValueType(), Ops);
|
||||||
LHS.getValueType(), &Ops[0], Ops.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return SDValue();
|
return SDValue();
|
||||||
@ -10749,8 +10735,7 @@ SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) {
|
|||||||
if (Ops.size() != N0.getNumOperands())
|
if (Ops.size() != N0.getNumOperands())
|
||||||
return SDValue();
|
return SDValue();
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
|
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N0.getValueType(), Ops);
|
||||||
N0.getValueType(), &Ops[0], Ops.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0,
|
SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0,
|
||||||
@ -11544,8 +11529,7 @@ SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
|
|||||||
return Aliases[0];
|
return Aliases[0];
|
||||||
|
|
||||||
// Construct a custom tailored token factor.
|
// Construct a custom tailored token factor.
|
||||||
return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other,
|
return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Aliases);
|
||||||
&Aliases[0], Aliases.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// SelectionDAG::Combine - This is the entry point for the file.
|
// SelectionDAG::Combine - This is the entry point for the file.
|
||||||
|
@ -387,9 +387,7 @@ static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
|
|||||||
MinAlign(ST->getAlignment(), Offset),
|
MinAlign(ST->getAlignment(), Offset),
|
||||||
ST->getTBAAInfo()));
|
ST->getTBAAInfo()));
|
||||||
// The order of the stores doesn't matter - say it with a TokenFactor.
|
// The order of the stores doesn't matter - say it with a TokenFactor.
|
||||||
SDValue Result =
|
SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
|
||||||
DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
|
|
||||||
Stores.size());
|
|
||||||
DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
|
DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@ -506,8 +504,7 @@ ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
|
|||||||
false, false, 0));
|
false, false, 0));
|
||||||
|
|
||||||
// The order of the stores doesn't matter - say it with a TokenFactor.
|
// The order of the stores doesn't matter - say it with a TokenFactor.
|
||||||
SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
|
SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
|
||||||
Stores.size());
|
|
||||||
|
|
||||||
// Finally, perform the original load only redirected to the stack slot.
|
// Finally, perform the original load only redirected to the stack slot.
|
||||||
Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
|
Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
|
||||||
@ -1528,8 +1525,7 @@ SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
|
|||||||
|
|
||||||
SDValue StoreChain;
|
SDValue StoreChain;
|
||||||
if (!Stores.empty()) // Not all undef elements?
|
if (!Stores.empty()) // Not all undef elements?
|
||||||
StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
|
||||||
&Stores[0], Stores.size());
|
|
||||||
else
|
else
|
||||||
StoreChain = DAG.getEntryNode();
|
StoreChain = DAG.getEntryNode();
|
||||||
|
|
||||||
@ -3304,7 +3300,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
|
|||||||
TLI.getVectorIdxTy())));
|
TLI.getVectorIdxTy())));
|
||||||
}
|
}
|
||||||
|
|
||||||
Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
|
Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
|
||||||
// We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
|
// We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
|
||||||
Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
|
Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
|
||||||
Results.push_back(Tmp1);
|
Results.push_back(Tmp1);
|
||||||
@ -4011,8 +4007,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
|
|||||||
VT.getScalarType(), Ex, Sh));
|
VT.getScalarType(), Ex, Sh));
|
||||||
}
|
}
|
||||||
SDValue Result =
|
SDValue Result =
|
||||||
DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
|
DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Scalars);
|
||||||
&Scalars[0], Scalars.size());
|
|
||||||
ReplaceNode(SDValue(Node, 0), Result);
|
ReplaceNode(SDValue(Node, 0), Result);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -434,7 +434,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
|
|||||||
EVT ValueVTs[] = { N->getValueType(0), NVT };
|
EVT ValueVTs[] = { N->getValueType(0), NVT };
|
||||||
SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
|
SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
|
||||||
SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
|
SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
|
||||||
DAG.getVTList(ValueVTs), Ops, 2);
|
DAG.getVTList(ValueVTs), Ops);
|
||||||
|
|
||||||
// Modified the sum result - switch anything that used the old sum to use
|
// Modified the sum result - switch anything that used the old sum to use
|
||||||
// the new one.
|
// the new one.
|
||||||
@ -1299,9 +1299,9 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
|
|||||||
// Emit this X << 1 as X+X.
|
// Emit this X << 1 as X+X.
|
||||||
SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
|
SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
|
||||||
SDValue LoOps[2] = { InL, InL };
|
SDValue LoOps[2] = { InL, InL };
|
||||||
Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2);
|
Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps);
|
||||||
SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
|
SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
|
||||||
Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3);
|
Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
|
||||||
} else {
|
} else {
|
||||||
Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
|
Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
|
||||||
Hi = DAG.getNode(ISD::OR, DL, NVT,
|
Hi = DAG.getNode(ISD::OR, DL, NVT,
|
||||||
@ -1550,20 +1550,20 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
|
|||||||
if (hasCarry) {
|
if (hasCarry) {
|
||||||
SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
|
SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
|
||||||
if (N->getOpcode() == ISD::ADD) {
|
if (N->getOpcode() == ISD::ADD) {
|
||||||
Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
|
Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
|
||||||
HiOps[2] = Lo.getValue(1);
|
HiOps[2] = Lo.getValue(1);
|
||||||
Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
|
Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
|
||||||
} else {
|
} else {
|
||||||
Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
|
Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
|
||||||
HiOps[2] = Lo.getValue(1);
|
HiOps[2] = Lo.getValue(1);
|
||||||
Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
|
Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
|
||||||
}
|
}
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (N->getOpcode() == ISD::ADD) {
|
if (N->getOpcode() == ISD::ADD) {
|
||||||
Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
|
Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
|
||||||
Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
|
Hi = DAG.getNode(ISD::ADD, dl, NVT, ArrayRef<SDValue>(HiOps, 2));
|
||||||
SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
|
SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
|
||||||
ISD::SETULT);
|
ISD::SETULT);
|
||||||
SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
|
SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
|
||||||
@ -1575,8 +1575,8 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
|
|||||||
DAG.getConstant(1, NVT), Carry1);
|
DAG.getConstant(1, NVT), Carry1);
|
||||||
Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
|
Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
|
||||||
} else {
|
} else {
|
||||||
Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
|
Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
|
||||||
Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
|
Hi = DAG.getNode(ISD::SUB, dl, NVT, ArrayRef<SDValue>(HiOps, 2));
|
||||||
SDValue Cmp =
|
SDValue Cmp =
|
||||||
DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
|
DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
|
||||||
LoOps[0], LoOps[1], ISD::SETULT);
|
LoOps[0], LoOps[1], ISD::SETULT);
|
||||||
@ -1599,13 +1599,13 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
|
|||||||
SDValue HiOps[3] = { LHSH, RHSH };
|
SDValue HiOps[3] = { LHSH, RHSH };
|
||||||
|
|
||||||
if (N->getOpcode() == ISD::ADDC) {
|
if (N->getOpcode() == ISD::ADDC) {
|
||||||
Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
|
Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
|
||||||
HiOps[2] = Lo.getValue(1);
|
HiOps[2] = Lo.getValue(1);
|
||||||
Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
|
Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
|
||||||
} else {
|
} else {
|
||||||
Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
|
Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
|
||||||
HiOps[2] = Lo.getValue(1);
|
HiOps[2] = Lo.getValue(1);
|
||||||
Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
|
Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Legalized the flag result - switch anything that used the old flag to
|
// Legalized the flag result - switch anything that used the old flag to
|
||||||
@ -1624,9 +1624,9 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
|
|||||||
SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
|
SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
|
||||||
SDValue HiOps[3] = { LHSH, RHSH };
|
SDValue HiOps[3] = { LHSH, RHSH };
|
||||||
|
|
||||||
Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
|
Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
|
||||||
HiOps[2] = Lo.getValue(1);
|
HiOps[2] = Lo.getValue(1);
|
||||||
Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
|
Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
|
||||||
|
|
||||||
// Legalized the flag result - switch anything that used the old flag to
|
// Legalized the flag result - switch anything that used the old flag to
|
||||||
// use the new one.
|
// use the new one.
|
||||||
@ -2066,7 +2066,7 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
|
|||||||
ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
|
ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
|
||||||
|
|
||||||
SDValue Ops[] = { LHSL, LHSH, ShiftOp };
|
SDValue Ops[] = { LHSL, LHSH, ShiftOp };
|
||||||
Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
|
Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
|
||||||
Hi = Lo.getValue(1);
|
Hi = Lo.getValue(1);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@ -2859,7 +2859,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
|
|||||||
Ops.push_back(Op);
|
Ops.push_back(Op);
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -2906,7 +2906,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
|
|||||||
Ops.push_back(Op);
|
Ops.push_back(Op);
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
|
SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
|
||||||
@ -2954,7 +2954,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
|
SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
|
||||||
@ -3010,6 +3010,5 @@ SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0),
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), NewOps);
|
||||||
&NewOps[0], NewOps.size());
|
|
||||||
}
|
}
|
||||||
|
@ -354,7 +354,8 @@ SDValue DAGTypeLegalizer::ExpandOp_BITCAST(SDNode *N) {
|
|||||||
SmallVector<SDValue, 8> Ops;
|
SmallVector<SDValue, 8> Ops;
|
||||||
IntegerToVector(N->getOperand(0), NumElts, Ops, NVT.getVectorElementType());
|
IntegerToVector(N->getOperand(0), NumElts, Ops, NVT.getVectorElementType());
|
||||||
|
|
||||||
SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], NumElts);
|
SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT,
|
||||||
|
ArrayRef<SDValue>(&Ops[0], NumElts));
|
||||||
return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), Vec);
|
return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), Vec);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -390,7 +391,7 @@ SDValue DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) {
|
|||||||
SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
|
SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
|
||||||
EVT::getVectorVT(*DAG.getContext(),
|
EVT::getVectorVT(*DAG.getContext(),
|
||||||
NewVT, NewElts.size()),
|
NewVT, NewElts.size()),
|
||||||
&NewElts[0], NewElts.size());
|
NewElts);
|
||||||
|
|
||||||
// Convert the new vector to the old vector type.
|
// Convert the new vector to the old vector type.
|
||||||
return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec);
|
return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec);
|
||||||
@ -449,7 +450,7 @@ SDValue DAGTypeLegalizer::ExpandOp_SCALAR_TO_VECTOR(SDNode *N) {
|
|||||||
SDValue UndefVal = DAG.getUNDEF(Ops[0].getValueType());
|
SDValue UndefVal = DAG.getUNDEF(Ops[0].getValueType());
|
||||||
for (unsigned i = 1; i < NumElts; ++i)
|
for (unsigned i = 1; i < NumElts; ++i)
|
||||||
Ops[i] = UndefVal;
|
Ops[i] = UndefVal;
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {
|
SDValue DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {
|
||||||
|
@ -343,7 +343,7 @@ SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
|
|||||||
Operands[j] = Op.getOperand(j);
|
Operands[j] = Op.getOperand(j);
|
||||||
}
|
}
|
||||||
|
|
||||||
Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size());
|
Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands);
|
||||||
|
|
||||||
return DAG.getNode(ISD::BITCAST, dl, VT, Op);
|
return DAG.getNode(ISD::BITCAST, dl, VT, Op);
|
||||||
}
|
}
|
||||||
@ -377,8 +377,7 @@ SDValue VectorLegalizer::PromoteVectorOpINT_TO_FP(SDValue Op) {
|
|||||||
Operands[j] = Op.getOperand(j);
|
Operands[j] = Op.getOperand(j);
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), &Operands[0],
|
return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
|
||||||
Operands.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// For FP_TO_INT we promote the result type to a vector type with wider
|
// For FP_TO_INT we promote the result type to a vector type with wider
|
||||||
@ -546,10 +545,9 @@ SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
|
||||||
&LoadChains[0], LoadChains.size());
|
|
||||||
SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
|
SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
|
||||||
Op.getNode()->getValueType(0), &Vals[0], Vals.size());
|
Op.getNode()->getValueType(0), Vals);
|
||||||
|
|
||||||
AddLegalizedOperand(Op.getValue(0), Value);
|
AddLegalizedOperand(Op.getValue(0), Value);
|
||||||
AddLegalizedOperand(Op.getValue(1), NewChain);
|
AddLegalizedOperand(Op.getValue(1), NewChain);
|
||||||
@ -603,8 +601,7 @@ SDValue VectorLegalizer::ExpandStore(SDValue Op) {
|
|||||||
|
|
||||||
Stores.push_back(Store);
|
Stores.push_back(Store);
|
||||||
}
|
}
|
||||||
SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
|
||||||
&Stores[0], Stores.size());
|
|
||||||
AddLegalizedOperand(Op, TF);
|
AddLegalizedOperand(Op, TF);
|
||||||
return TF;
|
return TF;
|
||||||
}
|
}
|
||||||
@ -648,7 +645,7 @@ SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
|
|||||||
|
|
||||||
// Broadcast the mask so that the entire vector is all-one or all zero.
|
// Broadcast the mask so that the entire vector is all-one or all zero.
|
||||||
SmallVector<SDValue, 8> Ops(NumElem, Mask);
|
SmallVector<SDValue, 8> Ops(NumElem, Mask);
|
||||||
Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, &Ops[0], Ops.size());
|
Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops);
|
||||||
|
|
||||||
// Bitcast the operands to be the same type as the mask.
|
// Bitcast the operands to be the same type as the mask.
|
||||||
// This is needed when we select between FP types because
|
// This is needed when we select between FP types because
|
||||||
@ -803,7 +800,7 @@ SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
|
|||||||
(EltVT.getSizeInBits()), EltVT),
|
(EltVT.getSizeInBits()), EltVT),
|
||||||
DAG.getConstant(0, EltVT));
|
DAG.getConstant(0, EltVT));
|
||||||
}
|
}
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
@ -437,13 +437,11 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
|
|||||||
assert(N->getValueType(0).getVectorNumElements() == 1 &&
|
assert(N->getValueType(0).getVectorNumElements() == 1 &&
|
||||||
"Unexected vector type!");
|
"Unexected vector type!");
|
||||||
SDValue Elt = GetScalarizedVector(N->getOperand(0));
|
SDValue Elt = GetScalarizedVector(N->getOperand(0));
|
||||||
SmallVector<SDValue, 1> Ops(1);
|
SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
|
||||||
Ops[0] = DAG.getNode(N->getOpcode(), SDLoc(N),
|
|
||||||
N->getValueType(0).getScalarType(), Elt);
|
N->getValueType(0).getScalarType(), Elt);
|
||||||
// Revectorize the result so the types line up with what the uses of this
|
// Revectorize the result so the types line up with what the uses of this
|
||||||
// expression expect.
|
// expression expect.
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0),
|
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
|
||||||
&Ops[0], 1);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
|
/// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
|
||||||
@ -452,8 +450,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
|
|||||||
SmallVector<SDValue, 8> Ops(N->getNumOperands());
|
SmallVector<SDValue, 8> Ops(N->getNumOperands());
|
||||||
for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
|
for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
|
||||||
Ops[i] = GetScalarizedVector(N->getOperand(i));
|
Ops[i] = GetScalarizedVector(N->getOperand(i));
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0),
|
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
|
||||||
&Ops[0], Ops.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
|
/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
|
||||||
@ -725,10 +722,10 @@ void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
|
|||||||
std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
|
std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
|
||||||
unsigned LoNumElts = LoVT.getVectorNumElements();
|
unsigned LoNumElts = LoVT.getVectorNumElements();
|
||||||
SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
|
SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
|
||||||
Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
|
Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
|
||||||
|
|
||||||
SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
|
SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
|
||||||
Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
|
Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
|
||||||
}
|
}
|
||||||
|
|
||||||
void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
|
void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
|
||||||
@ -746,10 +743,10 @@ void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
|
|||||||
std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
|
std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
|
||||||
|
|
||||||
SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
|
SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
|
||||||
Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
|
Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
|
||||||
|
|
||||||
SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
|
SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
|
||||||
Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
|
Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
|
||||||
}
|
}
|
||||||
|
|
||||||
void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
|
void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
|
||||||
@ -1093,7 +1090,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
|
|||||||
}
|
}
|
||||||
|
|
||||||
// Construct the Lo/Hi output using a BUILD_VECTOR.
|
// Construct the Lo/Hi output using a BUILD_VECTOR.
|
||||||
Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
|
Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
|
||||||
} else if (InputUsed[0] == -1U) {
|
} else if (InputUsed[0] == -1U) {
|
||||||
// No input vectors were used! The result is undefined.
|
// No input vectors were used! The result is undefined.
|
||||||
Output = DAG.getUNDEF(NewVT);
|
Output = DAG.getUNDEF(NewVT);
|
||||||
@ -1371,8 +1368,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0),
|
return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
|
||||||
&Elts[0], Elts.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue DAGTypeLegalizer::SplitVecOp_TRUNCATE(SDNode *N) {
|
SDValue DAGTypeLegalizer::SplitVecOp_TRUNCATE(SDNode *N) {
|
||||||
@ -1729,8 +1725,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
|
|||||||
while (SubConcatEnd < OpsToConcat)
|
while (SubConcatEnd < OpsToConcat)
|
||||||
SubConcatOps[SubConcatEnd++] = undefVec;
|
SubConcatOps[SubConcatEnd++] = undefVec;
|
||||||
ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
|
ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
|
||||||
NextVT, &SubConcatOps[0],
|
NextVT, SubConcatOps);
|
||||||
OpsToConcat);
|
|
||||||
ConcatEnd = SubConcatIdx + 1;
|
ConcatEnd = SubConcatIdx + 1;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -1749,7 +1744,8 @@ SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
|
|||||||
for (unsigned j = ConcatEnd; j < NumOps; ++j)
|
for (unsigned j = ConcatEnd; j < NumOps; ++j)
|
||||||
ConcatOps[j] = UndefVal;
|
ConcatOps[j] = UndefVal;
|
||||||
}
|
}
|
||||||
return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps);
|
return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
|
||||||
|
ArrayRef<SDValue>(&ConcatOps[0], NumOps));
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
|
SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
|
||||||
@ -1791,8 +1787,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
|
|||||||
SDValue UndefVal = DAG.getUNDEF(InVT);
|
SDValue UndefVal = DAG.getUNDEF(InVT);
|
||||||
for (unsigned i = 1; i != NumConcat; ++i)
|
for (unsigned i = 1; i != NumConcat; ++i)
|
||||||
Ops[i] = UndefVal;
|
Ops[i] = UndefVal;
|
||||||
SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT,
|
SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
|
||||||
&Ops[0], NumConcat);
|
|
||||||
if (N->getNumOperands() == 1)
|
if (N->getNumOperands() == 1)
|
||||||
return DAG.getNode(Opcode, DL, WidenVT, InVec);
|
return DAG.getNode(Opcode, DL, WidenVT, InVec);
|
||||||
return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
|
return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
|
||||||
@ -1827,7 +1822,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
|
|||||||
for (; i < WidenNumElts; ++i)
|
for (; i < WidenNumElts; ++i)
|
||||||
Ops[i] = UndefVal;
|
Ops[i] = UndefVal;
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts);
|
return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
|
SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
|
||||||
@ -1951,11 +1946,9 @@ SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
|
|||||||
|
|
||||||
SDValue NewVec;
|
SDValue NewVec;
|
||||||
if (InVT.isVector())
|
if (InVT.isVector())
|
||||||
NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
|
NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
|
||||||
NewInVT, &Ops[0], NewNumElts);
|
|
||||||
else
|
else
|
||||||
NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
|
NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
|
||||||
NewInVT, &Ops[0], NewNumElts);
|
|
||||||
return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
|
return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -1980,7 +1973,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
|
|||||||
assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
|
assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
|
||||||
NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
|
NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
|
SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
|
||||||
@ -2003,7 +1996,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
|
|||||||
Ops[i] = N->getOperand(i);
|
Ops[i] = N->getOperand(i);
|
||||||
for (unsigned i = NumOperands; i != NumConcat; ++i)
|
for (unsigned i = NumOperands; i != NumConcat; ++i)
|
||||||
Ops[i] = UndefVal;
|
Ops[i] = UndefVal;
|
||||||
return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
|
return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
InputWidened = true;
|
InputWidened = true;
|
||||||
@ -2049,7 +2042,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
|
|||||||
SDValue UndefVal = DAG.getUNDEF(EltVT);
|
SDValue UndefVal = DAG.getUNDEF(EltVT);
|
||||||
for (; Idx < WidenNumElts; ++Idx)
|
for (; Idx < WidenNumElts; ++Idx)
|
||||||
Ops[Idx] = UndefVal;
|
Ops[Idx] = UndefVal;
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
|
SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
|
||||||
@ -2094,7 +2087,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
|
|||||||
for (unsigned i = 1; i != NumConcat; ++i)
|
for (unsigned i = 1; i != NumConcat; ++i)
|
||||||
Ops[i] = UndefVal;
|
Ops[i] = UndefVal;
|
||||||
|
|
||||||
InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
|
InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
|
||||||
return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
|
return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
|
||||||
SatOp, CvtCode);
|
SatOp, CvtCode);
|
||||||
}
|
}
|
||||||
@ -2127,7 +2120,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
|
|||||||
for (; i < WidenNumElts; ++i)
|
for (; i < WidenNumElts; ++i)
|
||||||
Ops[i] = UndefVal;
|
Ops[i] = UndefVal;
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
|
SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
|
||||||
@ -2166,7 +2159,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
|
|||||||
SDValue UndefVal = DAG.getUNDEF(EltVT);
|
SDValue UndefVal = DAG.getUNDEF(EltVT);
|
||||||
for (; i < WidenNumElts; ++i)
|
for (; i < WidenNumElts; ++i)
|
||||||
Ops[i] = UndefVal;
|
Ops[i] = UndefVal;
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
|
SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
|
||||||
@ -2194,8 +2187,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
|
|||||||
if (LdChain.size() == 1)
|
if (LdChain.size() == 1)
|
||||||
NewChain = LdChain[0];
|
NewChain = LdChain[0];
|
||||||
else
|
else
|
||||||
NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other,
|
NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
|
||||||
&LdChain[0], LdChain.size());
|
|
||||||
|
|
||||||
// Modified the chain - switch anything that used the old chain to use
|
// Modified the chain - switch anything that used the old chain to use
|
||||||
// the new one.
|
// the new one.
|
||||||
@ -2401,7 +2393,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
|
|||||||
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
|
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
|
||||||
DAG.getConstant(i, TLI.getVectorIdxTy())));
|
DAG.getConstant(i, TLI.getVectorIdxTy())));
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
|
SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
|
||||||
@ -2450,7 +2442,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
|
|||||||
Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
|
Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
|
||||||
DAG.getConstant(j, TLI.getVectorIdxTy()));
|
DAG.getConstant(j, TLI.getVectorIdxTy()));
|
||||||
}
|
}
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
|
SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
|
||||||
@ -2479,8 +2471,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
|
|||||||
if (StChain.size() == 1)
|
if (StChain.size() == 1)
|
||||||
return StChain[0];
|
return StChain[0];
|
||||||
else
|
else
|
||||||
return DAG.getNode(ISD::TokenFactor, SDLoc(ST),
|
return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
|
||||||
MVT::Other,&StChain[0],StChain.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
|
SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
|
||||||
@ -2655,8 +2646,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
|
|||||||
ConcatOps[0] = LdOp;
|
ConcatOps[0] = LdOp;
|
||||||
for (unsigned i = 1; i != NumConcat; ++i)
|
for (unsigned i = 1; i != NumConcat; ++i)
|
||||||
ConcatOps[i] = UndefVal;
|
ConcatOps[i] = UndefVal;
|
||||||
return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0],
|
return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
|
||||||
NumConcat);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// Load vector by using multiple loads from largest vector to scalar
|
// Load vector by using multiple loads from largest vector to scalar
|
||||||
@ -2690,8 +2680,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
|
|||||||
Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
|
Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
|
||||||
size += L->getValueSizeInBits(0);
|
size += L->getValueSizeInBits(0);
|
||||||
}
|
}
|
||||||
L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0),
|
L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
|
||||||
&Loads[0], Loads.size());
|
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
|
L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
|
||||||
@ -2735,7 +2724,8 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
|
|||||||
if (NewLdTy != LdTy) {
|
if (NewLdTy != LdTy) {
|
||||||
// Create a larger vector
|
// Create a larger vector
|
||||||
ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
|
ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
|
||||||
&ConcatOps[Idx], End - Idx);
|
ArrayRef<SDValue>(&ConcatOps[Idx],
|
||||||
|
End - Idx));
|
||||||
Idx = End - 1;
|
Idx = End - 1;
|
||||||
LdTy = NewLdTy;
|
LdTy = NewLdTy;
|
||||||
}
|
}
|
||||||
@ -2744,7 +2734,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
|
|||||||
|
|
||||||
if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
|
if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
|
||||||
return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
|
return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
|
||||||
&ConcatOps[Idx], End - Idx);
|
ArrayRef<SDValue>(&ConcatOps[Idx], End - Idx));
|
||||||
|
|
||||||
// We need to fill the rest with undefs to build the vector
|
// We need to fill the rest with undefs to build the vector
|
||||||
unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
|
unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
|
||||||
@ -2757,7 +2747,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
|
|||||||
for (; i != NumOps; ++i)
|
for (; i != NumOps; ++i)
|
||||||
WidenOps[i] = UndefVal;
|
WidenOps[i] = UndefVal;
|
||||||
}
|
}
|
||||||
return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps);
|
return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue
|
SDValue
|
||||||
@ -2808,7 +2798,7 @@ DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
|
|||||||
for (; i != WidenNumElts; ++i)
|
for (; i != WidenNumElts; ++i)
|
||||||
Ops[i] = UndefVal;
|
Ops[i] = UndefVal;
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -2954,7 +2944,7 @@ SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
|
|||||||
for (unsigned i = 1; i != NumConcat; ++i)
|
for (unsigned i = 1; i != NumConcat; ++i)
|
||||||
Ops[i] = UndefVal;
|
Ops[i] = UndefVal;
|
||||||
|
|
||||||
return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
|
return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
|
if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
|
||||||
@ -2973,5 +2963,5 @@ SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
|
|||||||
SDValue UndefVal = DAG.getUNDEF(EltVT);
|
SDValue UndefVal = DAG.getUNDEF(EltVT);
|
||||||
for ( ; Idx < WidenNumElts; ++Idx)
|
for ( ; Idx < WidenNumElts; ++Idx)
|
||||||
Ops[Idx] = UndefVal;
|
Ops[Idx] = UndefVal;
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);
|
||||||
}
|
}
|
||||||
|
@ -1063,7 +1063,7 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, EVT VT, bool isT,
|
|||||||
|
|
||||||
SDValue Result = getNode(ISD::BITCAST, SDLoc(), VT,
|
SDValue Result = getNode(ISD::BITCAST, SDLoc(), VT,
|
||||||
getNode(ISD::BUILD_VECTOR, SDLoc(), ViaVecVT,
|
getNode(ISD::BUILD_VECTOR, SDLoc(), ViaVecVT,
|
||||||
&Ops[0], Ops.size()));
|
Ops));
|
||||||
return Result;
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1090,7 +1090,7 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, EVT VT, bool isT,
|
|||||||
if (VT.isVector()) {
|
if (VT.isVector()) {
|
||||||
SmallVector<SDValue, 8> Ops;
|
SmallVector<SDValue, 8> Ops;
|
||||||
Ops.assign(VT.getVectorNumElements(), Result);
|
Ops.assign(VT.getVectorNumElements(), Result);
|
||||||
Result = getNode(ISD::BUILD_VECTOR, SDLoc(), VT, &Ops[0], Ops.size());
|
Result = getNode(ISD::BUILD_VECTOR, SDLoc(), VT, Ops);
|
||||||
}
|
}
|
||||||
return Result;
|
return Result;
|
||||||
}
|
}
|
||||||
@ -1133,7 +1133,7 @@ SDValue SelectionDAG::getConstantFP(const ConstantFP& V, EVT VT, bool isTarget){
|
|||||||
SmallVector<SDValue, 8> Ops;
|
SmallVector<SDValue, 8> Ops;
|
||||||
Ops.assign(VT.getVectorNumElements(), Result);
|
Ops.assign(VT.getVectorNumElements(), Result);
|
||||||
// FIXME SDLoc info might be appropriate here
|
// FIXME SDLoc info might be appropriate here
|
||||||
Result = getNode(ISD::BUILD_VECTOR, SDLoc(), VT, &Ops[0], Ops.size());
|
Result = getNode(ISD::BUILD_VECTOR, SDLoc(), VT, Ops);
|
||||||
}
|
}
|
||||||
return Result;
|
return Result;
|
||||||
}
|
}
|
||||||
@ -2926,8 +2926,7 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, EVT VT,
|
|||||||
return Outputs.back();
|
return Outputs.back();
|
||||||
|
|
||||||
// Otherwise build a big vector out of the scalar elements we generated.
|
// Otherwise build a big vector out of the scalar elements we generated.
|
||||||
return getNode(ISD::BUILD_VECTOR, SDLoc(), VT, Outputs.data(),
|
return getNode(ISD::BUILD_VECTOR, SDLoc(), VT, Outputs);
|
||||||
Outputs.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
|
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
|
||||||
@ -2957,7 +2956,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
|
|||||||
SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(),
|
SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(),
|
||||||
N1.getNode()->op_end());
|
N1.getNode()->op_end());
|
||||||
Elts.append(N2.getNode()->op_begin(), N2.getNode()->op_end());
|
Elts.append(N2.getNode()->op_begin(), N2.getNode()->op_end());
|
||||||
return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
|
return getNode(ISD::BUILD_VECTOR, DL, VT, Elts);
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case ISD::AND:
|
case ISD::AND:
|
||||||
@ -3426,7 +3425,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT,
|
|||||||
N1.getNode()->op_end());
|
N1.getNode()->op_end());
|
||||||
Elts.append(N2.getNode()->op_begin(), N2.getNode()->op_end());
|
Elts.append(N2.getNode()->op_begin(), N2.getNode()->op_end());
|
||||||
Elts.append(N3.getNode()->op_begin(), N3.getNode()->op_end());
|
Elts.append(N3.getNode()->op_begin(), N3.getNode()->op_end());
|
||||||
return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
|
return getNode(ISD::BUILD_VECTOR, DL, VT, Elts);
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case ISD::SETCC: {
|
case ISD::SETCC: {
|
||||||
@ -3507,14 +3506,14 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT,
|
|||||||
SDValue N1, SDValue N2, SDValue N3,
|
SDValue N1, SDValue N2, SDValue N3,
|
||||||
SDValue N4) {
|
SDValue N4) {
|
||||||
SDValue Ops[] = { N1, N2, N3, N4 };
|
SDValue Ops[] = { N1, N2, N3, N4 };
|
||||||
return getNode(Opcode, DL, VT, Ops, 4);
|
return getNode(Opcode, DL, VT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT,
|
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT,
|
||||||
SDValue N1, SDValue N2, SDValue N3,
|
SDValue N1, SDValue N2, SDValue N3,
|
||||||
SDValue N4, SDValue N5) {
|
SDValue N4, SDValue N5) {
|
||||||
SDValue Ops[] = { N1, N2, N3, N4, N5 };
|
SDValue Ops[] = { N1, N2, N3, N4, N5 };
|
||||||
return getNode(Opcode, DL, VT, Ops, 5);
|
return getNode(Opcode, DL, VT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
/// getStackArgumentTokenFactor - Compute a TokenFactor to force all
|
/// getStackArgumentTokenFactor - Compute a TokenFactor to force all
|
||||||
@ -3536,8 +3535,7 @@ SDValue SelectionDAG::getStackArgumentTokenFactor(SDValue Chain) {
|
|||||||
ArgChains.push_back(SDValue(L, 1));
|
ArgChains.push_back(SDValue(L, 1));
|
||||||
|
|
||||||
// Build a tokenfactor for all the chains.
|
// Build a tokenfactor for all the chains.
|
||||||
return getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other,
|
return getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
|
||||||
&ArgChains[0], ArgChains.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/// getMemsetValue - Vectorized representation of the memset value
|
/// getMemsetValue - Vectorized representation of the memset value
|
||||||
@ -3858,8 +3856,7 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, SDLoc dl,
|
|||||||
Size -= VTSize;
|
Size -= VTSize;
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
|
||||||
&OutChains[0], OutChains.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, SDLoc dl,
|
static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, SDLoc dl,
|
||||||
@ -3924,8 +3921,7 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, SDLoc dl,
|
|||||||
LoadChains.push_back(Value.getValue(1));
|
LoadChains.push_back(Value.getValue(1));
|
||||||
SrcOff += VTSize;
|
SrcOff += VTSize;
|
||||||
}
|
}
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
|
||||||
&LoadChains[0], LoadChains.size());
|
|
||||||
OutChains.clear();
|
OutChains.clear();
|
||||||
for (unsigned i = 0; i < NumMemOps; i++) {
|
for (unsigned i = 0; i < NumMemOps; i++) {
|
||||||
EVT VT = MemOps[i];
|
EVT VT = MemOps[i];
|
||||||
@ -3939,8 +3935,7 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, SDLoc dl,
|
|||||||
DstOff += VTSize;
|
DstOff += VTSize;
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
|
||||||
&OutChains[0], OutChains.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/// \brief Lower the call to 'memset' intrinsic function into a series of store
|
/// \brief Lower the call to 'memset' intrinsic function into a series of store
|
||||||
@ -4041,8 +4036,7 @@ static SDValue getMemsetStores(SelectionDAG &DAG, SDLoc dl,
|
|||||||
Size -= VTSize;
|
Size -= VTSize;
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
|
||||||
&OutChains[0], OutChains.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue SelectionDAG::getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst,
|
SDValue SelectionDAG::getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst,
|
||||||
@ -4410,7 +4404,7 @@ SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps,
|
|||||||
for (unsigned i = 0; i < NumOps; ++i)
|
for (unsigned i = 0; i < NumOps; ++i)
|
||||||
VTs.push_back(Ops[i].getValueType());
|
VTs.push_back(Ops[i].getValueType());
|
||||||
return getNode(ISD::MERGE_VALUES, dl, getVTList(VTs),
|
return getNode(ISD::MERGE_VALUES, dl, getVTList(VTs),
|
||||||
Ops, NumOps);
|
ArrayRef<SDValue>(Ops, NumOps));
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue
|
SDValue
|
||||||
@ -4798,7 +4792,7 @@ SDValue SelectionDAG::getVAArg(EVT VT, SDLoc dl,
|
|||||||
SDValue SV,
|
SDValue SV,
|
||||||
unsigned Align) {
|
unsigned Align) {
|
||||||
SDValue Ops[] = { Chain, Ptr, SV, getTargetConstant(Align, MVT::i32) };
|
SDValue Ops[] = { Chain, Ptr, SV, getTargetConstant(Align, MVT::i32) };
|
||||||
return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 4);
|
return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT,
|
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT,
|
||||||
@ -4814,11 +4808,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT,
|
|||||||
// Copy from an SDUse array into an SDValue array for use with
|
// Copy from an SDUse array into an SDValue array for use with
|
||||||
// the regular getNode logic.
|
// the regular getNode logic.
|
||||||
SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps);
|
SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps);
|
||||||
return getNode(Opcode, DL, VT, &NewOps[0], NumOps);
|
return getNode(Opcode, DL, VT, NewOps);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT,
|
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT,
|
||||||
const SDValue *Ops, unsigned NumOps) {
|
ArrayRef<SDValue> Ops) {
|
||||||
|
unsigned NumOps = Ops.size();
|
||||||
switch (NumOps) {
|
switch (NumOps) {
|
||||||
case 0: return getNode(Opcode, DL, VT);
|
case 0: return getNode(Opcode, DL, VT);
|
||||||
case 1: return getNode(Opcode, DL, VT, Ops[0]);
|
case 1: return getNode(Opcode, DL, VT, Ops[0]);
|
||||||
@ -4853,18 +4848,18 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT,
|
|||||||
|
|
||||||
if (VT != MVT::Glue) {
|
if (VT != MVT::Glue) {
|
||||||
FoldingSetNodeID ID;
|
FoldingSetNodeID ID;
|
||||||
AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps);
|
AddNodeIDNode(ID, Opcode, VTs, Ops.data(), NumOps);
|
||||||
void *IP = nullptr;
|
void *IP = nullptr;
|
||||||
|
|
||||||
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
|
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
|
||||||
return SDValue(E, 0);
|
return SDValue(E, 0);
|
||||||
|
|
||||||
N = new (NodeAllocator) SDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(),
|
N = new (NodeAllocator) SDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(),
|
||||||
VTs, Ops, NumOps);
|
VTs, Ops.data(), NumOps);
|
||||||
CSEMap.InsertNode(N, IP);
|
CSEMap.InsertNode(N, IP);
|
||||||
} else {
|
} else {
|
||||||
N = new (NodeAllocator) SDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(),
|
N = new (NodeAllocator) SDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(),
|
||||||
VTs, Ops, NumOps);
|
VTs, Ops.data(), NumOps);
|
||||||
}
|
}
|
||||||
|
|
||||||
AllNodes.push_back(N);
|
AllNodes.push_back(N);
|
||||||
@ -4875,16 +4870,14 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT,
|
|||||||
}
|
}
|
||||||
|
|
||||||
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL,
|
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL,
|
||||||
ArrayRef<EVT> ResultTys,
|
ArrayRef<EVT> ResultTys, ArrayRef<SDValue> Ops) {
|
||||||
const SDValue *Ops, unsigned NumOps) {
|
return getNode(Opcode, DL, getVTList(ResultTys), Ops);
|
||||||
return getNode(Opcode, DL, getVTList(ResultTys),
|
|
||||||
Ops, NumOps);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
|
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
|
||||||
const SDValue *Ops, unsigned NumOps) {
|
ArrayRef<SDValue> Ops) {
|
||||||
if (VTList.NumVTs == 1)
|
if (VTList.NumVTs == 1)
|
||||||
return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps);
|
return getNode(Opcode, DL, VTList.VTs[0], Ops);
|
||||||
|
|
||||||
#if 0
|
#if 0
|
||||||
switch (Opcode) {
|
switch (Opcode) {
|
||||||
@ -4911,9 +4904,10 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
|
|||||||
|
|
||||||
// Memoize the node unless it returns a flag.
|
// Memoize the node unless it returns a flag.
|
||||||
SDNode *N;
|
SDNode *N;
|
||||||
|
unsigned NumOps = Ops.size();
|
||||||
if (VTList.VTs[VTList.NumVTs-1] != MVT::Glue) {
|
if (VTList.VTs[VTList.NumVTs-1] != MVT::Glue) {
|
||||||
FoldingSetNodeID ID;
|
FoldingSetNodeID ID;
|
||||||
AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
|
AddNodeIDNode(ID, Opcode, VTList, Ops.data(), NumOps);
|
||||||
void *IP = nullptr;
|
void *IP = nullptr;
|
||||||
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
|
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
|
||||||
return SDValue(E, 0);
|
return SDValue(E, 0);
|
||||||
@ -4931,7 +4925,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
|
|||||||
Ops[1], Ops[2]);
|
Ops[1], Ops[2]);
|
||||||
} else {
|
} else {
|
||||||
N = new (NodeAllocator) SDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(),
|
N = new (NodeAllocator) SDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(),
|
||||||
VTList, Ops, NumOps);
|
VTList, Ops.data(), NumOps);
|
||||||
}
|
}
|
||||||
CSEMap.InsertNode(N, IP);
|
CSEMap.InsertNode(N, IP);
|
||||||
} else {
|
} else {
|
||||||
@ -4948,7 +4942,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
|
|||||||
Ops[1], Ops[2]);
|
Ops[1], Ops[2]);
|
||||||
} else {
|
} else {
|
||||||
N = new (NodeAllocator) SDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(),
|
N = new (NodeAllocator) SDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(),
|
||||||
VTList, Ops, NumOps);
|
VTList, Ops.data(), NumOps);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
AllNodes.push_back(N);
|
AllNodes.push_back(N);
|
||||||
@ -4959,39 +4953,39 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
|
|||||||
}
|
}
|
||||||
|
|
||||||
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList) {
|
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList) {
|
||||||
return getNode(Opcode, DL, VTList, nullptr, 0);
|
return getNode(Opcode, DL, VTList, ArrayRef<SDValue>());
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
|
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
|
||||||
SDValue N1) {
|
SDValue N1) {
|
||||||
SDValue Ops[] = { N1 };
|
SDValue Ops[] = { N1 };
|
||||||
return getNode(Opcode, DL, VTList, Ops, 1);
|
return getNode(Opcode, DL, VTList, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
|
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
|
||||||
SDValue N1, SDValue N2) {
|
SDValue N1, SDValue N2) {
|
||||||
SDValue Ops[] = { N1, N2 };
|
SDValue Ops[] = { N1, N2 };
|
||||||
return getNode(Opcode, DL, VTList, Ops, 2);
|
return getNode(Opcode, DL, VTList, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
|
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
|
||||||
SDValue N1, SDValue N2, SDValue N3) {
|
SDValue N1, SDValue N2, SDValue N3) {
|
||||||
SDValue Ops[] = { N1, N2, N3 };
|
SDValue Ops[] = { N1, N2, N3 };
|
||||||
return getNode(Opcode, DL, VTList, Ops, 3);
|
return getNode(Opcode, DL, VTList, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
|
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
|
||||||
SDValue N1, SDValue N2, SDValue N3,
|
SDValue N1, SDValue N2, SDValue N3,
|
||||||
SDValue N4) {
|
SDValue N4) {
|
||||||
SDValue Ops[] = { N1, N2, N3, N4 };
|
SDValue Ops[] = { N1, N2, N3, N4 };
|
||||||
return getNode(Opcode, DL, VTList, Ops, 4);
|
return getNode(Opcode, DL, VTList, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
|
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
|
||||||
SDValue N1, SDValue N2, SDValue N3,
|
SDValue N1, SDValue N2, SDValue N3,
|
||||||
SDValue N4, SDValue N5) {
|
SDValue N4, SDValue N5) {
|
||||||
SDValue Ops[] = { N1, N2, N3, N4, N5 };
|
SDValue Ops[] = { N1, N2, N3, N4, N5 };
|
||||||
return getNode(Opcode, DL, VTList, Ops, 5);
|
return getNode(Opcode, DL, VTList, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDVTList SelectionDAG::getVTList(EVT VT) {
|
SDVTList SelectionDAG::getVTList(EVT VT) {
|
||||||
@ -6316,12 +6310,10 @@ SDValue SelectionDAG::UnrollVectorOp(SDNode *N, unsigned ResNE) {
|
|||||||
|
|
||||||
switch (N->getOpcode()) {
|
switch (N->getOpcode()) {
|
||||||
default:
|
default:
|
||||||
Scalars.push_back(getNode(N->getOpcode(), dl, EltVT,
|
Scalars.push_back(getNode(N->getOpcode(), dl, EltVT, Operands));
|
||||||
&Operands[0], Operands.size()));
|
|
||||||
break;
|
break;
|
||||||
case ISD::VSELECT:
|
case ISD::VSELECT:
|
||||||
Scalars.push_back(getNode(ISD::SELECT, dl, EltVT,
|
Scalars.push_back(getNode(ISD::SELECT, dl, EltVT, Operands));
|
||||||
&Operands[0], Operands.size()));
|
|
||||||
break;
|
break;
|
||||||
case ISD::SHL:
|
case ISD::SHL:
|
||||||
case ISD::SRA:
|
case ISD::SRA:
|
||||||
@ -6346,8 +6338,7 @@ SDValue SelectionDAG::UnrollVectorOp(SDNode *N, unsigned ResNE) {
|
|||||||
Scalars.push_back(getUNDEF(EltVT));
|
Scalars.push_back(getUNDEF(EltVT));
|
||||||
|
|
||||||
return getNode(ISD::BUILD_VECTOR, dl,
|
return getNode(ISD::BUILD_VECTOR, dl,
|
||||||
EVT::getVectorVT(*getContext(), EltVT, ResNE),
|
EVT::getVectorVT(*getContext(), EltVT, ResNE), Scalars);
|
||||||
&Scalars[0], Scalars.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -277,9 +277,9 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
|
|||||||
|
|
||||||
// Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
|
// Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
|
||||||
// intermediate operands.
|
// intermediate operands.
|
||||||
Val = DAG.getNode(IntermediateVT.isVector() ?
|
Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
|
||||||
ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
|
: ISD::BUILD_VECTOR,
|
||||||
ValueVT, &Ops[0], NumIntermediates);
|
DL, ValueVT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
// There is now one part, held in Val. Correct it to match ValueVT.
|
// There is now one part, held in Val. Correct it to match ValueVT.
|
||||||
@ -496,7 +496,7 @@ static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
|
|||||||
e = PartVT.getVectorNumElements(); i != e; ++i)
|
e = PartVT.getVectorNumElements(); i != e; ++i)
|
||||||
Ops.push_back(DAG.getUNDEF(ElementVT));
|
Ops.push_back(DAG.getUNDEF(ElementVT));
|
||||||
|
|
||||||
Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
|
Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
|
||||||
|
|
||||||
// FIXME: Use CONCAT for 2x -> 4x.
|
// FIXME: Use CONCAT for 2x -> 4x.
|
||||||
|
|
||||||
@ -753,9 +753,7 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
|
|||||||
Parts.clear();
|
Parts.clear();
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ISD::MERGE_VALUES, dl,
|
return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
|
||||||
DAG.getVTList(ValueVTs),
|
|
||||||
&Values[0], ValueVTs.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
|
/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
|
||||||
@ -809,7 +807,7 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
|
|||||||
// = op c3, ..., f2
|
// = op c3, ..., f2
|
||||||
Chain = Chains[NumRegs-1];
|
Chain = Chains[NumRegs-1];
|
||||||
else
|
else
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
|
||||||
}
|
}
|
||||||
|
|
||||||
/// AddInlineAsmOperands - Add this value to the specified inlineasm node
|
/// AddInlineAsmOperands - Add this value to the specified inlineasm node
|
||||||
@ -911,7 +909,7 @@ SDValue SelectionDAGBuilder::getRoot() {
|
|||||||
|
|
||||||
// Otherwise, we have to make a token factor node.
|
// Otherwise, we have to make a token factor node.
|
||||||
SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
|
SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
|
||||||
&PendingLoads[0], PendingLoads.size());
|
PendingLoads);
|
||||||
PendingLoads.clear();
|
PendingLoads.clear();
|
||||||
DAG.setRoot(Root);
|
DAG.setRoot(Root);
|
||||||
return Root;
|
return Root;
|
||||||
@ -941,8 +939,7 @@ SDValue SelectionDAGBuilder::getControlRoot() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
|
Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
|
||||||
&PendingExports[0],
|
PendingExports);
|
||||||
PendingExports.size());
|
|
||||||
PendingExports.clear();
|
PendingExports.clear();
|
||||||
DAG.setRoot(Root);
|
DAG.setRoot(Root);
|
||||||
return Root;
|
return Root;
|
||||||
@ -1113,7 +1110,7 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
|
|||||||
if (isa<ArrayType>(CDS->getType()))
|
if (isa<ArrayType>(CDS->getType()))
|
||||||
return DAG.getMergeValues(&Ops[0], Ops.size(), getCurSDLoc());
|
return DAG.getMergeValues(&Ops[0], Ops.size(), getCurSDLoc());
|
||||||
return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
|
return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
|
||||||
VT, &Ops[0], Ops.size());
|
VT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
|
if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
|
||||||
@ -1165,8 +1162,7 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
// Create a BUILD_VECTOR node.
|
// Create a BUILD_VECTOR node.
|
||||||
return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
|
return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
|
||||||
VT, &Ops[0], Ops.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// If this is a static alloca, generate it as the frameindex instead of
|
// If this is a static alloca, generate it as the frameindex instead of
|
||||||
@ -1227,7 +1223,7 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
|
Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
|
||||||
MVT::Other, &Chains[0], NumValues);
|
MVT::Other, Chains);
|
||||||
} else if (I.getNumOperands() != 0) {
|
} else if (I.getNumOperands() != 0) {
|
||||||
SmallVector<EVT, 4> ValueVTs;
|
SmallVector<EVT, 4> ValueVTs;
|
||||||
ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs);
|
ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs);
|
||||||
@ -2063,8 +2059,7 @@ void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
|
|||||||
|
|
||||||
// Merge into one.
|
// Merge into one.
|
||||||
SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
|
SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
|
||||||
DAG.getVTList(ValueVTs),
|
DAG.getVTList(ValueVTs), Ops);
|
||||||
&Ops[0], 2);
|
|
||||||
setValue(&LP, Res);
|
setValue(&LP, Res);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -2896,8 +2891,7 @@ void SelectionDAGBuilder::visitSelect(const User &I) {
|
|||||||
FalseVal.getResNo() + i));
|
FalseVal.getResNo() + i));
|
||||||
|
|
||||||
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
|
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
|
||||||
DAG.getVTList(ValueVTs),
|
DAG.getVTList(ValueVTs), Values));
|
||||||
&Values[0], NumValues));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void SelectionDAGBuilder::visitTrunc(const User &I) {
|
void SelectionDAGBuilder::visitTrunc(const User &I) {
|
||||||
@ -3106,11 +3100,9 @@ void SelectionDAGBuilder::visitShuffleVector(const User &I) {
|
|||||||
MOps2[0] = Src2;
|
MOps2[0] = Src2;
|
||||||
|
|
||||||
Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
|
Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
|
||||||
getCurSDLoc(), VT,
|
getCurSDLoc(), VT, MOps1);
|
||||||
&MOps1[0], NumConcat);
|
|
||||||
Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
|
Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
|
||||||
getCurSDLoc(), VT,
|
getCurSDLoc(), VT, MOps2);
|
||||||
&MOps2[0], NumConcat);
|
|
||||||
|
|
||||||
// Readjust mask for new input vector length.
|
// Readjust mask for new input vector length.
|
||||||
SmallVector<int, 8> MappedOps;
|
SmallVector<int, 8> MappedOps;
|
||||||
@ -3228,8 +3220,7 @@ void SelectionDAGBuilder::visitShuffleVector(const User &I) {
|
|||||||
Ops.push_back(Res);
|
Ops.push_back(Res);
|
||||||
}
|
}
|
||||||
|
|
||||||
setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
|
setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
|
||||||
VT, &Ops[0], Ops.size()));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
|
void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
|
||||||
@ -3271,8 +3262,7 @@ void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
|
|||||||
SDValue(Agg.getNode(), Agg.getResNo() + i);
|
SDValue(Agg.getNode(), Agg.getResNo() + i);
|
||||||
|
|
||||||
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
|
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
|
||||||
DAG.getVTList(AggValueVTs),
|
DAG.getVTList(AggValueVTs), Values));
|
||||||
&Values[0], NumAggValues));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
|
void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
|
||||||
@ -3306,8 +3296,7 @@ void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
|
|||||||
SDValue(Agg.getNode(), Agg.getResNo() + i);
|
SDValue(Agg.getNode(), Agg.getResNo() + i);
|
||||||
|
|
||||||
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
|
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
|
||||||
DAG.getVTList(ValValueVTs),
|
DAG.getVTList(ValValueVTs), Values));
|
||||||
&Values[0], NumValValues));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
|
void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
|
||||||
@ -3429,8 +3418,7 @@ void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
|
|||||||
|
|
||||||
SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
|
SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
|
||||||
SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
|
SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
|
||||||
SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(),
|
SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
|
||||||
VTs, Ops, 3);
|
|
||||||
setValue(&I, DSA);
|
setValue(&I, DSA);
|
||||||
DAG.setRoot(DSA.getValue(1));
|
DAG.setRoot(DSA.getValue(1));
|
||||||
|
|
||||||
@ -3493,8 +3481,8 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
|
|||||||
// (MaxParallelChains should always remain as failsafe).
|
// (MaxParallelChains should always remain as failsafe).
|
||||||
if (ChainI == MaxParallelChains) {
|
if (ChainI == MaxParallelChains) {
|
||||||
assert(PendingLoads.empty() && "PendingLoads must be serialized first");
|
assert(PendingLoads.empty() && "PendingLoads must be serialized first");
|
||||||
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
|
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
|
||||||
MVT::Other, &Chains[0], ChainI);
|
ArrayRef<SDValue>(Chains.data(), ChainI));
|
||||||
Root = Chain;
|
Root = Chain;
|
||||||
ChainI = 0;
|
ChainI = 0;
|
||||||
}
|
}
|
||||||
@ -3511,8 +3499,8 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (!ConstantMemory) {
|
if (!ConstantMemory) {
|
||||||
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
|
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
|
||||||
MVT::Other, &Chains[0], ChainI);
|
ArrayRef<SDValue>(Chains.data(), ChainI));
|
||||||
if (isVolatile)
|
if (isVolatile)
|
||||||
DAG.setRoot(Chain);
|
DAG.setRoot(Chain);
|
||||||
else
|
else
|
||||||
@ -3520,8 +3508,7 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
|
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
|
||||||
DAG.getVTList(ValueVTs),
|
DAG.getVTList(ValueVTs), Values));
|
||||||
&Values[0], NumValues));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void SelectionDAGBuilder::visitStore(const StoreInst &I) {
|
void SelectionDAGBuilder::visitStore(const StoreInst &I) {
|
||||||
@ -3557,8 +3544,8 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
|
|||||||
for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
|
for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
|
||||||
// See visitLoad comments.
|
// See visitLoad comments.
|
||||||
if (ChainI == MaxParallelChains) {
|
if (ChainI == MaxParallelChains) {
|
||||||
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
|
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
|
||||||
MVT::Other, &Chains[0], ChainI);
|
ArrayRef<SDValue>(Chains.data(), ChainI));
|
||||||
Root = Chain;
|
Root = Chain;
|
||||||
ChainI = 0;
|
ChainI = 0;
|
||||||
}
|
}
|
||||||
@ -3571,8 +3558,8 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
|
|||||||
Chains[ChainI] = St;
|
Chains[ChainI] = St;
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
|
SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
|
||||||
MVT::Other, &Chains[0], ChainI);
|
ArrayRef<SDValue>(Chains.data(), ChainI));
|
||||||
DAG.setRoot(StoreNode);
|
DAG.setRoot(StoreNode);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -3597,7 +3584,7 @@ static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
|
|||||||
Ops[0] = Chain;
|
Ops[0] = Chain;
|
||||||
Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
|
Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
|
||||||
Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
|
Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
|
||||||
return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
|
return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
|
void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
|
||||||
@ -3689,7 +3676,7 @@ void SelectionDAGBuilder::visitFence(const FenceInst &I) {
|
|||||||
Ops[0] = getRoot();
|
Ops[0] = getRoot();
|
||||||
Ops[1] = DAG.getConstant(I.getOrdering(), TLI->getPointerTy());
|
Ops[1] = DAG.getConstant(I.getOrdering(), TLI->getPointerTy());
|
||||||
Ops[2] = DAG.getConstant(I.getSynchScope(), TLI->getPointerTy());
|
Ops[2] = DAG.getConstant(I.getSynchScope(), TLI->getPointerTy());
|
||||||
DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
|
DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
|
||||||
}
|
}
|
||||||
|
|
||||||
void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
|
void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
|
||||||
@ -3818,14 +3805,11 @@ void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
|
|||||||
Info.align, Info.vol,
|
Info.align, Info.vol,
|
||||||
Info.readMem, Info.writeMem);
|
Info.readMem, Info.writeMem);
|
||||||
} else if (!HasChain) {
|
} else if (!HasChain) {
|
||||||
Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(),
|
Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
|
||||||
VTs, &Ops[0], Ops.size());
|
|
||||||
} else if (!I.getType()->isVoidTy()) {
|
} else if (!I.getType()->isVoidTy()) {
|
||||||
Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(),
|
Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
|
||||||
VTs, &Ops[0], Ops.size());
|
|
||||||
} else {
|
} else {
|
||||||
Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(),
|
Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
|
||||||
VTs, &Ops[0], Ops.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
if (HasChain) {
|
if (HasChain) {
|
||||||
@ -4909,8 +4893,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
|
|||||||
Ops[0] = getRoot();
|
Ops[0] = getRoot();
|
||||||
Ops[1] = getValue(I.getArgOperand(0));
|
Ops[1] = getValue(I.getArgOperand(0));
|
||||||
SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
|
SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
|
||||||
DAG.getVTList(MVT::i32, MVT::Other),
|
DAG.getVTList(MVT::i32, MVT::Other), Ops);
|
||||||
Ops, 2);
|
|
||||||
setValue(&I, Op.getValue(0));
|
setValue(&I, Op.getValue(0));
|
||||||
DAG.setRoot(Op.getValue(1));
|
DAG.setRoot(Op.getValue(1));
|
||||||
return nullptr;
|
return nullptr;
|
||||||
@ -4971,7 +4954,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
|
|||||||
SDValue ShOps[2];
|
SDValue ShOps[2];
|
||||||
ShOps[0] = ShAmt;
|
ShOps[0] = ShAmt;
|
||||||
ShOps[1] = DAG.getConstant(0, MVT::i32);
|
ShOps[1] = DAG.getConstant(0, MVT::i32);
|
||||||
ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, &ShOps[0], 2);
|
ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
|
||||||
EVT DestVT = TLI->getValueType(I.getType());
|
EVT DestVT = TLI->getValueType(I.getType());
|
||||||
ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
|
ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
|
||||||
Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
|
Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
|
||||||
@ -5145,8 +5128,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
|
|||||||
case Intrinsic::readcyclecounter: {
|
case Intrinsic::readcyclecounter: {
|
||||||
SDValue Op = getRoot();
|
SDValue Op = getRoot();
|
||||||
Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
|
Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
|
||||||
DAG.getVTList(MVT::i64, MVT::Other),
|
DAG.getVTList(MVT::i64, MVT::Other), Op);
|
||||||
&Op, 1);
|
|
||||||
setValue(&I, Res);
|
setValue(&I, Res);
|
||||||
DAG.setRoot(Res.getValue(1));
|
DAG.setRoot(Res.getValue(1));
|
||||||
return nullptr;
|
return nullptr;
|
||||||
@ -5181,7 +5163,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
|
|||||||
case Intrinsic::stacksave: {
|
case Intrinsic::stacksave: {
|
||||||
SDValue Op = getRoot();
|
SDValue Op = getRoot();
|
||||||
Res = DAG.getNode(ISD::STACKSAVE, sdl,
|
Res = DAG.getNode(ISD::STACKSAVE, sdl,
|
||||||
DAG.getVTList(TLI->getPointerTy(), MVT::Other), &Op, 1);
|
DAG.getVTList(TLI->getPointerTy(), MVT::Other), Op);
|
||||||
setValue(&I, Res);
|
setValue(&I, Res);
|
||||||
DAG.setRoot(Res.getValue(1));
|
DAG.setRoot(Res.getValue(1));
|
||||||
return nullptr;
|
return nullptr;
|
||||||
@ -5250,7 +5232,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
|
|||||||
Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
|
Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
|
||||||
Ops[5] = DAG.getSrcValue(F);
|
Ops[5] = DAG.getSrcValue(F);
|
||||||
|
|
||||||
Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops, 6);
|
Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
|
||||||
|
|
||||||
DAG.setRoot(Res);
|
DAG.setRoot(Res);
|
||||||
return nullptr;
|
return nullptr;
|
||||||
@ -5373,7 +5355,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
|
|||||||
Ops[1] = DAG.getFrameIndex(FI, TLI->getPointerTy(), true);
|
Ops[1] = DAG.getFrameIndex(FI, TLI->getPointerTy(), true);
|
||||||
unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
|
unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
|
||||||
|
|
||||||
Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops, 2);
|
Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
|
||||||
DAG.setRoot(Res);
|
DAG.setRoot(Res);
|
||||||
}
|
}
|
||||||
return nullptr;
|
return nullptr;
|
||||||
@ -5550,13 +5532,12 @@ void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
|
|||||||
}
|
}
|
||||||
|
|
||||||
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
|
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
|
||||||
MVT::Other, &Chains[0], NumValues);
|
MVT::Other, Chains);
|
||||||
PendingLoads.push_back(Chain);
|
PendingLoads.push_back(Chain);
|
||||||
|
|
||||||
setValue(CS.getInstruction(),
|
setValue(CS.getInstruction(),
|
||||||
DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
|
DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
|
||||||
DAG.getVTList(RetTys),
|
DAG.getVTList(RetTys), Values));
|
||||||
&Values[0], Values.size()));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!Result.second.getNode()) {
|
if (!Result.second.getNode()) {
|
||||||
@ -6717,8 +6698,7 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
|
|||||||
if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
|
if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
|
||||||
|
|
||||||
Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
|
Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
|
||||||
DAG.getVTList(MVT::Other, MVT::Glue),
|
DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
|
||||||
&AsmNodeOperands[0], AsmNodeOperands.size());
|
|
||||||
Flag = Chain.getValue(1);
|
Flag = Chain.getValue(1);
|
||||||
|
|
||||||
// If this asm returns a register value, copy the result from that register
|
// If this asm returns a register value, copy the result from that register
|
||||||
@ -6781,8 +6761,7 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (!OutChains.empty())
|
if (!OutChains.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
|
||||||
&OutChains[0], OutChains.size());
|
|
||||||
|
|
||||||
DAG.setRoot(Chain);
|
DAG.setRoot(Chain);
|
||||||
}
|
}
|
||||||
@ -7285,8 +7264,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
|
|||||||
return std::make_pair(SDValue(), CLI.Chain);
|
return std::make_pair(SDValue(), CLI.Chain);
|
||||||
|
|
||||||
SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
|
SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
|
||||||
CLI.DAG.getVTList(RetTys),
|
CLI.DAG.getVTList(RetTys), ReturnValues);
|
||||||
&ReturnValues[0], ReturnValues.size());
|
|
||||||
return std::make_pair(Res, CLI.Chain);
|
return std::make_pair(Res, CLI.Chain);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1806,8 +1806,7 @@ SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
|
|||||||
SelectInlineAsmMemoryOperands(Ops);
|
SelectInlineAsmMemoryOperands(Ops);
|
||||||
|
|
||||||
EVT VTs[] = { MVT::Other, MVT::Glue };
|
EVT VTs[] = { MVT::Other, MVT::Glue };
|
||||||
SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
|
SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), VTs, Ops);
|
||||||
VTs, &Ops[0], Ops.size());
|
|
||||||
New->setNodeId(-1);
|
New->setNodeId(-1);
|
||||||
return New.getNode();
|
return New.getNode();
|
||||||
}
|
}
|
||||||
@ -2081,7 +2080,7 @@ HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
|
|||||||
if (InputChains.size() == 1)
|
if (InputChains.size() == 1)
|
||||||
return InputChains[0];
|
return InputChains[0];
|
||||||
return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
|
return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
|
||||||
MVT::Other, &InputChains[0], InputChains.size());
|
MVT::Other, InputChains);
|
||||||
}
|
}
|
||||||
|
|
||||||
/// MorphNode - Handle morphing a node in place for the selector.
|
/// MorphNode - Handle morphing a node in place for the selector.
|
||||||
|
@ -1294,8 +1294,7 @@ AArch64TargetLowering::SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG,
|
|||||||
FuncInfo->setVariadicGPRSize(GPRSaveSize);
|
FuncInfo->setVariadicGPRSize(GPRSaveSize);
|
||||||
|
|
||||||
if (!MemOps.empty()) {
|
if (!MemOps.empty()) {
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
|
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
|
||||||
MemOps.size());
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1488,8 +1487,7 @@ AArch64TargetLowering::LowerReturn(SDValue Chain,
|
|||||||
if (Flag.getNode())
|
if (Flag.getNode())
|
||||||
RetOps.push_back(Flag);
|
RetOps.push_back(Flag);
|
||||||
|
|
||||||
return DAG.getNode(AArch64ISD::Ret, dl, MVT::Other,
|
return DAG.getNode(AArch64ISD::Ret, dl, MVT::Other, RetOps);
|
||||||
&RetOps[0], RetOps.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned AArch64TargetLowering::getByValTypeAlignment(Type *Ty) const {
|
unsigned AArch64TargetLowering::getByValTypeAlignment(Type *Ty) const {
|
||||||
@ -1680,8 +1678,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
|
|||||||
// other. Combining them with this TokenFactor notes that fact for the rest of
|
// other. Combining them with this TokenFactor notes that fact for the rest of
|
||||||
// the backend.
|
// the backend.
|
||||||
if (!MemOpChains.empty())
|
if (!MemOpChains.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
|
||||||
&MemOpChains[0], MemOpChains.size());
|
|
||||||
|
|
||||||
// Most of the rest of the instructions need to be glued together; we don't
|
// Most of the rest of the instructions need to be glued together; we don't
|
||||||
// want assignments to actual registers used by a call to be rearranged by a
|
// want assignments to actual registers used by a call to be rearranged by a
|
||||||
@ -1751,10 +1748,10 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
|
|||||||
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
|
|
||||||
if (IsTailCall) {
|
if (IsTailCall) {
|
||||||
return DAG.getNode(AArch64ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
|
return DAG.getNode(AArch64ISD::TC_RETURN, dl, NodeTys, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
Chain = DAG.getNode(AArch64ISD::Call, dl, NodeTys, &Ops[0], Ops.size());
|
Chain = DAG.getNode(AArch64ISD::Call, dl, NodeTys, Ops);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
// Now we can reclaim the stack, just as well do it before working out where
|
// Now we can reclaim the stack, just as well do it before working out where
|
||||||
@ -1966,8 +1963,7 @@ SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
|
|||||||
}
|
}
|
||||||
|
|
||||||
// Build a tokenfactor for all the chains.
|
// Build a tokenfactor for all the chains.
|
||||||
return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other,
|
return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
|
||||||
&ArgChains[0], ArgChains.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static A64CC::CondCodes IntCCToA64CC(ISD::CondCode CC) {
|
static A64CC::CondCodes IntCCToA64CC(ISD::CondCode CC) {
|
||||||
@ -2592,8 +2588,7 @@ SDValue AArch64TargetLowering::LowerTLSDescCall(SDValue SymAddr,
|
|||||||
Ops.push_back(Glue);
|
Ops.push_back(Glue);
|
||||||
|
|
||||||
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
Chain = DAG.getNode(AArch64ISD::TLSDESCCALL, DL, NodeTys, &Ops[0],
|
Chain = DAG.getNode(AArch64ISD::TLSDESCCALL, DL, NodeTys, Ops);
|
||||||
Ops.size());
|
|
||||||
Glue = Chain.getValue(1);
|
Glue = Chain.getValue(1);
|
||||||
|
|
||||||
// After the call, the offset from TPIDR_EL0 is in X0, copy it out and pass it
|
// After the call, the offset from TPIDR_EL0 is in X0, copy it out and pass it
|
||||||
@ -3286,8 +3281,7 @@ AArch64TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
VROffsAddr, MachinePointerInfo(SV, 28),
|
VROffsAddr, MachinePointerInfo(SV, 28),
|
||||||
false, false, 0));
|
false, false, 0));
|
||||||
|
|
||||||
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
|
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
|
||||||
MemOps.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue
|
SDValue
|
||||||
@ -4822,7 +4816,7 @@ AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
|
|||||||
Ops.push_back(N);
|
Ops.push_back(N);
|
||||||
Ops.push_back(Op.getOperand(I));
|
Ops.push_back(Op.getOperand(I));
|
||||||
Ops.push_back(DAG.getConstant(I, MVT::i64));
|
Ops.push_back(DAG.getConstant(I, MVT::i64));
|
||||||
N = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, &Ops[0], 3);
|
N = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Ops);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return N;
|
return N;
|
||||||
|
@ -3440,8 +3440,7 @@ SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){
|
|||||||
return nullptr;
|
return nullptr;
|
||||||
|
|
||||||
SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
|
SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
|
||||||
CurDAG->getVTList(MVT::Other, MVT::Glue), &AsmNodeOperands[0],
|
CurDAG->getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
|
||||||
AsmNodeOperands.size());
|
|
||||||
New->setNodeId(-1);
|
New->setNodeId(-1);
|
||||||
return New.getNode();
|
return New.getNode();
|
||||||
}
|
}
|
||||||
|
@ -1552,7 +1552,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
|
SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
|
||||||
MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
|
MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
|
||||||
Ops, array_lengthof(Ops)));
|
Ops));
|
||||||
}
|
}
|
||||||
} else if (!isSibCall) {
|
} else if (!isSibCall) {
|
||||||
assert(VA.isMemLoc());
|
assert(VA.isMemLoc());
|
||||||
@ -1563,8 +1563,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (!MemOpChains.empty())
|
if (!MemOpChains.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
|
||||||
&MemOpChains[0], MemOpChains.size());
|
|
||||||
|
|
||||||
// Build a sequence of copy-to-reg nodes chained together with token chain
|
// Build a sequence of copy-to-reg nodes chained together with token chain
|
||||||
// and flag operands which copy the outgoing args into the appropriate regs.
|
// and flag operands which copy the outgoing args into the appropriate regs.
|
||||||
@ -1751,10 +1750,10 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
|
|
||||||
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
if (isTailCall)
|
if (isTailCall)
|
||||||
return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
|
return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
|
||||||
|
|
||||||
// Returns a chain and a flag for retval copy to use.
|
// Returns a chain and a flag for retval copy to use.
|
||||||
Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
|
Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
|
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
|
||||||
@ -2059,8 +2058,7 @@ static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
|
|||||||
|
|
||||||
RetOps.insert(RetOps.begin() + 1, DAG.getConstant(LROffset, MVT::i32, false));
|
RetOps.insert(RetOps.begin() + 1, DAG.getConstant(LROffset, MVT::i32, false));
|
||||||
|
|
||||||
return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other,
|
return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
|
||||||
RetOps.data(), RetOps.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue
|
SDValue
|
||||||
@ -2127,7 +2125,7 @@ ARMTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
// Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
|
// Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
|
||||||
// available.
|
// available.
|
||||||
SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
|
SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
|
||||||
DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
|
DAG.getVTList(MVT::i32, MVT::i32), Arg);
|
||||||
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
|
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
|
||||||
Flag = Chain.getValue(1);
|
Flag = Chain.getValue(1);
|
||||||
RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
|
RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
|
||||||
@ -2161,8 +2159,7 @@ ARMTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
return LowerInterruptReturn(RetOps, dl, DAG);
|
return LowerInterruptReturn(RetOps, dl, DAG);
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other,
|
return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
|
||||||
RetOps.data(), RetOps.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
|
bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
|
||||||
@ -2813,8 +2810,7 @@ ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
|
|||||||
AFI->setArgRegsSaveSize(ArgRegsSaveSize + AFI->getArgRegsSaveSize());
|
AFI->setArgRegsSaveSize(ArgRegsSaveSize + AFI->getArgRegsSaveSize());
|
||||||
|
|
||||||
if (!MemOps.empty())
|
if (!MemOps.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
|
||||||
&MemOps[0], MemOps.size());
|
|
||||||
return FrameIndex;
|
return FrameIndex;
|
||||||
} else {
|
} else {
|
||||||
if (ArgSize == 0) {
|
if (ArgSize == 0) {
|
||||||
@ -3483,7 +3479,7 @@ ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
ARMcc = DAG.getConstant(CondCode, MVT::i32);
|
ARMcc = DAG.getConstant(CondCode, MVT::i32);
|
||||||
SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
|
SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
|
||||||
return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
|
return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
return SDValue();
|
return SDValue();
|
||||||
@ -3523,11 +3519,11 @@ SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
|
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
|
||||||
SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
|
SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
|
||||||
SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
|
SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
|
||||||
if (CondCode2 != ARMCC::AL) {
|
if (CondCode2 != ARMCC::AL) {
|
||||||
ARMcc = DAG.getConstant(CondCode2, MVT::i32);
|
ARMcc = DAG.getConstant(CondCode2, MVT::i32);
|
||||||
SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
|
SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
|
||||||
Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
|
Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
|
||||||
}
|
}
|
||||||
return Res;
|
return Res;
|
||||||
}
|
}
|
||||||
@ -3724,7 +3720,7 @@ SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
// Bitcast operand 1 to i32.
|
// Bitcast operand 1 to i32.
|
||||||
if (SrcVT == MVT::f64)
|
if (SrcVT == MVT::f64)
|
||||||
Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
|
Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
|
||||||
&Tmp1, 1).getValue(1);
|
Tmp1).getValue(1);
|
||||||
Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
|
Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
|
||||||
|
|
||||||
// Or in the signbit with integer operations.
|
// Or in the signbit with integer operations.
|
||||||
@ -3740,7 +3736,7 @@ SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
|
|
||||||
// f64: Or the high part with signbit and then combine two parts.
|
// f64: Or the high part with signbit and then combine two parts.
|
||||||
Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
|
Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
|
||||||
&Tmp0, 1);
|
Tmp0);
|
||||||
SDValue Lo = Tmp0.getValue(0);
|
SDValue Lo = Tmp0.getValue(0);
|
||||||
SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
|
SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
|
||||||
Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
|
Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
|
||||||
@ -3818,7 +3814,7 @@ static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
|
|||||||
// Turn f64->i64 into VMOVRRD.
|
// Turn f64->i64 into VMOVRRD.
|
||||||
if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
|
if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
|
||||||
SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
|
SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
|
||||||
DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
|
DAG.getVTList(MVT::i32, MVT::i32), Op);
|
||||||
// Merge the pieces into a single i64 value.
|
// Merge the pieces into a single i64 value.
|
||||||
return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
|
return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
|
||||||
}
|
}
|
||||||
@ -4113,7 +4109,7 @@ static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
|
|||||||
// First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
|
// First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
|
||||||
// captures the result into a carry flag.
|
// captures the result into a carry flag.
|
||||||
unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
|
unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
|
||||||
Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
|
Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
|
||||||
|
|
||||||
// The low part is an ARMISD::RRX operand, which shifts the carry in.
|
// The low part is an ARMISD::RRX operand, which shifts the carry in.
|
||||||
Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
|
Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
|
||||||
@ -4870,7 +4866,7 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
|
|||||||
Ops.push_back(N);
|
Ops.push_back(N);
|
||||||
Ops.push_back(Op.getOperand(I));
|
Ops.push_back(Op.getOperand(I));
|
||||||
Ops.push_back(DAG.getConstant(I, MVT::i32));
|
Ops.push_back(DAG.getConstant(I, MVT::i32));
|
||||||
N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, &Ops[0], 3);
|
N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return N;
|
return N;
|
||||||
@ -4881,7 +4877,7 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
|
|||||||
Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
|
Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
|
||||||
Op.getOperand(i)));
|
Op.getOperand(i)));
|
||||||
EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
|
EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
|
||||||
SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
|
SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
|
||||||
Val = LowerBUILD_VECTOR(Val, DAG, ST);
|
Val = LowerBUILD_VECTOR(Val, DAG, ST);
|
||||||
if (Val.getNode())
|
if (Val.getNode())
|
||||||
return DAG.getNode(ISD::BITCAST, dl, VT, Val);
|
return DAG.getNode(ISD::BITCAST, dl, VT, Val);
|
||||||
@ -4917,7 +4913,7 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
|
|||||||
SmallVector<SDValue, 8> Ops;
|
SmallVector<SDValue, 8> Ops;
|
||||||
for (unsigned i = 0; i < NumElts; ++i)
|
for (unsigned i = 0; i < NumElts; ++i)
|
||||||
Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
|
Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
|
||||||
SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
|
SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
|
||||||
return DAG.getNode(ISD::BITCAST, dl, VT, Val);
|
return DAG.getNode(ISD::BITCAST, dl, VT, Val);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -5224,12 +5220,10 @@ static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
|
|||||||
|
|
||||||
if (V2.getNode()->getOpcode() == ISD::UNDEF)
|
if (V2.getNode()->getOpcode() == ISD::UNDEF)
|
||||||
return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
|
return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
|
||||||
DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
|
DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
|
||||||
&VTBLMask[0], 8));
|
|
||||||
|
|
||||||
return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
|
return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
|
||||||
DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
|
DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
|
||||||
&VTBLMask[0], 8));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
|
static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
|
||||||
@ -5382,7 +5376,7 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
|
|||||||
DAG.getConstant(ShuffleMask[i] & (NumElts-1),
|
DAG.getConstant(ShuffleMask[i] & (NumElts-1),
|
||||||
MVT::i32)));
|
MVT::i32)));
|
||||||
}
|
}
|
||||||
SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
|
SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
|
||||||
return DAG.getNode(ISD::BITCAST, dl, VT, Val);
|
return DAG.getNode(ISD::BITCAST, dl, VT, Val);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -5619,7 +5613,7 @@ static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
|
|||||||
Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
|
Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
|
||||||
}
|
}
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
|
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
|
||||||
MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
|
MVT::getVectorVT(TruncVT, NumElts), Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
|
static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
|
||||||
@ -6009,8 +6003,7 @@ static void ReplaceREADCYCLECOUNTER(SDNode *N,
|
|||||||
};
|
};
|
||||||
|
|
||||||
Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
|
Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
|
||||||
DAG.getVTList(MVT::i32, MVT::Other), &Ops[0],
|
DAG.getVTList(MVT::i32, MVT::Other), Ops);
|
||||||
array_lengthof(Ops));
|
|
||||||
OutChain = Cycles32.getValue(1);
|
OutChain = Cycles32.getValue(1);
|
||||||
} else {
|
} else {
|
||||||
// Intrinsic is defined to return 0 on unsupported platforms. Technically
|
// Intrinsic is defined to return 0 on unsupported platforms. Technically
|
||||||
@ -7531,8 +7524,7 @@ static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
|
|||||||
llvm_unreachable("Invalid vector element type for padd optimization.");
|
llvm_unreachable("Invalid vector element type for padd optimization.");
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
|
SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), widenType, Ops);
|
||||||
widenType, &Ops[0], Ops.size());
|
|
||||||
unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE;
|
unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE;
|
||||||
return DAG.getNode(ExtOp, SDLoc(N), VT, tmp);
|
return DAG.getNode(ExtOp, SDLoc(N), VT, tmp);
|
||||||
}
|
}
|
||||||
@ -7663,8 +7655,7 @@ static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
|
|||||||
Ops.push_back(*HiAdd);
|
Ops.push_back(*HiAdd);
|
||||||
|
|
||||||
SDValue MLALNode = DAG.getNode(FinalOpc, SDLoc(AddcNode),
|
SDValue MLALNode = DAG.getNode(FinalOpc, SDLoc(AddcNode),
|
||||||
DAG.getVTList(MVT::i32, MVT::i32),
|
DAG.getVTList(MVT::i32, MVT::i32), Ops);
|
||||||
&Ops[0], Ops.size());
|
|
||||||
|
|
||||||
// Replace the ADDs' nodes uses by the MLA node's values.
|
// Replace the ADDs' nodes uses by the MLA node's values.
|
||||||
SDValue HiMLALResult(MLALNode.getNode(), 1);
|
SDValue HiMLALResult(MLALNode.getNode(), 1);
|
||||||
@ -8301,8 +8292,7 @@ static SDValue PerformSTORECombine(SDNode *N,
|
|||||||
Increment);
|
Increment);
|
||||||
Chains.push_back(Ch);
|
Chains.push_back(Ch);
|
||||||
}
|
}
|
||||||
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &Chains[0],
|
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
|
||||||
Chains.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!ISD::isNormalStore(St))
|
if (!ISD::isNormalStore(St))
|
||||||
@ -8398,7 +8388,7 @@ static SDValue PerformBUILD_VECTORCombine(SDNode *N,
|
|||||||
DCI.AddToWorklist(V.getNode());
|
DCI.AddToWorklist(V.getNode());
|
||||||
}
|
}
|
||||||
EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
|
EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
|
||||||
SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
|
SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops);
|
||||||
return DAG.getNode(ISD::BITCAST, dl, VT, BV);
|
return DAG.getNode(ISD::BITCAST, dl, VT, BV);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -72,7 +72,8 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
|
|||||||
TFOps[i] = Loads[i].getValue(1);
|
TFOps[i] = Loads[i].getValue(1);
|
||||||
SrcOff += VTSize;
|
SrcOff += VTSize;
|
||||||
}
|
}
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
||||||
|
ArrayRef<SDValue>(TFOps, i));
|
||||||
|
|
||||||
for (i = 0;
|
for (i = 0;
|
||||||
i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
|
i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
|
||||||
@ -83,7 +84,8 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
|
|||||||
isVolatile, false, 0);
|
isVolatile, false, 0);
|
||||||
DstOff += VTSize;
|
DstOff += VTSize;
|
||||||
}
|
}
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
||||||
|
ArrayRef<SDValue>(TFOps, i));
|
||||||
|
|
||||||
EmittedNumMemOps += i;
|
EmittedNumMemOps += i;
|
||||||
}
|
}
|
||||||
@ -113,7 +115,8 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
|
|||||||
SrcOff += VTSize;
|
SrcOff += VTSize;
|
||||||
BytesLeft -= VTSize;
|
BytesLeft -= VTSize;
|
||||||
}
|
}
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
||||||
|
ArrayRef<SDValue>(TFOps, i));
|
||||||
|
|
||||||
i = 0;
|
i = 0;
|
||||||
BytesLeft = BytesLeftSave;
|
BytesLeft = BytesLeftSave;
|
||||||
@ -134,7 +137,8 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
|
|||||||
DstOff += VTSize;
|
DstOff += VTSize;
|
||||||
BytesLeft -= VTSize;
|
BytesLeft -= VTSize;
|
||||||
}
|
}
|
||||||
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
|
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
||||||
|
ArrayRef<SDValue>(TFOps, i));
|
||||||
}
|
}
|
||||||
|
|
||||||
// Adjust parameters for memset, EABI uses format (ptr, size, value),
|
// Adjust parameters for memset, EABI uses format (ptr, size, value),
|
||||||
|
@ -1421,8 +1421,7 @@ static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
|
|||||||
BuildVectorOps.push_back(Sclr);
|
BuildVectorOps.push_back(Sclr);
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &BuildVectorOps[0],
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, BuildVectorOps);
|
||||||
BuildVectorOps.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue ARM64TargetLowering::LowerINT_TO_FP(SDValue Op,
|
SDValue ARM64TargetLowering::LowerINT_TO_FP(SDValue Op,
|
||||||
@ -1821,8 +1820,7 @@ void ARM64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (!MemOps.empty()) {
|
if (!MemOps.empty()) {
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
|
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
|
||||||
MemOps.size());
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -2109,8 +2107,7 @@ SDValue ARM64TargetLowering::LowerCall(CallLoweringInfo &CLI,
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (!MemOpChains.empty())
|
if (!MemOpChains.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOpChains[0],
|
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
|
||||||
MemOpChains.size());
|
|
||||||
|
|
||||||
// Build a sequence of copy-to-reg nodes chained together with token chain
|
// Build a sequence of copy-to-reg nodes chained together with token chain
|
||||||
// and flag operands which copy the outgoing args into the appropriate regs.
|
// and flag operands which copy the outgoing args into the appropriate regs.
|
||||||
@ -2186,10 +2183,10 @@ SDValue ARM64TargetLowering::LowerCall(CallLoweringInfo &CLI,
|
|||||||
// If we're doing a tall call, use a TC_RETURN here rather than an
|
// If we're doing a tall call, use a TC_RETURN here rather than an
|
||||||
// actual call instruction.
|
// actual call instruction.
|
||||||
if (IsTailCall)
|
if (IsTailCall)
|
||||||
return DAG.getNode(ARM64ISD::TC_RETURN, DL, NodeTys, &Ops[0], Ops.size());
|
return DAG.getNode(ARM64ISD::TC_RETURN, DL, NodeTys, Ops);
|
||||||
|
|
||||||
// Returns a chain and a flag for retval copy to use.
|
// Returns a chain and a flag for retval copy to use.
|
||||||
Chain = DAG.getNode(ARM64ISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
|
Chain = DAG.getNode(ARM64ISD::CALL, DL, NodeTys, Ops);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
|
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
|
||||||
@ -2257,8 +2254,7 @@ ARM64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
|
|||||||
if (Flag.getNode())
|
if (Flag.getNode())
|
||||||
RetOps.push_back(Flag);
|
RetOps.push_back(Flag);
|
||||||
|
|
||||||
return DAG.getNode(ARM64ISD::RET_FLAG, DL, MVT::Other, &RetOps[0],
|
return DAG.getNode(ARM64ISD::RET_FLAG, DL, MVT::Other, RetOps);
|
||||||
RetOps.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
@ -2428,7 +2424,7 @@ SDValue ARM64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
|
|||||||
Ops.push_back(Glue);
|
Ops.push_back(Glue);
|
||||||
|
|
||||||
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
Chain = DAG.getNode(ARM64ISD::TLSDESC_CALL, DL, NodeTys, &Ops[0], Ops.size());
|
Chain = DAG.getNode(ARM64ISD::TLSDESC_CALL, DL, NodeTys, Ops);
|
||||||
Glue = Chain.getValue(1);
|
Glue = Chain.getValue(1);
|
||||||
|
|
||||||
return DAG.getCopyFromReg(Chain, DL, ARM64::X0, PtrVT, Glue);
|
return DAG.getCopyFromReg(Chain, DL, ARM64::X0, PtrVT, Glue);
|
||||||
@ -2738,8 +2734,7 @@ SDValue ARM64TargetLowering::LowerFCOPYSIGN(SDValue Op,
|
|||||||
for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i)
|
for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i)
|
||||||
BuildVectorOps.push_back(EltMask);
|
BuildVectorOps.push_back(EltMask);
|
||||||
|
|
||||||
SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT,
|
SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps);
|
||||||
&BuildVectorOps[0], BuildVectorOps.size());
|
|
||||||
|
|
||||||
// If we couldn't materialize the mask above, then the mask vector will be
|
// If we couldn't materialize the mask above, then the mask vector will be
|
||||||
// the zero vector, and we need to negate it here.
|
// the zero vector, and we need to negate it here.
|
||||||
@ -3276,8 +3271,7 @@ SDValue ARM64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
|
|||||||
VROffsAddr, MachinePointerInfo(SV, 28), false,
|
VROffsAddr, MachinePointerInfo(SV, 28), false,
|
||||||
false, 4));
|
false, 4));
|
||||||
|
|
||||||
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
|
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
|
||||||
MemOps.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue ARM64TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
|
SDValue ARM64TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
|
||||||
@ -4362,14 +4356,16 @@ static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
|
|||||||
Shuffle = DAG.getNode(
|
Shuffle = DAG.getNode(
|
||||||
ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
|
ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
|
||||||
DAG.getConstant(Intrinsic::arm64_neon_tbl1, MVT::i32), V1Cst,
|
DAG.getConstant(Intrinsic::arm64_neon_tbl1, MVT::i32), V1Cst,
|
||||||
DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT, &TBLMask[0], IndexLen));
|
DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
|
||||||
|
ArrayRef<SDValue>(TBLMask.data(), IndexLen)));
|
||||||
} else {
|
} else {
|
||||||
if (IndexLen == 8) {
|
if (IndexLen == 8) {
|
||||||
V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
|
V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
|
||||||
Shuffle = DAG.getNode(
|
Shuffle = DAG.getNode(
|
||||||
ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
|
ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
|
||||||
DAG.getConstant(Intrinsic::arm64_neon_tbl1, MVT::i32), V1Cst,
|
DAG.getConstant(Intrinsic::arm64_neon_tbl1, MVT::i32), V1Cst,
|
||||||
DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT, &TBLMask[0], IndexLen));
|
DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
|
||||||
|
ArrayRef<SDValue>(TBLMask.data(), IndexLen)));
|
||||||
} else {
|
} else {
|
||||||
// FIXME: We cannot, for the moment, emit a TBL2 instruction because we
|
// FIXME: We cannot, for the moment, emit a TBL2 instruction because we
|
||||||
// cannot currently represent the register constraints on the input
|
// cannot currently represent the register constraints on the input
|
||||||
@ -4380,7 +4376,8 @@ static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
|
|||||||
Shuffle = DAG.getNode(
|
Shuffle = DAG.getNode(
|
||||||
ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
|
ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
|
||||||
DAG.getConstant(Intrinsic::arm64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
|
DAG.getConstant(Intrinsic::arm64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
|
||||||
DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT, &TBLMask[0], IndexLen));
|
DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
|
||||||
|
ArrayRef<SDValue>(TBLMask.data(), IndexLen)));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
|
return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
|
||||||
@ -5163,7 +5160,7 @@ FailedModImm:
|
|||||||
for (unsigned i = 0; i < NumElts; ++i)
|
for (unsigned i = 0; i < NumElts; ++i)
|
||||||
Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
|
Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
|
||||||
EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
|
EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
|
||||||
SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
|
SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
|
||||||
Val = LowerBUILD_VECTOR(Val, DAG);
|
Val = LowerBUILD_VECTOR(Val, DAG);
|
||||||
if (Val.getNode())
|
if (Val.getNode())
|
||||||
return DAG.getNode(ISD::BITCAST, dl, VT, Val);
|
return DAG.getNode(ISD::BITCAST, dl, VT, Val);
|
||||||
|
@ -348,8 +348,7 @@ HexagonTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
if (Flag.getNode())
|
if (Flag.getNode())
|
||||||
RetOps.push_back(Flag);
|
RetOps.push_back(Flag);
|
||||||
|
|
||||||
return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other,
|
return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
|
||||||
&RetOps[0], RetOps.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -522,8 +521,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
// Transform all store nodes into one single node because all store
|
// Transform all store nodes into one single node because all store
|
||||||
// nodes are independent of each other.
|
// nodes are independent of each other.
|
||||||
if (!MemOpChains.empty()) {
|
if (!MemOpChains.empty()) {
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0],
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
|
||||||
MemOpChains.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!isTailCall)
|
if (!isTailCall)
|
||||||
@ -597,9 +595,9 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (isTailCall)
|
if (isTailCall)
|
||||||
return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
|
return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
|
||||||
|
|
||||||
Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
|
Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
// Create the CALLSEQ_END node.
|
// Create the CALLSEQ_END node.
|
||||||
@ -918,8 +916,7 @@ const {
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (!MemOps.empty())
|
if (!MemOps.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0],
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
|
||||||
MemOps.size());
|
|
||||||
|
|
||||||
if (isVarArg) {
|
if (isVarArg) {
|
||||||
// This will point to the next argument passed via stack.
|
// This will point to the next argument passed via stack.
|
||||||
|
@ -568,7 +568,7 @@ MSP430TargetLowering::LowerReturn(SDValue Chain,
|
|||||||
if (Flag.getNode())
|
if (Flag.getNode())
|
||||||
RetOps.push_back(Flag);
|
RetOps.push_back(Flag);
|
||||||
|
|
||||||
return DAG.getNode(Opc, dl, MVT::Other, &RetOps[0], RetOps.size());
|
return DAG.getNode(Opc, dl, MVT::Other, RetOps);
|
||||||
}
|
}
|
||||||
|
|
||||||
/// LowerCCCCallTo - functions arguments are copied from virtual regs to
|
/// LowerCCCCallTo - functions arguments are copied from virtual regs to
|
||||||
@ -659,8 +659,7 @@ MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
|
|||||||
// Transform all store nodes into one single node because all store nodes are
|
// Transform all store nodes into one single node because all store nodes are
|
||||||
// independent of each other.
|
// independent of each other.
|
||||||
if (!MemOpChains.empty())
|
if (!MemOpChains.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
|
||||||
&MemOpChains[0], MemOpChains.size());
|
|
||||||
|
|
||||||
// Build a sequence of copy-to-reg nodes chained together with token chain and
|
// Build a sequence of copy-to-reg nodes chained together with token chain and
|
||||||
// flag operands which copy the outgoing args into registers. The InFlag in
|
// flag operands which copy the outgoing args into registers. The InFlag in
|
||||||
@ -695,7 +694,7 @@ MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
|
|||||||
if (InFlag.getNode())
|
if (InFlag.getNode())
|
||||||
Ops.push_back(InFlag);
|
Ops.push_back(InFlag);
|
||||||
|
|
||||||
Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
|
Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
// Create the CALLSEQ_END node.
|
// Create the CALLSEQ_END node.
|
||||||
@ -986,7 +985,7 @@ SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
Ops.push_back(Zero);
|
Ops.push_back(Zero);
|
||||||
Ops.push_back(TargetCC);
|
Ops.push_back(TargetCC);
|
||||||
Ops.push_back(Flag);
|
Ops.push_back(Flag);
|
||||||
return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
|
return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1009,7 +1008,7 @@ SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
|
|||||||
Ops.push_back(TargetCC);
|
Ops.push_back(TargetCC);
|
||||||
Ops.push_back(Flag);
|
Ops.push_back(Flag);
|
||||||
|
|
||||||
return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
|
return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
|
SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
|
||||||
|
@ -1510,7 +1510,7 @@ SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
|
|||||||
SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0,
|
SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0,
|
||||||
MipsII::MO_GPREL);
|
MipsII::MO_GPREL);
|
||||||
SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL,
|
SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL,
|
||||||
DAG.getVTList(MVT::i32), &GA, 1);
|
DAG.getVTList(MVT::i32), GA);
|
||||||
SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
|
SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
|
||||||
return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode);
|
return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode);
|
||||||
}
|
}
|
||||||
@ -2438,8 +2438,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
// Transform all store nodes into one single node because all store
|
// Transform all store nodes into one single node because all store
|
||||||
// nodes are independent of each other.
|
// nodes are independent of each other.
|
||||||
if (!MemOpChains.empty())
|
if (!MemOpChains.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
|
||||||
&MemOpChains[0], MemOpChains.size());
|
|
||||||
|
|
||||||
// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
|
// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
|
||||||
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
|
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
|
||||||
@ -2493,9 +2492,9 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
CLI, Callee, Chain);
|
CLI, Callee, Chain);
|
||||||
|
|
||||||
if (IsTailCall)
|
if (IsTailCall)
|
||||||
return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, &Ops[0], Ops.size());
|
return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
|
||||||
|
|
||||||
Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, &Ops[0], Ops.size());
|
Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
|
||||||
SDValue InFlag = Chain.getValue(1);
|
SDValue InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
// Create the CALLSEQ_END node.
|
// Create the CALLSEQ_END node.
|
||||||
@ -2683,8 +2682,7 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
|
|||||||
// the size of Ins and InVals. This only happens when on varg functions
|
// the size of Ins and InVals. This only happens when on varg functions
|
||||||
if (!OutChains.empty()) {
|
if (!OutChains.empty()) {
|
||||||
OutChains.push_back(Chain);
|
OutChains.push_back(Chain);
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
|
||||||
&OutChains[0], OutChains.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return Chain;
|
return Chain;
|
||||||
@ -2769,7 +2767,7 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
RetOps.push_back(Flag);
|
RetOps.push_back(Flag);
|
||||||
|
|
||||||
// Return on Mips is always a "jr $ra"
|
// Return on Mips is always a "jr $ra"
|
||||||
return DAG.getNode(MipsISD::Ret, DL, MVT::Other, &RetOps[0], RetOps.size());
|
return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
|
||||||
}
|
}
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
@ -1236,7 +1236,7 @@ static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
|
|||||||
ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
|
ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
|
||||||
|
|
||||||
// Create node.
|
// Create node.
|
||||||
SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
|
SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops);
|
||||||
SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
|
SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
|
||||||
|
|
||||||
if (!HasChainIn)
|
if (!HasChainIn)
|
||||||
@ -1281,8 +1281,8 @@ static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
|
|||||||
SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
|
SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
|
||||||
LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
|
LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
|
||||||
|
|
||||||
SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, Ops,
|
SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
|
||||||
ViaVecTy.getVectorNumElements());
|
ArrayRef<SDValue>(Ops, ViaVecTy.getVectorNumElements()));
|
||||||
|
|
||||||
if (ViaVecTy != ResVecTy)
|
if (ViaVecTy != ResVecTy)
|
||||||
Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
|
Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
|
||||||
@ -1321,8 +1321,8 @@ static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
|
|||||||
SplatValueA, SplatValueB, SplatValueA, SplatValueB,
|
SplatValueA, SplatValueB, SplatValueA, SplatValueB,
|
||||||
SplatValueA, SplatValueB, SplatValueA, SplatValueB };
|
SplatValueA, SplatValueB, SplatValueA, SplatValueB };
|
||||||
|
|
||||||
SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, Ops,
|
SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
|
||||||
ViaVecTy.getVectorNumElements());
|
ArrayRef<SDValue>(Ops, ViaVecTy.getVectorNumElements()));
|
||||||
|
|
||||||
if (VecTy != ViaVecTy)
|
if (VecTy != ViaVecTy)
|
||||||
Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
|
Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
|
||||||
@ -1736,7 +1736,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
|
|||||||
|
|
||||||
// If ResTy is v2i64 then the type legalizer will break this node down into
|
// If ResTy is v2i64 then the type legalizer will break this node down into
|
||||||
// an equivalent v4i32.
|
// an equivalent v4i32.
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size());
|
return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, Ops);
|
||||||
}
|
}
|
||||||
case Intrinsic::mips_fexp2_w:
|
case Intrinsic::mips_fexp2_w:
|
||||||
case Intrinsic::mips_fexp2_d: {
|
case Intrinsic::mips_fexp2_d: {
|
||||||
@ -2561,8 +2561,7 @@ static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
|
|||||||
++I)
|
++I)
|
||||||
Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
|
Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
|
||||||
|
|
||||||
SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, &Ops[0],
|
SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, Ops);
|
||||||
Ops.size());
|
|
||||||
|
|
||||||
if (Using1stVec && Using2ndVec) {
|
if (Using1stVec && Using2ndVec) {
|
||||||
Op0 = Op->getOperand(0);
|
Op0 = Op->getOperand(0);
|
||||||
|
@ -685,7 +685,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
DAG.getConstant(paramCount, MVT::i32),
|
DAG.getConstant(paramCount, MVT::i32),
|
||||||
DAG.getConstant(sz, MVT::i32), InFlag };
|
DAG.getConstant(sz, MVT::i32), InFlag };
|
||||||
Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
|
Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
|
||||||
DeclareParamOps, 5);
|
DeclareParamOps);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
unsigned curOffset = 0;
|
unsigned curOffset = 0;
|
||||||
for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
|
for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
|
||||||
@ -731,7 +731,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
DAG.getConstant(paramCount, MVT::i32),
|
DAG.getConstant(paramCount, MVT::i32),
|
||||||
DAG.getConstant(sz, MVT::i32), InFlag };
|
DAG.getConstant(sz, MVT::i32), InFlag };
|
||||||
Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
|
Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
|
||||||
DeclareParamOps, 5);
|
DeclareParamOps);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
unsigned NumElts = ObjectVT.getVectorNumElements();
|
unsigned NumElts = ObjectVT.getVectorNumElements();
|
||||||
EVT EltVT = ObjectVT.getVectorElementType();
|
EVT EltVT = ObjectVT.getVectorElementType();
|
||||||
@ -872,7 +872,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
DAG.getConstant(sz, MVT::i32),
|
DAG.getConstant(sz, MVT::i32),
|
||||||
DAG.getConstant(0, MVT::i32), InFlag };
|
DAG.getConstant(0, MVT::i32), InFlag };
|
||||||
Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
|
Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
|
||||||
DeclareParamOps, 5);
|
DeclareParamOps);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
SDValue OutV = OutVals[OIdx];
|
SDValue OutV = OutVals[OIdx];
|
||||||
if (needExtend) {
|
if (needExtend) {
|
||||||
@ -916,7 +916,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
InFlag
|
InFlag
|
||||||
};
|
};
|
||||||
Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
|
Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
|
||||||
DeclareParamOps, 5);
|
DeclareParamOps);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
unsigned curOffset = 0;
|
unsigned curOffset = 0;
|
||||||
for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
|
for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
|
||||||
@ -975,7 +975,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
DAG.getConstant(resultsz, MVT::i32),
|
DAG.getConstant(resultsz, MVT::i32),
|
||||||
DAG.getConstant(0, MVT::i32), InFlag };
|
DAG.getConstant(0, MVT::i32), InFlag };
|
||||||
Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
|
Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
|
||||||
DeclareRetOps, 5);
|
DeclareRetOps);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
} else {
|
} else {
|
||||||
retAlignment = getArgumentAlignment(Callee, CS, retTy, 0);
|
retAlignment = getArgumentAlignment(Callee, CS, retTy, 0);
|
||||||
@ -985,7 +985,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
DAG.getConstant(resultsz / 8, MVT::i32),
|
DAG.getConstant(resultsz / 8, MVT::i32),
|
||||||
DAG.getConstant(0, MVT::i32), InFlag };
|
DAG.getConstant(0, MVT::i32), InFlag };
|
||||||
Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
|
Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
|
||||||
DeclareRetOps, 5);
|
DeclareRetOps);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -1005,7 +1005,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
SDValue ProtoOps[] = {
|
SDValue ProtoOps[] = {
|
||||||
Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
|
Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
|
||||||
};
|
};
|
||||||
Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, &ProtoOps[0], 3);
|
Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
}
|
}
|
||||||
// Op to just print "call"
|
// Op to just print "call"
|
||||||
@ -1014,20 +1014,20 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, MVT::i32), InFlag
|
Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, MVT::i32), InFlag
|
||||||
};
|
};
|
||||||
Chain = DAG.getNode(Func ? (NVPTXISD::PrintCallUni) : (NVPTXISD::PrintCall),
|
Chain = DAG.getNode(Func ? (NVPTXISD::PrintCallUni) : (NVPTXISD::PrintCall),
|
||||||
dl, PrintCallVTs, PrintCallOps, 3);
|
dl, PrintCallVTs, PrintCallOps);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
// Ops to print out the function name
|
// Ops to print out the function name
|
||||||
SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
SDValue CallVoidOps[] = { Chain, Callee, InFlag };
|
SDValue CallVoidOps[] = { Chain, Callee, InFlag };
|
||||||
Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps, 3);
|
Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
// Ops to print out the param list
|
// Ops to print out the param list
|
||||||
SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
SDValue CallArgBeginOps[] = { Chain, InFlag };
|
SDValue CallArgBeginOps[] = { Chain, InFlag };
|
||||||
Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
|
Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
|
||||||
CallArgBeginOps, 2);
|
CallArgBeginOps);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
for (unsigned i = 0, e = paramCount; i != e; ++i) {
|
for (unsigned i = 0, e = paramCount; i != e; ++i) {
|
||||||
@ -1039,21 +1039,20 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
SDValue CallArgOps[] = { Chain, DAG.getConstant(1, MVT::i32),
|
SDValue CallArgOps[] = { Chain, DAG.getConstant(1, MVT::i32),
|
||||||
DAG.getConstant(i, MVT::i32), InFlag };
|
DAG.getConstant(i, MVT::i32), InFlag };
|
||||||
Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps, 4);
|
Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
}
|
}
|
||||||
SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
SDValue CallArgEndOps[] = { Chain, DAG.getConstant(Func ? 1 : 0, MVT::i32),
|
SDValue CallArgEndOps[] = { Chain, DAG.getConstant(Func ? 1 : 0, MVT::i32),
|
||||||
InFlag };
|
InFlag };
|
||||||
Chain =
|
Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
|
||||||
DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps, 3);
|
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
if (!Func) {
|
if (!Func) {
|
||||||
SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
SDValue PrototypeOps[] = { Chain, DAG.getConstant(uniqueCallSite, MVT::i32),
|
SDValue PrototypeOps[] = { Chain, DAG.getConstant(uniqueCallSite, MVT::i32),
|
||||||
InFlag };
|
InFlag };
|
||||||
Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps, 3);
|
Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1263,8 +1262,7 @@ NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
DAG.getIntPtrConstant(j)));
|
DAG.getIntPtrConstant(j)));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), &Ops[0],
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Ops);
|
||||||
Ops.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue
|
SDValue
|
||||||
@ -1793,8 +1791,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
|
|||||||
//}
|
//}
|
||||||
|
|
||||||
if (!OutChains.empty())
|
if (!OutChains.empty())
|
||||||
DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &OutChains[0],
|
DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains));
|
||||||
OutChains.size()));
|
|
||||||
|
|
||||||
return Chain;
|
return Chain;
|
||||||
}
|
}
|
||||||
@ -2561,8 +2558,7 @@ static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
|
|||||||
|
|
||||||
SDValue LoadChain = NewLD.getValue(NumElts);
|
SDValue LoadChain = NewLD.getValue(NumElts);
|
||||||
|
|
||||||
SDValue BuildVec =
|
SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
|
||||||
DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, &ScalarRes[0], NumElts);
|
|
||||||
|
|
||||||
Results.push_back(BuildVec);
|
Results.push_back(BuildVec);
|
||||||
Results.push_back(LoadChain);
|
Results.push_back(LoadChain);
|
||||||
@ -2676,7 +2672,7 @@ static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
|
|||||||
SDValue LoadChain = NewLD.getValue(NumElts);
|
SDValue LoadChain = NewLD.getValue(NumElts);
|
||||||
|
|
||||||
SDValue BuildVec =
|
SDValue BuildVec =
|
||||||
DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, &ScalarRes[0], NumElts);
|
DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
|
||||||
|
|
||||||
Results.push_back(BuildVec);
|
Results.push_back(BuildVec);
|
||||||
Results.push_back(LoadChain);
|
Results.push_back(LoadChain);
|
||||||
|
@ -2334,8 +2334,7 @@ PPCTargetLowering::LowerFormalArguments_32SVR4(
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (!MemOps.empty())
|
if (!MemOps.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
|
||||||
MVT::Other, &MemOps[0], MemOps.size());
|
|
||||||
|
|
||||||
return Chain;
|
return Chain;
|
||||||
}
|
}
|
||||||
@ -2684,8 +2683,7 @@ PPCTargetLowering::LowerFormalArguments_64SVR4(
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (!MemOps.empty())
|
if (!MemOps.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
|
||||||
MVT::Other, &MemOps[0], MemOps.size());
|
|
||||||
|
|
||||||
return Chain;
|
return Chain;
|
||||||
}
|
}
|
||||||
@ -3040,8 +3038,7 @@ PPCTargetLowering::LowerFormalArguments_Darwin(
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (!MemOps.empty())
|
if (!MemOps.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
|
||||||
MVT::Other, &MemOps[0], MemOps.size());
|
|
||||||
|
|
||||||
return Chain;
|
return Chain;
|
||||||
}
|
}
|
||||||
@ -3362,8 +3359,7 @@ void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
|
|||||||
StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
|
StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
|
||||||
MemOpChains2, dl);
|
MemOpChains2, dl);
|
||||||
if (!MemOpChains2.empty())
|
if (!MemOpChains2.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
|
||||||
&MemOpChains2[0], MemOpChains2.size());
|
|
||||||
|
|
||||||
// Store the return address to the appropriate stack slot.
|
// Store the return address to the appropriate stack slot.
|
||||||
Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
|
Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
|
||||||
@ -3477,8 +3473,8 @@ unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
|
|||||||
// Load the address of the function entry point from the function
|
// Load the address of the function entry point from the function
|
||||||
// descriptor.
|
// descriptor.
|
||||||
SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
|
SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
|
||||||
SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
|
SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
|
||||||
InFlag.getNode() ? 3 : 2);
|
ArrayRef<SDValue>(MTCTROps, InFlag.getNode() ? 3 : 2));
|
||||||
Chain = LoadFuncPtr.getValue(1);
|
Chain = LoadFuncPtr.getValue(1);
|
||||||
InFlag = LoadFuncPtr.getValue(2);
|
InFlag = LoadFuncPtr.getValue(2);
|
||||||
|
|
||||||
@ -3514,8 +3510,8 @@ unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
|
|||||||
MTCTROps[2] = InFlag;
|
MTCTROps[2] = InFlag;
|
||||||
}
|
}
|
||||||
|
|
||||||
Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
|
Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
|
||||||
InFlag.getNode() ? 3 : 2);
|
ArrayRef<SDValue>(MTCTROps, InFlag.getNode() ? 3 : 2));
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
NodeTys.clear();
|
NodeTys.clear();
|
||||||
@ -3651,7 +3647,7 @@ PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
|
|||||||
isa<ConstantSDNode>(Callee)) &&
|
isa<ConstantSDNode>(Callee)) &&
|
||||||
"Expecting an global address, external symbol, absolute value or register");
|
"Expecting an global address, external symbol, absolute value or register");
|
||||||
|
|
||||||
return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
|
return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Add a NOP immediately after the branch instruction when using the 64-bit
|
// Add a NOP immediately after the branch instruction when using the 64-bit
|
||||||
@ -3684,7 +3680,7 @@ PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
|
Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
if (needsTOCRestore) {
|
if (needsTOCRestore) {
|
||||||
@ -3926,8 +3922,7 @@ PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (!MemOpChains.empty())
|
if (!MemOpChains.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
|
||||||
&MemOpChains[0], MemOpChains.size());
|
|
||||||
|
|
||||||
// Build a sequence of copy-to-reg nodes chained together with token chain
|
// Build a sequence of copy-to-reg nodes chained together with token chain
|
||||||
// and flag operands which copy the outgoing args into the appropriate regs.
|
// and flag operands which copy the outgoing args into the appropriate regs.
|
||||||
@ -3945,7 +3940,8 @@ PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
|
|||||||
SDValue Ops[] = { Chain, InFlag };
|
SDValue Ops[] = { Chain, InFlag };
|
||||||
|
|
||||||
Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
|
Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
|
||||||
dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
|
dl, VTs,
|
||||||
|
ArrayRef<SDValue>(Ops, InFlag.getNode() ? 2 : 1));
|
||||||
|
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
}
|
}
|
||||||
@ -4338,8 +4334,7 @@ PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (!MemOpChains.empty())
|
if (!MemOpChains.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
|
||||||
&MemOpChains[0], MemOpChains.size());
|
|
||||||
|
|
||||||
// Check if this is an indirect call (MTCTR/BCTRL).
|
// Check if this is an indirect call (MTCTR/BCTRL).
|
||||||
// See PrepareCall() for more information about calls through function
|
// See PrepareCall() for more information about calls through function
|
||||||
@ -4701,8 +4696,7 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (!MemOpChains.empty())
|
if (!MemOpChains.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
|
||||||
&MemOpChains[0], MemOpChains.size());
|
|
||||||
|
|
||||||
// On Darwin, R12 must contain the address of an indirect callee. This does
|
// On Darwin, R12 must contain the address of an indirect callee. This does
|
||||||
// not mean the MTCTR instruction must use R12; it's easier to model this as
|
// not mean the MTCTR instruction must use R12; it's easier to model this as
|
||||||
@ -4790,8 +4784,7 @@ PPCTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
if (Flag.getNode())
|
if (Flag.getNode())
|
||||||
RetOps.push_back(Flag);
|
RetOps.push_back(Flag);
|
||||||
|
|
||||||
return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
|
return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
|
||||||
&RetOps[0], RetOps.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
|
SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
|
||||||
@ -4894,7 +4887,7 @@ SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
|
|||||||
// Build a DYNALLOC node.
|
// Build a DYNALLOC node.
|
||||||
SDValue Ops[3] = { Chain, NegSize, FPSIdx };
|
SDValue Ops[3] = { Chain, NegSize, FPSIdx };
|
||||||
SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
|
SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
|
||||||
return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
|
return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
|
SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
|
||||||
@ -5284,14 +5277,13 @@ SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
|
|||||||
MachineFunction &MF = DAG.getMachineFunction();
|
MachineFunction &MF = DAG.getMachineFunction();
|
||||||
EVT VT = Op.getValueType();
|
EVT VT = Op.getValueType();
|
||||||
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
||||||
SDValue MFFSreg, InFlag;
|
|
||||||
|
|
||||||
// Save FP Control Word to register
|
// Save FP Control Word to register
|
||||||
EVT NodeTys[] = {
|
EVT NodeTys[] = {
|
||||||
MVT::f64, // return register
|
MVT::f64, // return register
|
||||||
MVT::Glue // unused in this context
|
MVT::Glue // unused in this context
|
||||||
};
|
};
|
||||||
SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
|
SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, ArrayRef<SDValue>());
|
||||||
|
|
||||||
// Save FP register to stack slot
|
// Save FP register to stack slot
|
||||||
int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
|
int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
|
||||||
@ -5437,8 +5429,7 @@ static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
|
|||||||
SDValue Elt = DAG.getConstant(Val, MVT::i32);
|
SDValue Elt = DAG.getConstant(Val, MVT::i32);
|
||||||
SmallVector<SDValue, 8> Ops;
|
SmallVector<SDValue, 8> Ops;
|
||||||
Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
|
Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
|
||||||
SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
|
SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
|
||||||
&Ops[0], Ops.size());
|
|
||||||
return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
|
return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -5843,7 +5834,7 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
|
|||||||
}
|
}
|
||||||
|
|
||||||
SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
|
SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
|
||||||
&ResultMask[0], ResultMask.size());
|
ResultMask);
|
||||||
return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
|
return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -5918,7 +5909,7 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
|
|||||||
DAG.getConstant(CompareOpc, MVT::i32)
|
DAG.getConstant(CompareOpc, MVT::i32)
|
||||||
};
|
};
|
||||||
EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
|
EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
|
||||||
SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
|
SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
|
||||||
|
|
||||||
// Now that we have the comparison, emit a copy from the CR to a GPR.
|
// Now that we have the comparison, emit a copy from the CR to a GPR.
|
||||||
// This is flagged to the above dot comparison.
|
// This is flagged to the above dot comparison.
|
||||||
@ -7584,8 +7575,7 @@ SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
|
|||||||
Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
|
Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
|
||||||
|
|
||||||
DAG.ReplaceAllUsesOfValueWith(PromOp,
|
DAG.ReplaceAllUsesOfValueWith(PromOp,
|
||||||
DAG.getNode(PromOp.getOpcode(), dl, MVT::i1,
|
DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
|
||||||
Ops.data(), Ops.size()));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// Now we're left with the initial truncation itself.
|
// Now we're left with the initial truncation itself.
|
||||||
@ -7821,8 +7811,7 @@ SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
|
|||||||
}
|
}
|
||||||
|
|
||||||
DAG.ReplaceAllUsesOfValueWith(PromOp,
|
DAG.ReplaceAllUsesOfValueWith(PromOp,
|
||||||
DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0),
|
DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
|
||||||
Ops.data(), Ops.size()));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// Now we're left with the initial extension itself.
|
// Now we're left with the initial extension itself.
|
||||||
@ -8383,7 +8372,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
|
|||||||
DAG.getConstant(CompareOpc, MVT::i32)
|
DAG.getConstant(CompareOpc, MVT::i32)
|
||||||
};
|
};
|
||||||
EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
|
EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
|
||||||
SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
|
SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
|
||||||
|
|
||||||
// Unpack the result based on how the target uses it.
|
// Unpack the result based on how the target uses it.
|
||||||
PPC::Predicate CompOpc;
|
PPC::Predicate CompOpc;
|
||||||
|
@ -444,8 +444,7 @@ SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
|
|||||||
Chains.push_back(LowerConstantInitializer(Init->getAggregateElement(i),
|
Chains.push_back(LowerConstantInitializer(Init->getAggregateElement(i),
|
||||||
GV, Ptr, Chain, DAG));
|
GV, Ptr, Chain, DAG));
|
||||||
}
|
}
|
||||||
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
|
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
|
||||||
Chains.data(), Chains.size());
|
|
||||||
} else {
|
} else {
|
||||||
Init->dump();
|
Init->dump();
|
||||||
llvm_unreachable("Unhandled constant initializer");
|
llvm_unreachable("Unhandled constant initializer");
|
||||||
@ -525,8 +524,7 @@ SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
|
|||||||
DAG.ExtractVectorElements(A, Args);
|
DAG.ExtractVectorElements(A, Args);
|
||||||
DAG.ExtractVectorElements(B, Args);
|
DAG.ExtractVectorElements(B, Args);
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
|
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
|
||||||
Args.data(), Args.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
|
SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
|
||||||
@ -538,8 +536,7 @@ SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
|
|||||||
DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
|
DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
|
||||||
VT.getVectorNumElements());
|
VT.getVectorNumElements());
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
|
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
|
||||||
Args.data(), Args.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
|
SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
|
||||||
@ -728,8 +725,7 @@ SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op,
|
|||||||
MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
|
MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
|
||||||
Load->getAlignment()));
|
Load->getAlignment()));
|
||||||
}
|
}
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, SL, Op.getValueType(),
|
return DAG.getNode(ISD::BUILD_VECTOR, SL, Op.getValueType(), Loads);
|
||||||
Loads.data(), Loads.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
|
SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
|
||||||
@ -813,7 +809,7 @@ SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
|
|||||||
MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
|
MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
|
||||||
Store->getAlignment()));
|
Store->getAlignment()));
|
||||||
}
|
}
|
||||||
return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains.data(), NumElts);
|
return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
|
SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
|
||||||
@ -1107,7 +1103,7 @@ SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
|
|||||||
for (unsigned I = 0; I < NElts; ++I)
|
for (unsigned I = 0; I < NElts; ++I)
|
||||||
Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
|
Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args.data(), Args.size());
|
return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
|
||||||
}
|
}
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
@ -562,8 +562,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
|
|||||||
DAG.getConstant(2, MVT::i32), // SWZ_Z
|
DAG.getConstant(2, MVT::i32), // SWZ_Z
|
||||||
DAG.getConstant(3, MVT::i32) // SWZ_W
|
DAG.getConstant(3, MVT::i32) // SWZ_W
|
||||||
};
|
};
|
||||||
return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(),
|
return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(), Args);
|
||||||
Args, 8);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// default for switch(IntrinsicID)
|
// default for switch(IntrinsicID)
|
||||||
@ -713,7 +712,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
|
|||||||
Op.getOperand(9),
|
Op.getOperand(9),
|
||||||
Op.getOperand(10)
|
Op.getOperand(10)
|
||||||
};
|
};
|
||||||
return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs, 19);
|
return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
|
||||||
}
|
}
|
||||||
case AMDGPUIntrinsic::AMDGPU_dp4: {
|
case AMDGPUIntrinsic::AMDGPU_dp4: {
|
||||||
SDValue Args[8] = {
|
SDValue Args[8] = {
|
||||||
@ -734,7 +733,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
|
|||||||
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
|
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
|
||||||
DAG.getConstant(3, MVT::i32))
|
DAG.getConstant(3, MVT::i32))
|
||||||
};
|
};
|
||||||
return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args, 8);
|
return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args);
|
||||||
}
|
}
|
||||||
|
|
||||||
case Intrinsic::r600_read_ngroups_x:
|
case Intrinsic::r600_read_ngroups_x:
|
||||||
@ -1112,7 +1111,7 @@ SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
DAG.getConstant(0, MVT::i32),
|
DAG.getConstant(0, MVT::i32),
|
||||||
Mask
|
Mask
|
||||||
};
|
};
|
||||||
SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src, 4);
|
SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src);
|
||||||
SDValue Args[3] = { Chain, Input, DWordAddr };
|
SDValue Args[3] = { Chain, Input, DWordAddr };
|
||||||
return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
|
return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
|
||||||
Op->getVTList(), Args, 3, MemVT,
|
Op->getVTList(), Args, 3, MemVT,
|
||||||
@ -1155,7 +1154,7 @@ SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
if (ValueVT.isVector()) {
|
if (ValueVT.isVector()) {
|
||||||
unsigned NumElemVT = ValueVT.getVectorNumElements();
|
unsigned NumElemVT = ValueVT.getVectorNumElements();
|
||||||
EVT ElemVT = ValueVT.getVectorElementType();
|
EVT ElemVT = ValueVT.getVectorElementType();
|
||||||
SDValue Stores[4];
|
SmallVector<SDValue, 4> Stores(NumElemVT);
|
||||||
|
|
||||||
assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
|
assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
|
||||||
"vector width in load");
|
"vector width in load");
|
||||||
@ -1172,7 +1171,7 @@ SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
Chain, Elem, Ptr,
|
Chain, Elem, Ptr,
|
||||||
DAG.getTargetConstant(Channel, MVT::i32));
|
DAG.getTargetConstant(Channel, MVT::i32));
|
||||||
}
|
}
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores, NumElemVT);
|
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores);
|
||||||
} else {
|
} else {
|
||||||
if (ValueVT == MVT::i8) {
|
if (ValueVT == MVT::i8) {
|
||||||
Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
|
Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
|
||||||
@ -1277,7 +1276,8 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
|
|||||||
NewVT = VT;
|
NewVT = VT;
|
||||||
NumElements = VT.getVectorNumElements();
|
NumElements = VT.getVectorNumElements();
|
||||||
}
|
}
|
||||||
Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT, Slots, NumElements);
|
Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT,
|
||||||
|
ArrayRef<SDValue>(Slots, NumElements));
|
||||||
} else {
|
} else {
|
||||||
// non-constant ptr can't be folded, keeps it as a v4f32 load
|
// non-constant ptr can't be folded, keeps it as a v4f32 load
|
||||||
Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
|
Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
|
||||||
@ -1357,7 +1357,7 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
|
|||||||
Loads[i] = DAG.getUNDEF(ElemVT);
|
Loads[i] = DAG.getUNDEF(ElemVT);
|
||||||
}
|
}
|
||||||
EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
|
EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
|
||||||
LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads, 4);
|
LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads);
|
||||||
} else {
|
} else {
|
||||||
LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
|
LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
|
||||||
Chain, Ptr,
|
Chain, Ptr,
|
||||||
@ -1479,7 +1479,7 @@ static SDValue CompactSwizzlableVector(
|
|||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
|
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
|
||||||
VectorEntry.getValueType(), NewBldVec, 4);
|
VectorEntry.getValueType(), NewBldVec);
|
||||||
}
|
}
|
||||||
|
|
||||||
static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
|
static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
|
||||||
@ -1517,7 +1517,7 @@ static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
|
|||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
|
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
|
||||||
VectorEntry.getValueType(), NewBldVec, 4);
|
VectorEntry.getValueType(), NewBldVec);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -1645,8 +1645,7 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
|
|||||||
}
|
}
|
||||||
|
|
||||||
// Return the new vector
|
// Return the new vector
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl,
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
|
||||||
VT, Ops.data(), Ops.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// Extract_vec (Build_vector) generated by custom lowering
|
// Extract_vec (Build_vector) generated by custom lowering
|
||||||
@ -1729,7 +1728,7 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
|
|||||||
};
|
};
|
||||||
SDLoc DL(N);
|
SDLoc DL(N);
|
||||||
NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG);
|
NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG);
|
||||||
return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs, 8);
|
return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs);
|
||||||
}
|
}
|
||||||
case AMDGPUISD::TEXTURE_FETCH: {
|
case AMDGPUISD::TEXTURE_FETCH: {
|
||||||
SDValue Arg = N->getOperand(1);
|
SDValue Arg = N->getOperand(1);
|
||||||
@ -1759,7 +1758,7 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
|
|||||||
};
|
};
|
||||||
NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG);
|
NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG);
|
||||||
return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, SDLoc(N), N->getVTList(),
|
return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, SDLoc(N), N->getVTList(),
|
||||||
NewArgs, 19);
|
NewArgs);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return SDValue();
|
return SDValue();
|
||||||
|
@ -431,8 +431,7 @@ SDValue SITargetLowering::LowerFormalArguments(
|
|||||||
for (unsigned j = 0; j != NumElements; ++j)
|
for (unsigned j = 0; j != NumElements; ++j)
|
||||||
Regs.push_back(DAG.getUNDEF(VT));
|
Regs.push_back(DAG.getUNDEF(VT));
|
||||||
|
|
||||||
InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT,
|
InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
|
||||||
Regs.data(), Regs.size()));
|
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -745,7 +744,7 @@ SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
|
|||||||
// build the new intrinsic call
|
// build the new intrinsic call
|
||||||
SDNode *Result = DAG.getNode(
|
SDNode *Result = DAG.getNode(
|
||||||
Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
|
Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
|
||||||
DAG.getVTList(Res), Ops.data(), Ops.size()).getNode();
|
DAG.getVTList(Res), Ops).getNode();
|
||||||
|
|
||||||
if (BR) {
|
if (BR) {
|
||||||
// Give the branch instruction our target
|
// Give the branch instruction our target
|
||||||
|
@ -235,8 +235,7 @@ SparcTargetLowering::LowerReturn_32(SDValue Chain,
|
|||||||
if (Flag.getNode())
|
if (Flag.getNode())
|
||||||
RetOps.push_back(Flag);
|
RetOps.push_back(Flag);
|
||||||
|
|
||||||
return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other,
|
return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
|
||||||
&RetOps[0], RetOps.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// Lower return values for the 64-bit ABI.
|
// Lower return values for the 64-bit ABI.
|
||||||
@ -315,8 +314,7 @@ SparcTargetLowering::LowerReturn_64(SDValue Chain,
|
|||||||
if (Flag.getNode())
|
if (Flag.getNode())
|
||||||
RetOps.push_back(Flag);
|
RetOps.push_back(Flag);
|
||||||
|
|
||||||
return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other,
|
return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
|
||||||
&RetOps[0], RetOps.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue SparcTargetLowering::
|
SDValue SparcTargetLowering::
|
||||||
@ -528,8 +526,7 @@ LowerFormalArguments_32(SDValue Chain,
|
|||||||
|
|
||||||
if (!OutChains.empty()) {
|
if (!OutChains.empty()) {
|
||||||
OutChains.push_back(Chain);
|
OutChains.push_back(Chain);
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
|
||||||
&OutChains[0], OutChains.size());
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -644,8 +641,7 @@ LowerFormalArguments_64(SDValue Chain,
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (!OutChains.empty())
|
if (!OutChains.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
|
||||||
&OutChains[0], OutChains.size());
|
|
||||||
|
|
||||||
return Chain;
|
return Chain;
|
||||||
}
|
}
|
||||||
@ -877,8 +873,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
|
|
||||||
// Emit all stores, make sure the occur before any copies into physregs.
|
// Emit all stores, make sure the occur before any copies into physregs.
|
||||||
if (!MemOpChains.empty())
|
if (!MemOpChains.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
|
||||||
&MemOpChains[0], MemOpChains.size());
|
|
||||||
|
|
||||||
// Build a sequence of copy-to-reg nodes chained together with token
|
// Build a sequence of copy-to-reg nodes chained together with token
|
||||||
// chain and flag operands which copy the outgoing args into registers.
|
// chain and flag operands which copy the outgoing args into registers.
|
||||||
@ -927,7 +922,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
if (InFlag.getNode())
|
if (InFlag.getNode())
|
||||||
Ops.push_back(InFlag);
|
Ops.push_back(InFlag);
|
||||||
|
|
||||||
Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
|
Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
|
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
|
||||||
@ -1194,8 +1189,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
|
|
||||||
// Emit all stores, make sure they occur before the call.
|
// Emit all stores, make sure they occur before the call.
|
||||||
if (!MemOpChains.empty())
|
if (!MemOpChains.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
|
||||||
&MemOpChains[0], MemOpChains.size());
|
|
||||||
|
|
||||||
// Build a sequence of CopyToReg nodes glued together with token chain and
|
// Build a sequence of CopyToReg nodes glued together with token chain and
|
||||||
// glue operands which copy the outgoing args into registers. The InGlue is
|
// glue operands which copy the outgoing args into registers. The InGlue is
|
||||||
@ -1245,7 +1239,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
|
|
||||||
// Now the call itself.
|
// Now the call itself.
|
||||||
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
|
Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, Ops);
|
||||||
InGlue = Chain.getValue(1);
|
InGlue = Chain.getValue(1);
|
||||||
|
|
||||||
// Revert the stack pointer immediately after the call.
|
// Revert the stack pointer immediately after the call.
|
||||||
@ -1914,7 +1908,7 @@ SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
|
|||||||
assert(Mask && "Missing call preserved mask for calling convention");
|
assert(Mask && "Missing call preserved mask for calling convention");
|
||||||
Ops.push_back(DAG.getRegisterMask(Mask));
|
Ops.push_back(DAG.getRegisterMask(Mask));
|
||||||
Ops.push_back(InFlag);
|
Ops.push_back(InFlag);
|
||||||
Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, &Ops[0], Ops.size());
|
Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, true),
|
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, true),
|
||||||
DAG.getIntPtrConstant(0, true), InFlag, DL);
|
DAG.getIntPtrConstant(0, true), InFlag, DL);
|
||||||
@ -2597,8 +2591,7 @@ static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
|
|||||||
SubRegOdd);
|
SubRegOdd);
|
||||||
SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
|
SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
|
||||||
SDValue(Lo64.getNode(), 1) };
|
SDValue(Lo64.getNode(), 1) };
|
||||||
SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
|
||||||
&OutChains[0], 2);
|
|
||||||
SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
|
SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
|
||||||
return DAG.getMergeValues(Ops, 2, dl);
|
return DAG.getMergeValues(Ops, 2, dl);
|
||||||
}
|
}
|
||||||
@ -2644,8 +2637,7 @@ static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
|
|||||||
LoPtr,
|
LoPtr,
|
||||||
MachinePointerInfo(),
|
MachinePointerInfo(),
|
||||||
false, false, alignment);
|
false, false, alignment);
|
||||||
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
|
||||||
&OutChains[0], 2);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
|
static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
|
||||||
|
@ -772,8 +772,8 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
|
|||||||
}
|
}
|
||||||
// Join the stores, which are independent of one another.
|
// Join the stores, which are independent of one another.
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
|
||||||
&MemOps[NumFixedFPRs],
|
ArrayRef<SDValue>(&MemOps[NumFixedFPRs],
|
||||||
SystemZ::NumArgFPRs - NumFixedFPRs);
|
SystemZ::NumArgFPRs-NumFixedFPRs));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -875,8 +875,7 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
|
|||||||
|
|
||||||
// Join the stores, which are independent of one another.
|
// Join the stores, which are independent of one another.
|
||||||
if (!MemOpChains.empty())
|
if (!MemOpChains.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
|
||||||
&MemOpChains[0], MemOpChains.size());
|
|
||||||
|
|
||||||
// Accept direct calls by converting symbolic call addresses to the
|
// Accept direct calls by converting symbolic call addresses to the
|
||||||
// associated Target* opcodes. Force %r1 to be used for indirect
|
// associated Target* opcodes. Force %r1 to be used for indirect
|
||||||
@ -919,8 +918,8 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
|
|||||||
// Emit the call.
|
// Emit the call.
|
||||||
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
if (IsTailCall)
|
if (IsTailCall)
|
||||||
return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, &Ops[0], Ops.size());
|
return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops);
|
||||||
Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
|
Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops);
|
||||||
Glue = Chain.getValue(1);
|
Glue = Chain.getValue(1);
|
||||||
|
|
||||||
// Mark the end of the call, which is glued to the call itself.
|
// Mark the end of the call, which is glued to the call itself.
|
||||||
@ -996,8 +995,7 @@ SystemZTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
if (Glue.getNode())
|
if (Glue.getNode())
|
||||||
RetOps.push_back(Glue);
|
RetOps.push_back(Glue);
|
||||||
|
|
||||||
return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other,
|
return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, RetOps);
|
||||||
RetOps.data(), RetOps.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue SystemZTargetLowering::
|
SDValue SystemZTargetLowering::
|
||||||
@ -1779,7 +1777,7 @@ SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
|
|||||||
Ops.push_back(Glue);
|
Ops.push_back(Glue);
|
||||||
|
|
||||||
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
|
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
|
||||||
return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, &Ops[0], Ops.size());
|
return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
|
SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
|
||||||
@ -1971,7 +1969,7 @@ SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
|
|||||||
false, false, 0);
|
false, false, 0);
|
||||||
Offset += 8;
|
Offset += 8;
|
||||||
}
|
}
|
||||||
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps, NumFields);
|
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
|
SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
|
||||||
|
@ -231,7 +231,7 @@ EmitTargetCodeForMemchr(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
|
|||||||
Ops.push_back(DAG.getConstant(SystemZ::CCMASK_SRST_FOUND, MVT::i32));
|
Ops.push_back(DAG.getConstant(SystemZ::CCMASK_SRST_FOUND, MVT::i32));
|
||||||
Ops.push_back(Glue);
|
Ops.push_back(Glue);
|
||||||
VTs = DAG.getVTList(PtrVT, MVT::Glue);
|
VTs = DAG.getVTList(PtrVT, MVT::Glue);
|
||||||
End = DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, &Ops[0], Ops.size());
|
End = DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
|
||||||
return std::make_pair(End, Chain);
|
return std::make_pair(End, Chain);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -376,8 +376,7 @@ static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
|
|||||||
else
|
else
|
||||||
Ops.push_back(Chain.getOperand(i));
|
Ops.push_back(Chain.getOperand(i));
|
||||||
SDValue NewChain =
|
SDValue NewChain =
|
||||||
CurDAG->getNode(ISD::TokenFactor, SDLoc(Load),
|
CurDAG->getNode(ISD::TokenFactor, SDLoc(Load), MVT::Other, Ops);
|
||||||
MVT::Other, &Ops[0], Ops.size());
|
|
||||||
Ops.clear();
|
Ops.clear();
|
||||||
Ops.push_back(NewChain);
|
Ops.push_back(NewChain);
|
||||||
}
|
}
|
||||||
@ -1992,7 +1991,7 @@ static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
|
|||||||
// Make a new TokenFactor with all the other input chains except
|
// Make a new TokenFactor with all the other input chains except
|
||||||
// for the load.
|
// for the load.
|
||||||
InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
|
InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
|
||||||
MVT::Other, &ChainOps[0], ChainOps.size());
|
MVT::Other, ChainOps);
|
||||||
}
|
}
|
||||||
if (!ChainCheck)
|
if (!ChainCheck)
|
||||||
return false;
|
return false;
|
||||||
|
@ -1933,8 +1933,7 @@ X86TargetLowering::LowerReturn(SDValue Chain,
|
|||||||
if (Flag.getNode())
|
if (Flag.getNode())
|
||||||
RetOps.push_back(Flag);
|
RetOps.push_back(Flag);
|
||||||
|
|
||||||
return DAG.getNode(X86ISD::RET_FLAG, dl,
|
return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
|
||||||
MVT::Other, &RetOps[0], RetOps.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
|
bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
|
||||||
@ -2427,13 +2426,11 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
|
|||||||
SaveXMMOps.push_back(Val);
|
SaveXMMOps.push_back(Val);
|
||||||
}
|
}
|
||||||
MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
|
MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
|
||||||
MVT::Other,
|
MVT::Other, SaveXMMOps));
|
||||||
&SaveXMMOps[0], SaveXMMOps.size()));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!MemOps.empty())
|
if (!MemOps.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
|
||||||
&MemOps[0], MemOps.size());
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -2699,8 +2696,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (!MemOpChains.empty())
|
if (!MemOpChains.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
|
||||||
&MemOpChains[0], MemOpChains.size());
|
|
||||||
|
|
||||||
if (Subtarget->isPICStyleGOT()) {
|
if (Subtarget->isPICStyleGOT()) {
|
||||||
// ELF / PIC requires GOT in the EBX register before function calls via PLT
|
// ELF / PIC requires GOT in the EBX register before function calls via PLT
|
||||||
@ -2799,8 +2795,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (!MemOpChains2.empty())
|
if (!MemOpChains2.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
|
||||||
&MemOpChains2[0], MemOpChains2.size());
|
|
||||||
|
|
||||||
// Store the return address to the appropriate stack slot.
|
// Store the return address to the appropriate stack slot.
|
||||||
Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
|
Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
|
||||||
@ -2937,10 +2932,10 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
// This isn't right, although it's probably harmless on x86; liveouts
|
// This isn't right, although it's probably harmless on x86; liveouts
|
||||||
// should be computed from returns not tail calls. Consider a void
|
// should be computed from returns not tail calls. Consider a void
|
||||||
// function making a tail call to a function returning int.
|
// function making a tail call to a function returning int.
|
||||||
return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
|
return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
|
Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
// Create the CALLSEQ_END node.
|
// Create the CALLSEQ_END node.
|
||||||
@ -4833,28 +4828,24 @@ static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
|
|||||||
if (Subtarget->hasInt256()) { // AVX2
|
if (Subtarget->hasInt256()) { // AVX2
|
||||||
SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
|
SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
|
||||||
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
|
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
|
||||||
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
|
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
|
||||||
array_lengthof(Ops));
|
|
||||||
} else {
|
} else {
|
||||||
// 256-bit logic and arithmetic instructions in AVX are all
|
// 256-bit logic and arithmetic instructions in AVX are all
|
||||||
// floating-point, no support for integer ops. Emit fp zeroed vectors.
|
// floating-point, no support for integer ops. Emit fp zeroed vectors.
|
||||||
SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
|
SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
|
||||||
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
|
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
|
||||||
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
|
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
|
||||||
array_lengthof(Ops));
|
|
||||||
}
|
}
|
||||||
} else if (VT.is512BitVector()) { // AVX-512
|
} else if (VT.is512BitVector()) { // AVX-512
|
||||||
SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
|
SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
|
||||||
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
|
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
|
||||||
Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
|
Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
|
||||||
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
|
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
|
||||||
} else if (VT.getScalarType() == MVT::i1) {
|
} else if (VT.getScalarType() == MVT::i1) {
|
||||||
assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
|
assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
|
||||||
SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
|
SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
|
||||||
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
|
SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
|
||||||
Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
|
|
||||||
Ops, VT.getVectorNumElements());
|
|
||||||
} else
|
} else
|
||||||
llvm_unreachable("Unexpected vector type");
|
llvm_unreachable("Unexpected vector type");
|
||||||
|
|
||||||
@ -4874,8 +4865,7 @@ static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
|
|||||||
if (VT.is256BitVector()) {
|
if (VT.is256BitVector()) {
|
||||||
if (HasInt256) { // AVX2
|
if (HasInt256) { // AVX2
|
||||||
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
|
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
|
||||||
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
|
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
|
||||||
array_lengthof(Ops));
|
|
||||||
} else { // AVX
|
} else { // AVX
|
||||||
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
|
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
|
||||||
Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
|
Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
|
||||||
@ -5854,18 +5844,14 @@ X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
SDLoc dl(Op);
|
SDLoc dl(Op);
|
||||||
if (ISD::isBuildVectorAllZeros(Op.getNode())) {
|
if (ISD::isBuildVectorAllZeros(Op.getNode())) {
|
||||||
SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
|
SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
|
||||||
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
|
SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
|
||||||
Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
|
|
||||||
Ops, VT.getVectorNumElements());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
if (ISD::isBuildVectorAllOnes(Op.getNode())) {
|
if (ISD::isBuildVectorAllOnes(Op.getNode())) {
|
||||||
SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
|
SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
|
||||||
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
|
SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
|
||||||
Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
|
|
||||||
Ops, VT.getVectorNumElements());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
bool AllContants = true;
|
bool AllContants = true;
|
||||||
@ -6125,9 +6111,11 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
|
EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
|
||||||
|
|
||||||
// Build both the lower and upper subvector.
|
// Build both the lower and upper subvector.
|
||||||
SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
|
SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
|
||||||
SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
|
ArrayRef<SDValue>(&V[0], NumElems/2));
|
||||||
NumElems/2);
|
SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
|
||||||
|
ArrayRef<SDValue>(&V[NumElems / 2],
|
||||||
|
NumElems/2));
|
||||||
|
|
||||||
// Recreate the wider vector with the lower and upper part.
|
// Recreate the wider vector with the lower and upper part.
|
||||||
if (VT.is256BitVector())
|
if (VT.is256BitVector())
|
||||||
@ -6414,8 +6402,7 @@ static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
|
|||||||
if (ShufVT != VT)
|
if (ShufVT != VT)
|
||||||
V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
|
V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
|
||||||
return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
|
return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
|
||||||
DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT,
|
DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
|
||||||
PshufbMask.data(), PshufbMask.size()));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// v8i16 shuffles - Prefer shuffles in the following order:
|
// v8i16 shuffles - Prefer shuffles in the following order:
|
||||||
@ -6717,7 +6704,7 @@ static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
|
|||||||
}
|
}
|
||||||
V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
|
V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
|
||||||
DAG.getNode(ISD::BUILD_VECTOR, dl,
|
DAG.getNode(ISD::BUILD_VECTOR, dl,
|
||||||
MVT::v16i8, &pshufbMask[0], 16));
|
MVT::v16i8, pshufbMask));
|
||||||
|
|
||||||
// As PSHUFB will zero elements with negative indices, it's safe to ignore
|
// As PSHUFB will zero elements with negative indices, it's safe to ignore
|
||||||
// the 2nd operand if it's undefined or zero.
|
// the 2nd operand if it's undefined or zero.
|
||||||
@ -6735,7 +6722,7 @@ static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
|
|||||||
}
|
}
|
||||||
V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
|
V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
|
||||||
DAG.getNode(ISD::BUILD_VECTOR, dl,
|
DAG.getNode(ISD::BUILD_VECTOR, dl,
|
||||||
MVT::v16i8, &pshufbMask[0], 16));
|
MVT::v16i8, pshufbMask));
|
||||||
return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
|
return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -7006,8 +6993,7 @@ LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
// Construct the output using a BUILD_VECTOR.
|
// Construct the output using a BUILD_VECTOR.
|
||||||
Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
|
Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
|
||||||
SVOps.size());
|
|
||||||
} else if (InputUsed[0] < 0) {
|
} else if (InputUsed[0] < 0) {
|
||||||
// No input vectors were used! The result is undefined.
|
// No input vectors were used! The result is undefined.
|
||||||
Output[l] = DAG.getUNDEF(NVT);
|
Output[l] = DAG.getUNDEF(NVT);
|
||||||
@ -7794,8 +7780,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
|
permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
|
SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
|
||||||
&permclMask[0], NumElems);
|
|
||||||
if (V2IsUndef)
|
if (V2IsUndef)
|
||||||
// Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
|
// Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
|
||||||
return DAG.getNode(X86ISD::VPERMV, dl, VT,
|
return DAG.getNode(X86ISD::VPERMV, dl, VT,
|
||||||
@ -8494,10 +8479,10 @@ GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
|
|||||||
|
|
||||||
if (InFlag) {
|
if (InFlag) {
|
||||||
SDValue Ops[] = { Chain, TGA, *InFlag };
|
SDValue Ops[] = { Chain, TGA, *InFlag };
|
||||||
Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
|
Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
|
||||||
} else {
|
} else {
|
||||||
SDValue Ops[] = { Chain, TGA };
|
SDValue Ops[] = { Chain, TGA };
|
||||||
Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
|
Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
// TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
|
// TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
|
||||||
@ -8681,7 +8666,7 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
SDValue Chain = DAG.getEntryNode();
|
SDValue Chain = DAG.getEntryNode();
|
||||||
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
SDValue Args[] = { Chain, Offset };
|
SDValue Args[] = { Chain, Offset };
|
||||||
Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
|
Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
|
||||||
|
|
||||||
// TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
|
// TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
|
||||||
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
|
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
|
||||||
@ -8809,11 +8794,11 @@ static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
|
|||||||
SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
|
SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
|
||||||
|
|
||||||
if (Op.getOpcode() == ISD::SHL_PARTS) {
|
if (Op.getOpcode() == ISD::SHL_PARTS) {
|
||||||
Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
|
Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
|
||||||
Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
|
Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
|
||||||
} else {
|
} else {
|
||||||
Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
|
Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
|
||||||
Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
|
Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue Ops[2] = { Lo, Hi };
|
SDValue Ops[2] = { Lo, Hi };
|
||||||
@ -9221,7 +9206,7 @@ X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
|
|||||||
MVT::i32, eax.getValue(2));
|
MVT::i32, eax.getValue(2));
|
||||||
SDValue Ops[] = { eax, edx };
|
SDValue Ops[] = { eax, edx };
|
||||||
SDValue pair = IsReplace
|
SDValue pair = IsReplace
|
||||||
? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
|
? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
|
||||||
: DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
|
: DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
|
||||||
return std::make_pair(pair, SDValue());
|
return std::make_pair(pair, SDValue());
|
||||||
}
|
}
|
||||||
@ -9417,8 +9402,7 @@ SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
for (unsigned j = 0; j < 8; ++j)
|
for (unsigned j = 0; j < 8; ++j)
|
||||||
pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
|
pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
|
||||||
}
|
}
|
||||||
SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
|
SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
|
||||||
&pshufbMask[0], 32);
|
|
||||||
In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
|
In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
|
||||||
In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
|
In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
|
||||||
|
|
||||||
@ -10015,7 +9999,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
|
|||||||
for (unsigned i = 0; i != NumOperands; ++i)
|
for (unsigned i = 0; i != NumOperands; ++i)
|
||||||
Ops.push_back(Op.getOperand(i));
|
Ops.push_back(Op.getOperand(i));
|
||||||
|
|
||||||
SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
|
SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
|
||||||
DAG.ReplaceAllUsesWith(Op, New);
|
DAG.ReplaceAllUsesWith(Op, New);
|
||||||
return SDValue(New.getNode(), 1);
|
return SDValue(New.getNode(), 1);
|
||||||
}
|
}
|
||||||
@ -10298,7 +10282,7 @@ static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
|
|||||||
ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
|
ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1.data(), ULTOp1.size());
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
|
||||||
}
|
}
|
||||||
|
|
||||||
static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
|
static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
|
||||||
@ -10865,7 +10849,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
// condition is true.
|
// condition is true.
|
||||||
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
|
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
|
||||||
SDValue Ops[] = { Op2, Op1, CC, Cond };
|
SDValue Ops[] = { Op2, Op1, CC, Cond };
|
||||||
return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
|
return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
|
static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
|
||||||
@ -11421,8 +11405,7 @@ SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
|
Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
|
||||||
MachinePointerInfo(SV, 16), false, false, 0);
|
MachinePointerInfo(SV, 16), false, false, 0);
|
||||||
MemOps.push_back(Store);
|
MemOps.push_back(Store);
|
||||||
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
|
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
|
||||||
&MemOps[0], MemOps.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
|
SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
|
||||||
@ -11576,7 +11559,7 @@ static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
|
|||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Elts[0], NumElts);
|
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
|
return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
|
||||||
@ -11608,7 +11591,7 @@ static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
|
|||||||
ShOps[0] = ShAmt;
|
ShOps[0] = ShAmt;
|
||||||
ShOps[1] = DAG.getConstant(0, MVT::i32);
|
ShOps[1] = DAG.getConstant(0, MVT::i32);
|
||||||
ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
|
ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
|
||||||
ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
|
ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
|
||||||
|
|
||||||
// The return type has to be a 128-bit type with the same element
|
// The return type has to be a 128-bit type with the same element
|
||||||
// type as the input type.
|
// type as the input type.
|
||||||
@ -12197,7 +12180,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
|
|||||||
}
|
}
|
||||||
SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
|
SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
|
||||||
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
|
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
|
||||||
SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
|
SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
|
||||||
SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
|
SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
|
||||||
DAG.getConstant(X86CC, MVT::i8),
|
DAG.getConstant(X86CC, MVT::i8),
|
||||||
SDValue(PCMP.getNode(), 1));
|
SDValue(PCMP.getNode(), 1));
|
||||||
@ -12214,7 +12197,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
|
|||||||
|
|
||||||
SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
|
SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
|
||||||
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
|
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
|
||||||
return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
|
return DAG.getNode(Opcode, dl, VTs, NewOps);
|
||||||
}
|
}
|
||||||
case Intrinsic::x86_fma_vfmadd_ps:
|
case Intrinsic::x86_fma_vfmadd_ps:
|
||||||
case Intrinsic::x86_fma_vfmadd_pd:
|
case Intrinsic::x86_fma_vfmadd_pd:
|
||||||
@ -12397,8 +12380,7 @@ static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
|
|||||||
SelectionDAG &DAG, const X86Subtarget *Subtarget,
|
SelectionDAG &DAG, const X86Subtarget *Subtarget,
|
||||||
SmallVectorImpl<SDValue> &Results) {
|
SmallVectorImpl<SDValue> &Results) {
|
||||||
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
SDValue TheChain = N->getOperand(0);
|
SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
|
||||||
SDValue rd = DAG.getNode(Opcode, DL, Tys, &TheChain, 1);
|
|
||||||
SDValue LO, HI;
|
SDValue LO, HI;
|
||||||
|
|
||||||
// The processor's time-stamp counter (a 64-bit MSR) is stored into the
|
// The processor's time-stamp counter (a 64-bit MSR) is stored into the
|
||||||
@ -12440,8 +12422,7 @@ static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
|
|||||||
|
|
||||||
// Use a buildpair to merge the two 32-bit values into a 64-bit one.
|
// Use a buildpair to merge the two 32-bit values into a 64-bit one.
|
||||||
SDValue Ops[] = { LO, HI };
|
SDValue Ops[] = { LO, HI };
|
||||||
SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops,
|
SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
|
||||||
array_lengthof(Ops));
|
|
||||||
Results.push_back(Pair);
|
Results.push_back(Pair);
|
||||||
Results.push_back(Chain);
|
Results.push_back(Chain);
|
||||||
}
|
}
|
||||||
@ -12485,7 +12466,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
|
|||||||
SDValue(Result.getNode(), 1) };
|
SDValue(Result.getNode(), 1) };
|
||||||
SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
|
SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
|
||||||
DAG.getVTList(Op->getValueType(1), MVT::Glue),
|
DAG.getVTList(Op->getValueType(1), MVT::Glue),
|
||||||
Ops, array_lengthof(Ops));
|
Ops);
|
||||||
|
|
||||||
// Return { result, isValid, chain }.
|
// Return { result, isValid, chain }.
|
||||||
return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
|
return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
|
||||||
@ -12828,7 +12809,7 @@ SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
|
|||||||
MachinePointerInfo(TrmpAddr, 22),
|
MachinePointerInfo(TrmpAddr, 22),
|
||||||
false, false, 0);
|
false, false, 0);
|
||||||
|
|
||||||
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
|
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
|
||||||
} else {
|
} else {
|
||||||
const Function *Func =
|
const Function *Func =
|
||||||
cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
|
cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
|
||||||
@ -12908,7 +12889,7 @@ SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
|
|||||||
MachinePointerInfo(TrmpAddr, 6),
|
MachinePointerInfo(TrmpAddr, 6),
|
||||||
false, false, 1);
|
false, false, 1);
|
||||||
|
|
||||||
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
|
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -13005,7 +12986,7 @@ static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
|
|||||||
DAG.getConstant(X86::COND_E, MVT::i8),
|
DAG.getConstant(X86::COND_E, MVT::i8),
|
||||||
Op.getValue(1)
|
Op.getValue(1)
|
||||||
};
|
};
|
||||||
Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
|
Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
|
||||||
|
|
||||||
// Finally xor with NumBits-1.
|
// Finally xor with NumBits-1.
|
||||||
Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
|
Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
|
||||||
@ -13057,7 +13038,7 @@ static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
|
|||||||
DAG.getConstant(X86::COND_E, MVT::i8),
|
DAG.getConstant(X86::COND_E, MVT::i8),
|
||||||
Op.getValue(1)
|
Op.getValue(1)
|
||||||
};
|
};
|
||||||
return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
|
return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
|
// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
|
||||||
@ -13249,7 +13230,7 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
|
|||||||
DAG.getConstant(uint8_t(-1U << ShiftAmt),
|
DAG.getConstant(uint8_t(-1U << ShiftAmt),
|
||||||
MVT::i8));
|
MVT::i8));
|
||||||
return DAG.getNode(ISD::AND, dl, VT, SHL,
|
return DAG.getNode(ISD::AND, dl, VT, SHL,
|
||||||
DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
|
DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
|
||||||
}
|
}
|
||||||
if (Op.getOpcode() == ISD::SRL) {
|
if (Op.getOpcode() == ISD::SRL) {
|
||||||
// Make a large shift.
|
// Make a large shift.
|
||||||
@ -13262,7 +13243,7 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
|
|||||||
DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
|
DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
|
||||||
MVT::i8));
|
MVT::i8));
|
||||||
return DAG.getNode(ISD::AND, dl, VT, SRL,
|
return DAG.getNode(ISD::AND, dl, VT, SRL,
|
||||||
DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
|
DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
|
||||||
}
|
}
|
||||||
if (Op.getOpcode() == ISD::SRA) {
|
if (Op.getOpcode() == ISD::SRA) {
|
||||||
if (ShiftAmt == 7) {
|
if (ShiftAmt == 7) {
|
||||||
@ -13275,7 +13256,7 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
|
|||||||
SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
|
SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
|
||||||
SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
|
SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
|
||||||
MVT::i8));
|
MVT::i8));
|
||||||
SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
|
SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
|
||||||
Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
|
Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
|
||||||
Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
|
Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
|
||||||
return Res;
|
return Res;
|
||||||
@ -13295,7 +13276,7 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
|
|||||||
DAG.getConstant(uint8_t(-1U << ShiftAmt),
|
DAG.getConstant(uint8_t(-1U << ShiftAmt),
|
||||||
MVT::i8));
|
MVT::i8));
|
||||||
return DAG.getNode(ISD::AND, dl, VT, SHL,
|
return DAG.getNode(ISD::AND, dl, VT, SHL,
|
||||||
DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
|
DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
|
||||||
}
|
}
|
||||||
if (Op.getOpcode() == ISD::SRL) {
|
if (Op.getOpcode() == ISD::SRL) {
|
||||||
// Make a large shift.
|
// Make a large shift.
|
||||||
@ -13308,7 +13289,7 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
|
|||||||
DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
|
DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
|
||||||
MVT::i8));
|
MVT::i8));
|
||||||
return DAG.getNode(ISD::AND, dl, VT, SRL,
|
return DAG.getNode(ISD::AND, dl, VT, SRL,
|
||||||
DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
|
DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
|
||||||
}
|
}
|
||||||
if (Op.getOpcode() == ISD::SRA) {
|
if (Op.getOpcode() == ISD::SRA) {
|
||||||
if (ShiftAmt == 7) {
|
if (ShiftAmt == 7) {
|
||||||
@ -13321,7 +13302,7 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
|
|||||||
SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
|
SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
|
||||||
SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
|
SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
|
||||||
MVT::i8));
|
MVT::i8));
|
||||||
SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
|
SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
|
||||||
Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
|
Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
|
||||||
Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
|
Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
|
||||||
return Res;
|
return Res;
|
||||||
@ -13589,7 +13570,7 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
|
|||||||
}
|
}
|
||||||
Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
|
Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
|
||||||
}
|
}
|
||||||
SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Elts[0], NumElems);
|
SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
|
||||||
return DAG.getNode(ISD::MUL, dl, VT, R, BV);
|
return DAG.getNode(ISD::MUL, dl, VT, R, BV);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -13753,10 +13734,8 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
|
|||||||
for (unsigned i = NumElems/2; i != NumElems; ++i)
|
for (unsigned i = NumElems/2; i != NumElems; ++i)
|
||||||
Amt2Csts.push_back(Amt->getOperand(i));
|
Amt2Csts.push_back(Amt->getOperand(i));
|
||||||
|
|
||||||
Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
|
Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
|
||||||
&Amt1Csts[0], NumElems/2);
|
Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
|
||||||
Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
|
|
||||||
&Amt2Csts[0], NumElems/2);
|
|
||||||
} else {
|
} else {
|
||||||
// Variable shift amount
|
// Variable shift amount
|
||||||
Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
|
Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
|
||||||
@ -14261,7 +14240,7 @@ ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
|
|||||||
DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
|
DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
|
||||||
cast<MemSDNode>(Node)->getMemOperand());
|
cast<MemSDNode>(Node)->getMemOperand());
|
||||||
SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
|
SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
|
||||||
Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
|
Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF));
|
||||||
Results.push_back(Result.getValue(2));
|
Results.push_back(Result.getValue(2));
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -14388,7 +14367,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
|
|||||||
Regs64bit ? X86::RDX : X86::EDX,
|
Regs64bit ? X86::RDX : X86::EDX,
|
||||||
HalfT, cpOutL.getValue(2));
|
HalfT, cpOutL.getValue(2));
|
||||||
SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
|
SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
|
||||||
Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
|
Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
|
||||||
Results.push_back(cpOutH.getValue(1));
|
Results.push_back(cpOutH.getValue(1));
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@ -18128,8 +18107,7 @@ static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
|
|||||||
(FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
|
(FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
|
||||||
SDValue Ops[] = { FalseOp, TrueOp,
|
SDValue Ops[] = { FalseOp, TrueOp,
|
||||||
DAG.getConstant(CC, MVT::i8), Flags };
|
DAG.getConstant(CC, MVT::i8), Flags };
|
||||||
return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
|
return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
|
||||||
Ops, array_lengthof(Ops));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// If this is a select between two integer constants, try to do some
|
// If this is a select between two integer constants, try to do some
|
||||||
@ -18259,8 +18237,7 @@ static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
|
|||||||
CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
|
CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
|
||||||
SDValue Ops[] = { FalseOp, Cond.getOperand(0),
|
SDValue Ops[] = { FalseOp, Cond.getOperand(0),
|
||||||
DAG.getConstant(CC, MVT::i8), Cond };
|
DAG.getConstant(CC, MVT::i8), Cond };
|
||||||
return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
|
return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
|
||||||
array_lengthof(Ops));
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -18611,7 +18588,7 @@ static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
|
|||||||
N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
|
N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
|
||||||
N1->getOperand(0));
|
N1->getOperand(0));
|
||||||
SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
|
SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
|
||||||
N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
|
N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
|
||||||
} else if (RHSTrunc) {
|
} else if (RHSTrunc) {
|
||||||
N1 = N1->getOperand(0);
|
N1 = N1->getOperand(0);
|
||||||
}
|
}
|
||||||
@ -18894,8 +18871,7 @@ static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
|
|||||||
SDValue Ops[] = { N0.getOperand(0), Neg,
|
SDValue Ops[] = { N0.getOperand(0), Neg,
|
||||||
DAG.getConstant(X86::COND_GE, MVT::i8),
|
DAG.getConstant(X86::COND_GE, MVT::i8),
|
||||||
SDValue(Neg.getNode(), 1) };
|
SDValue(Neg.getNode(), 1) };
|
||||||
return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
|
return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
|
||||||
Ops, array_lengthof(Ops));
|
|
||||||
}
|
}
|
||||||
return SDValue();
|
return SDValue();
|
||||||
}
|
}
|
||||||
@ -19052,8 +19028,7 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
|
|||||||
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
|
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
|
SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
|
||||||
Chains.size());
|
|
||||||
|
|
||||||
// Bitcast the loaded value to a vector of the original element type, in
|
// Bitcast the loaded value to a vector of the original element type, in
|
||||||
// the size of the target vector type.
|
// the size of the target vector type.
|
||||||
@ -19228,8 +19203,7 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
|
|||||||
Chains.push_back(Ch);
|
Chains.push_back(Ch);
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
|
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
|
||||||
Chains.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// Turn load->store of MMX types into GPR load/stores. This avoids clobbering
|
// Turn load->store of MMX types into GPR load/stores. This avoids clobbering
|
||||||
@ -19295,8 +19269,7 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
|
|||||||
SDValue NewChain = NewLd.getValue(1);
|
SDValue NewChain = NewLd.getValue(1);
|
||||||
if (TokenFactorIndex != -1) {
|
if (TokenFactorIndex != -1) {
|
||||||
Ops.push_back(NewChain);
|
Ops.push_back(NewChain);
|
||||||
NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
|
NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
|
||||||
Ops.size());
|
|
||||||
}
|
}
|
||||||
return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
|
return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
|
||||||
St->getPointerInfo(),
|
St->getPointerInfo(),
|
||||||
@ -19323,8 +19296,7 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
|
|||||||
if (TokenFactorIndex != -1) {
|
if (TokenFactorIndex != -1) {
|
||||||
Ops.push_back(LoLd);
|
Ops.push_back(LoLd);
|
||||||
Ops.push_back(HiLd);
|
Ops.push_back(HiLd);
|
||||||
NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
|
NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
|
||||||
Ops.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
LoAddr = St->getBasePtr();
|
LoAddr = St->getBasePtr();
|
||||||
|
@ -140,7 +140,7 @@ X86SelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
|
|||||||
|
|
||||||
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
|
SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
|
||||||
Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
|
Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops);
|
||||||
|
|
||||||
if (TwoRepStos) {
|
if (TwoRepStos) {
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
@ -154,7 +154,7 @@ X86SelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
|
|||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
Tys = DAG.getVTList(MVT::Other, MVT::Glue);
|
Tys = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag };
|
SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag };
|
||||||
Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
|
Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops);
|
||||||
} else if (BytesLeft) {
|
} else if (BytesLeft) {
|
||||||
// Handle the last 1 - 7 bytes.
|
// Handle the last 1 - 7 bytes.
|
||||||
unsigned Offset = SizeVal - BytesLeft;
|
unsigned Offset = SizeVal - BytesLeft;
|
||||||
@ -242,8 +242,7 @@ X86SelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
|
|||||||
|
|
||||||
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
|
SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
|
||||||
SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops,
|
SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops);
|
||||||
array_lengthof(Ops));
|
|
||||||
|
|
||||||
SmallVector<SDValue, 4> Results;
|
SmallVector<SDValue, 4> Results;
|
||||||
Results.push_back(RepMovs);
|
Results.push_back(RepMovs);
|
||||||
@ -264,6 +263,5 @@ X86SelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
|
|||||||
SrcPtrInfo.getWithOffset(Offset)));
|
SrcPtrInfo.getWithOffset(Offset)));
|
||||||
}
|
}
|
||||||
|
|
||||||
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Results);
|
||||||
&Results[0], Results.size());
|
|
||||||
}
|
}
|
||||||
|
@ -227,8 +227,7 @@ replaceInChain(SelectionDAG *CurDAG, SDValue Chain, SDValue Old, SDValue New)
|
|||||||
}
|
}
|
||||||
if (!found)
|
if (!found)
|
||||||
return SDValue();
|
return SDValue();
|
||||||
return CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other,
|
return CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, Ops);
|
||||||
&Ops[0], Ops.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
SDNode *XCoreDAGToDAGISel::SelectBRIND(SDNode *N) {
|
SDNode *XCoreDAGToDAGISel::SelectBRIND(SDNode *N) {
|
||||||
|
@ -886,7 +886,7 @@ LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
DAG.getCopyToReg(Chain, dl, HandlerReg, Handler)
|
DAG.getCopyToReg(Chain, dl, HandlerReg, Handler)
|
||||||
};
|
};
|
||||||
|
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 2);
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
|
||||||
|
|
||||||
return DAG.getNode(XCoreISD::EH_RETURN, dl, MVT::Other, Chain,
|
return DAG.getNode(XCoreISD::EH_RETURN, dl, MVT::Other, Chain,
|
||||||
DAG.getRegister(StackReg, MVT::i32),
|
DAG.getRegister(StackReg, MVT::i32),
|
||||||
@ -952,7 +952,7 @@ LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
|
|||||||
MachinePointerInfo(TrmpAddr, 16), false, false,
|
MachinePointerInfo(TrmpAddr, 16), false, false,
|
||||||
0);
|
0);
|
||||||
|
|
||||||
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 5);
|
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDValue XCoreTargetLowering::
|
SDValue XCoreTargetLowering::
|
||||||
@ -1111,7 +1111,7 @@ LowerCallResult(SDValue Chain, SDValue InFlag,
|
|||||||
unsigned index = ResultMemLocs[i].second;
|
unsigned index = ResultMemLocs[i].second;
|
||||||
SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
|
SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
|
||||||
SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, MVT::i32) };
|
SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, MVT::i32) };
|
||||||
SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops, 2);
|
SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops);
|
||||||
InVals[index] = load;
|
InVals[index] = load;
|
||||||
MemOpChains.push_back(load.getValue(1));
|
MemOpChains.push_back(load.getValue(1));
|
||||||
}
|
}
|
||||||
@ -1119,8 +1119,7 @@ LowerCallResult(SDValue Chain, SDValue InFlag,
|
|||||||
// Transform all loads nodes into one single node because
|
// Transform all loads nodes into one single node because
|
||||||
// all load nodes are independent of each other.
|
// all load nodes are independent of each other.
|
||||||
if (!MemOpChains.empty())
|
if (!MemOpChains.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
|
||||||
&MemOpChains[0], MemOpChains.size());
|
|
||||||
|
|
||||||
return Chain;
|
return Chain;
|
||||||
}
|
}
|
||||||
@ -1204,8 +1203,7 @@ XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
|
|||||||
// Transform all store nodes into one single node because
|
// Transform all store nodes into one single node because
|
||||||
// all store nodes are independent of each other.
|
// all store nodes are independent of each other.
|
||||||
if (!MemOpChains.empty())
|
if (!MemOpChains.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
|
||||||
&MemOpChains[0], MemOpChains.size());
|
|
||||||
|
|
||||||
// Build a sequence of copy-to-reg nodes chained together with token
|
// Build a sequence of copy-to-reg nodes chained together with token
|
||||||
// chain and flag operands which copy the outgoing args into registers.
|
// chain and flag operands which copy the outgoing args into registers.
|
||||||
@ -1244,7 +1242,7 @@ XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
|
|||||||
if (InFlag.getNode())
|
if (InFlag.getNode())
|
||||||
Ops.push_back(InFlag);
|
Ops.push_back(InFlag);
|
||||||
|
|
||||||
Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, &Ops[0], Ops.size());
|
Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, Ops);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
// Create the CALLSEQ_END node.
|
// Create the CALLSEQ_END node.
|
||||||
@ -1422,8 +1420,7 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
|
|||||||
|
|
||||||
// 2. chain CopyFromReg nodes into a TokenFactor.
|
// 2. chain CopyFromReg nodes into a TokenFactor.
|
||||||
if (!CFRegNode.empty())
|
if (!CFRegNode.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &CFRegNode[0],
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, CFRegNode);
|
||||||
CFRegNode.size());
|
|
||||||
|
|
||||||
// 3. Memcpy 'byVal' args & push final InVals.
|
// 3. Memcpy 'byVal' args & push final InVals.
|
||||||
// Aggregates passed "byVal" need to be copied by the callee.
|
// Aggregates passed "byVal" need to be copied by the callee.
|
||||||
@ -1452,8 +1449,7 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
|
|||||||
// 4, chain mem ops nodes into a TokenFactor.
|
// 4, chain mem ops nodes into a TokenFactor.
|
||||||
if (!MemOps.empty()) {
|
if (!MemOps.empty()) {
|
||||||
MemOps.push_back(Chain);
|
MemOps.push_back(Chain);
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0],
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
|
||||||
MemOps.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return Chain;
|
return Chain;
|
||||||
@ -1535,8 +1531,7 @@ XCoreTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
// Transform all store nodes into one single node because
|
// Transform all store nodes into one single node because
|
||||||
// all stores are independent of each other.
|
// all stores are independent of each other.
|
||||||
if (!MemOpChains.empty())
|
if (!MemOpChains.empty())
|
||||||
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
|
||||||
&MemOpChains[0], MemOpChains.size());
|
|
||||||
|
|
||||||
// Now handle return values copied to registers.
|
// Now handle return values copied to registers.
|
||||||
for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
|
for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
|
||||||
@ -1558,8 +1553,7 @@ XCoreTargetLowering::LowerReturn(SDValue Chain,
|
|||||||
if (Flag.getNode())
|
if (Flag.getNode())
|
||||||
RetOps.push_back(Flag);
|
RetOps.push_back(Flag);
|
||||||
|
|
||||||
return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
|
return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, RetOps);
|
||||||
&RetOps[0], RetOps.size());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
Loading…
Reference in New Issue
Block a user