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https://github.com/c64scene-ar/llvm-6502.git
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80 column cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96393 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
08d3561eee
commit
80dc116ce3
@ -523,7 +523,8 @@ multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
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Requires<[IsARM, HasV6]> {
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let Inst{11-10} = 0b00;
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}
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def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
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def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS,
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i32imm:$rot),
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IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
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[(set GPR:$dst, (opnode GPR:$LHS,
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(rotr GPR:$RHS, rot_imm:$rot)))]>,
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@ -771,7 +772,7 @@ def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
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"(${label}_${id}-(",
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"${:private}PCRELL${:uid}+8))\n"),
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!strconcat("${:private}PCRELL${:uid}:\n\t",
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"add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
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"add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
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[]> {
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let Inst{25} = 1;
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}
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@ -1066,8 +1067,8 @@ def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
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[(store GPR:$src, addrmode2:$addr)]>;
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// Stores with truncate
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def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, IIC_iStorer,
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"strh", "\t$src, $addr",
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def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
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IIC_iStorer, "strh", "\t$src, $addr",
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[(truncstorei16 GPR:$src, addrmode3:$addr)]>;
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def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
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@ -1596,7 +1597,7 @@ multiclass AI_smla<string opc, PatFrag opnode> {
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def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
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IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
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[(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
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(sra GPR:$b, (i32 16)))))]>,
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(sra GPR:$b, (i32 16)))))]>,
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Requires<[IsARM, HasV5TE]> {
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let Inst{5} = 0;
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let Inst{6} = 1;
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@ -2101,7 +2102,7 @@ def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
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// FIXME: Remove this when we can do generalized remat.
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let isReMaterializable = 1 in
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def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
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"movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
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"movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
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[(set GPR:$dst, (i32 imm:$src))]>,
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Requires<[IsARM, HasV6T2]>;
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@ -208,7 +208,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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let Inst{6-3} = 0b1110; // Rm = lr
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}
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// Alternative return instruction used by vararg functions.
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def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target", []>,
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def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target",[]>,
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T1Special<{1,1,0,?}>; // A6.2.3 & A8.6.25
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}
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@ -769,7 +769,7 @@ def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
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T1Misc<{0,0,1,0,1,0,?}>;
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// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
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// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
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// Expanded after instruction selection into a branch sequence.
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let usesCustomInserter = 1 in // Expanded after instruction selection.
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def tMOVCCr_pseudo :
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@ -371,7 +371,8 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
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/// for a binary operation that produces a value and use the carry
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/// bit. It's not predicable.
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let Uses = [CPSR] in {
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multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, bit Commutable = 0> {
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multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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bit Commutable = 0> {
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// shifted imm
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def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
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opc, "\t$dst, $lhs, $rhs",
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@ -411,7 +412,8 @@ multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, bit Comm
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// Carry setting variants
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let Defs = [CPSR] in {
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multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode, bit Commutable = 0> {
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multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
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bit Commutable = 0> {
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// shifted imm
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def Sri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
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opc, "\t$dst, $lhs, $rhs",
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@ -928,9 +930,9 @@ def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb),
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}
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// Store
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defm t2STR : T2I_st<0b10, "str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
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defm t2STRB : T2I_st<0b00, "strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
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defm t2STRH : T2I_st<0b01, "strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
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defm t2STR :T2I_st<0b10,"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
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defm t2STRB:T2I_st<0b00,"strb",BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
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defm t2STRH:T2I_st<0b01,"strh",BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
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// Store doubleword
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let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in
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@ -991,7 +993,7 @@ def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
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def t2LDM : T2XI<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
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IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb", []> {
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IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide}\t$addr, $wb", []> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b00;
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let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
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@ -1003,7 +1005,7 @@ def t2LDM : T2XI<(outs),
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let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
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def t2STM : T2XI<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
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IIC_iStorem, "stm${addr:submode}${p}${addr:wide}\t$addr, $wb", []> {
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IIC_iStorem, "stm${addr:submode}${p}${addr:wide}\t$addr, $wb", []> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b00;
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let Inst{24-23} = {?, ?}; // IA: '01', DB: '10'
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@ -1472,7 +1474,7 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
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def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
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!strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
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[(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
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(sra GPR:$b, (i32 16)))))]> {
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(sra GPR:$b, (i32 16)))))]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b001;
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@ -1496,7 +1498,7 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
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def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
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!strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
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[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
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(sra GPR:$b, (i32 16)))))]> {
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(sra GPR:$b, (i32 16)))))]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b001;
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@ -1508,7 +1510,7 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
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def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
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!strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
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[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
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(sext_inreg GPR:$b, i16)), (i32 16))))]> {
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(sext_inreg GPR:$b, i16)), (i32 16))))]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b011;
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@ -1520,7 +1522,7 @@ multiclass T2I_smla<string opc, PatFrag opnode> {
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def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
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!strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
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[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
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(sra GPR:$b, (i32 16))), (i32 16))))]> {
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(sra GPR:$b, (i32 16))), (i32 16))))]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0110;
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let Inst{22-20} = 0b011;
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@ -1541,8 +1543,8 @@ defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
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// Misc. Arithmetic Instructions.
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//
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class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
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InstrItinClass itin, string opc, string asm, list<dag> pattern>
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: T2I<oops, iops, itin, opc, asm, pattern> {
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let Inst{31-27} = 0b11111;
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let Inst{26-22} = 0b01010;
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