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https://github.com/c64scene-ar/llvm-6502.git
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Fix patterns for CVTTPS2DQ to specify SSE2 instead of SSE1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160941 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -366,7 +366,7 @@ class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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//
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//
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// SDI - SSE2 instructions with XD prefix.
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// SDI - SSE2 instructions with XD prefix.
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// SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
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// SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
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// SSDI - SSE2 instructions with XS prefix.
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// S2SI - SSE2 instructions with XS prefix.
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// SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
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// SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
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// PDI - SSE2 instructions with TB and OpSize prefixes.
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// PDI - SSE2 instructions with TB and OpSize prefixes.
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// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
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// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
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@ -379,10 +379,10 @@ class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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: Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
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: Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
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class SSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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: I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasSSE2]>;
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: I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasSSE2]>;
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class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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: Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
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: Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
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class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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@ -397,6 +397,10 @@ class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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: I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
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: I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
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Requires<[HasAVX]>;
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Requires<[HasAVX]>;
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class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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: I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
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Requires<[HasAVX]>;
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class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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: I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>, TB,
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: I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>, TB,
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@ -251,7 +251,7 @@ def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
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(iPTR 0))))))],
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(iPTR 0))))))],
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IIC_MMX_MOVQ_RR>;
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IIC_MMX_MOVQ_RR>;
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def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMSrcReg, (outs VR128:$dst),
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def MMX_MOVQ2DQrr : S2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst),
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(ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",
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(ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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[(set VR128:$dst,
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(v2i64 (scalar_to_vector
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(v2i64 (scalar_to_vector
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@ -259,7 +259,7 @@ def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMSrcReg, (outs VR128:$dst),
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IIC_MMX_MOVQ_RR>;
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IIC_MMX_MOVQ_RR>;
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let neverHasSideEffects = 1 in
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let neverHasSideEffects = 1 in
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def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMSrcReg, (outs FR64:$dst),
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def MMX_MOVQ2FR64rr: S2SIi8<0xD6, MRMSrcReg, (outs FR64:$dst),
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(ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}", [],
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(ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}", [],
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IIC_MMX_MOVQ_RR>;
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IIC_MMX_MOVQ_RR>;
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@ -1846,37 +1846,36 @@ def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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// Convert with truncation packed single/double fp to doubleword
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// Convert with truncation packed single/double fp to doubleword
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// SSE2 packed instructions with XS prefix
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// SSE2 packed instructions with XS prefix
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def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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[(set VR128:$dst,
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(int_x86_sse2_cvttps2dq VR128:$src))],
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(int_x86_sse2_cvttps2dq VR128:$src))],
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IIC_SSE_CVT_PS_RR>, VEX;
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def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvttps2dq
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(memopv4f32 addr:$src)))],
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IIC_SSE_CVT_PS_RM>, VEX;
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def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR256:$dst,
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(int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
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IIC_SSE_CVT_PS_RR>, VEX;
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IIC_SSE_CVT_PS_RR>, VEX;
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def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvttps2dq
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[(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
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(memopv4f32 addr:$src)))],
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(memopv8f32 addr:$src)))],
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IIC_SSE_CVT_PS_RM>, VEX;
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IIC_SSE_CVT_PS_RM>, VEX;
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def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR256:$dst,
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(int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
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IIC_SSE_CVT_PS_RR>, VEX;
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def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
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(memopv8f32 addr:$src)))],
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IIC_SSE_CVT_PS_RM>, VEX;
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def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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[(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
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(int_x86_sse2_cvttps2dq VR128:$src))],
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IIC_SSE_CVT_PS_RR>;
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IIC_SSE_CVT_PS_RR>;
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def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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[(set VR128:$dst,
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(int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
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(int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
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IIC_SSE_CVT_PS_RM>;
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IIC_SSE_CVT_PS_RM>;
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let Predicates = [HasAVX] in {
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let Predicates = [HasAVX] in {
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def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
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def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
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@ -2009,29 +2008,29 @@ def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
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// Convert Packed DW Integers to Packed Double FP
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// Convert Packed DW Integers to Packed Double FP
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let Predicates = [HasAVX] in {
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let Predicates = [HasAVX] in {
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let neverHasSideEffects = 1, mayLoad = 1 in
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let neverHasSideEffects = 1, mayLoad = 1 in
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def VCVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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"vcvtdq2pd\t{$src, $dst|$dst, $src}",
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"vcvtdq2pd\t{$src, $dst|$dst, $src}",
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[]>, VEX;
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[]>, VEX;
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def VCVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"vcvtdq2pd\t{$src, $dst|$dst, $src}",
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"vcvtdq2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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[(set VR128:$dst,
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(int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX;
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(int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX;
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def VCVTDQ2PDYrm : SSDI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
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def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
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"vcvtdq2pd\t{$src, $dst|$dst, $src}",
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"vcvtdq2pd\t{$src, $dst|$dst, $src}",
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[(set VR256:$dst,
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[(set VR256:$dst,
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(int_x86_avx_cvtdq2_pd_256
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(int_x86_avx_cvtdq2_pd_256
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(bitconvert (memopv2i64 addr:$src))))]>, VEX;
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(bitconvert (memopv2i64 addr:$src))))]>, VEX;
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def VCVTDQ2PDYrr : SSDI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
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def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
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"vcvtdq2pd\t{$src, $dst|$dst, $src}",
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"vcvtdq2pd\t{$src, $dst|$dst, $src}",
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[(set VR256:$dst,
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[(set VR256:$dst,
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(int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX;
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(int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX;
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}
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}
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let neverHasSideEffects = 1, mayLoad = 1 in
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let neverHasSideEffects = 1, mayLoad = 1 in
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def CVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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"cvtdq2pd\t{$src, $dst|$dst, $src}", [],
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"cvtdq2pd\t{$src, $dst|$dst, $src}", [],
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IIC_SSE_CVT_PD_RR>;
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IIC_SSE_CVT_PD_RR>;
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def CVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtdq2pd\t{$src, $dst|$dst, $src}",
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"cvtdq2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
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[(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
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IIC_SSE_CVT_PD_RM>;
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IIC_SSE_CVT_PD_RM>;
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@ -4547,7 +4546,7 @@ def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
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// Bitcast FR64 <-> GR64
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// Bitcast FR64 <-> GR64
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//
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//
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let Predicates = [HasAVX] in
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let Predicates = [HasAVX] in
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def VMOV64toSDrm : SSDI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
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def VMOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
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"vmovq\t{$src, $dst|$dst, $src}",
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"vmovq\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
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[(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
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VEX;
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VEX;
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@ -4560,7 +4559,7 @@ def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
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[(store (i64 (bitconvert FR64:$src)), addr:$dst)],
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[(store (i64 (bitconvert FR64:$src)), addr:$dst)],
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IIC_SSE_MOVDQ>, VEX;
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IIC_SSE_MOVDQ>, VEX;
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def MOV64toSDrm : SSDI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
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def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
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"movq\t{$src, $dst|$dst, $src}",
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"movq\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
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[(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
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IIC_SSE_MOVDQ>;
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IIC_SSE_MOVDQ>;
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