6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
Code Issues Projects Releases Wiki Activity

Change name of class to ArithOverflowR.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141743 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-10-11 23:43:48 +00:00
parent 2dfd3a9789
commit 80eb994929
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/Mips/MipsInstrInfo.td
View File

@ -260,7 +260,7 @@ class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
let isCommutable = isComm;
}
class ArithLogicOfR<bits<6> op, bits<6> func, string instr_asm,
class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
!strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> {
@ -616,8 +616,8 @@ def LUi : LoadUpper<0x0f, "lui">;
/// Arithmetic Instructions (3-Operand, R-Type)
def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;
def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>;
def ADD : ArithLogicOfR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
def SUB : ArithLogicOfR<0x00, 0x22, "sub", IIAlu, CPURegs>;
def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>;
def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;